CN118801218A - A semiconductor laser structure with dual-gate control and preparation method - Google Patents

Abstract

The application provides a semiconductor laser structure with double gate control and a preparation method thereof, wherein the structure comprises a substrate, a buffer layer, a nitride epitaxial DBR and an N-type semiconductor transmission layer, wherein a multi-quantum well layer is arranged at the upper part of the N-type semiconductor transmission layer, a ferroelectric material and an N-type ohmic electrode are arranged at the upper part of the exposed N-type semiconductor transmission layer, a ferroelectric material electrode is arranged at the upper part of the ferroelectric material, a P-type current blocking layer and a P-type semiconductor transmission layer are sequentially arranged at the upper part of the multi-quantum well layer, a current limiting hole structure layer is arranged at the upper surface of the P-type semiconductor transmission layer, and a current expansion layer covers the P-type semiconductor transmission layer and the current limiting hole structure layer; the upper side of the current expansion layer is provided with a dielectric DBR and a P-type ohmic electrode; the application can enhance the VCSEL current control capability, effectively prevent the reverse leakage of the device, inhibit the leakage level of the active region and improve the reliability and stability of the device.

Description

A semiconductor laser structure with dual-gate control and preparation method

Technical Field

The present application relates to the technical field of semiconductor lasers, and in particular to a semiconductor laser structure with dual-gate control and a preparation method thereof.

Background Art

Since the concept was proposed in 1977, Vertical Cavity Surface Emitting Laser (VCSEL) has attracted close attention from researchers due to its advantages such as small threshold current, excellent beam quality and strong directionality, and has been widely used in laser display, lidar, optical communication and other fields. At present, the development of GaAs-based VCSEL has gradually matured and has been successfully commercialized. However, the short-wave VCSEL technology based on GaN wide-bandgap semiconductors still has many shortcomings and there is still a long way to go before commercial application and promotion.

Research shows that electron leakage is an important reason for the deterioration of GaN-based VCSEL luminous efficiency. First, due to lattice mismatch and thermal expansion coefficient mismatch, GaN-based VCSEL devices have a large number of defects such as threading dislocations inside the device. These defects will form leakage channels to a certain extent, increasing the leakage level of the device. Second, since the mobility of electrons is much greater than the mobility of holes, and the p-type doping efficiency in GaN materials is much lower than the n-type doping efficiency, this leads to extremely uneven distribution of electron and hole concentrations in the active region. Most electrons tend to undergo non-radiative recombination or escape from the active region and leak into the p-region, resulting in a deterioration of VCSEL luminous efficiency. It is worth noting that the above problems will become more prominent due to the self-heating effect and polarization effect of the device, which seriously restricts the development of GaN-based VCSEL devices.

In order to alleviate the electron leakage phenomenon in the active area, current VCSEL devices usually adopt a p-type electron blocking layer (EBL) design, which uses the barrier energy difference in the conduction band to prevent electrons from escaping the active area. However, the p-EBL design will also increase the barrier height that hinders hole injection in the valence band, resulting in a large number of holes being unable to be efficiently transported to the active area. Therefore, the composition and thickness of the p-EBL have always been the focus of researchers' optimization. For this reason, superlattice p-EBL, component gradient p-EBL and other architectures have been proposed to balance the problems of electron leakage and hole injection. However, the operational space of this measure is limited, and the optimal window value of the variable requires a lot of exploration.

The applicant has conducted a detailed search of the prior art and has not found any patent application related to the present application; therefore, effectively preventing the reverse leakage of the device and suppressing the leakage level in the active area are still urgent issues to be resolved.

Therefore, it is necessary to provide a new technical solution to solve the above technical problems.

Summary of the invention

The present invention provides a semiconductor laser structure with dual-gate control, wherein the dual gates refer to two layers of AlGaN with different components as polarization gates and a ferroelectric material as another gate; even if one of the gates is controlled by a ferroelectric material electrode, the other gate is formed by two N-type semiconductor transmission layers with specific components forming polarized negative charges at the interface between the two, which plays a role in depleting electrons.

The semiconductor laser comprises a substrate, a buffer layer, a nitride epitaxial DBR, and an N-type semiconductor transmission layer in sequence along the epitaxial growth direction; a multi-quantum well layer is arranged on the upper part of the N-type semiconductor transmission layer; a ferroelectric material and an N-type ohmic electrode are arranged on the upper part of the exposed N-type semiconductor transmission layer; a ferroelectric material electrode is arranged on the upper part of the ferroelectric material; a P-type current blocking layer and a P-type semiconductor transmission layer are arranged in sequence on the upper part of the multi-quantum well layer; the outer side of the upper surface of the P-type semiconductor transmission layer is an annular insulating layer as a current limiting hole structure layer; a current expansion layer covers the P-type semiconductor transmission layer and the current limiting hole structure layer; a dielectric DBR and a P-type ohmic electrode are arranged on the upper side of the current expansion layer; and the projection area of the dielectric DBR is smaller than that of the current expansion layer.

As a preferred solution, the projection area of the dielectric DBR is 0.5-0.9 of the area of the current spreading layer.

As a preferred solution, the material of the substrate is sapphire, SiC, Si, AlN, GaN or quartz glass.

As a preferred solution, the buffer layer is made of _{Alx1Gay1In1 -x1-y1N} , wherein 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, _and has a thickness of 10-500nm.

As a preferred scheme, the nitride epitaxial DBR is composed of Al _x2 Ga _y2 In _1-x2-y2 N and Al _x3 Ga _y3 In _1-x3-y3 N alternately, the thickness of Al _x2 Ga _y2 In _1-x2-y2 N and Al _x3 Ga _y3 In _1-x3-y3 N are respectively one-fourth of the wavelength of the required light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; wherein, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1.

As a preferred scheme, the N-type semiconductor transport layer is composed of _{Alx4Gay4In1 -x4-y4N and Alx5Gay5In1 -x5- y5N} along the growth direction, wherein 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1, 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4＞x5; a multi-quantum well layer, a ferroelectric material and an N-type _ohmic electrode are arranged above the _{Alx5Gay5In1 -x5-y5N} layer.

As a preferred solution, the thickness of the _{Alx4Gay4In1 -x4-y4N is} 50nm-5μm, and the thickness of the _{Alx5Gay5In1 -x5-y5N is} 50nm-2μm.

As a preferred solution, the ferroelectric material is AlScN.

As a preferred solution, the thickness of the ferroelectric material is 5-100 nm.

As a preferred scheme, the multi-quantum well layer is composed of quantum wells _{Alx6Iny6Ga1 -x6-y6N and} quantum barriers _{Alx7Iny7Ga1 -x7-y7N ,} wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of quantum wells is greater than or equal to 1.

As a preferred solution, the thickness of the quantum well _{Alx6Iny6Ga1 -x6-y6N is} 1-10nm, and the thickness of the quantum barrier _{Alx7Iny7Ga1 -x7-y7N is} 5-50nm.

As a preferred solution, the material of the N-type ohmic electrode is Al/Au or Cr/Au.

As a preferred solution, the material of the P-type current blocking layer is _{Alx8Iny8Ga1 -x8-y8N ,} wherein 0≤x8≤1, 0≤y8≤1, and 0≤1-x8-y8≤1.

As a preferred solution, the thickness of the P-type current blocking layer is 10-100 nm.

As a preferred solution, the material of the P-type _{semiconductor} transport layer is _{Alx9Iny9Ga1 -x9-y9N} , wherein 0≤x9≤1, 0≤y9≤1, and 0≤1-x9-y9≤1.

As a preferred solution, the thickness of the P-type semiconductor transport layer is 50-300 nm.

As a preferred solution, the material of the current limiting aperture structure layer is SiO ₂ .

As a preferred solution, the current limiting pore structure layer has a thickness of 10-100 nm.

As a preferred solution, the material of the current spreading layer is one of ITO, Ni/Au, zinc oxide, graphene, aluminum or metal nanowires.

As a preferred solution, the thickness of the current spreading layer is 10-100 nm.

As a preferred solution, the material of the dielectric DBR is Ta ₂ O ₅ /SiO ₂ or TiO ₂ /SiO ₂ .

As a preferred solution, the thickness of Ta ₂ O ₅ /SiO ₂ or TiO ₂ /SiO ₂ is respectively one quarter of the wavelength of the desired luminous wavelength in the medium, and the number of periods is greater than or equal to one.

As a preferred solution, the material of the P-type ohmic electrode is one of Ni/Au, Cr/Au, Pt/Au, and Ni/Al.

A method for preparing a semiconductor laser structure with dual-gate control comprises the following steps:

S1, in an MOCVD reactor, growing a buffer layer, a nitride epitaxial DBR, an N-type semiconductor transport layer, a quantum well layer, a P-type current blocking layer, and a P-type semiconductor transport layer on the surface of the substrate respectively;

S2, on the P-type semiconductor transmission layer, a step is formed by photolithography and etching process to expose the N-type semiconductor transmission layer;

S3, depositing and growing a current limiting hole structure layer on the P-type semiconductor transport layer;

S4, evaporating a current spreading layer on the current limiting hole structure layer;

S5, atomic layer deposition of dielectric DBR on the current spreading layer;

S6, based on S5, depositing ferroelectric material on the exposed N-type semiconductor transport layer through photolithography and etching technology;

S7, evaporating and photolithography to form a ferroelectric material electrode on the ferroelectric material; and evaporating and photolithography to form a P-type ohmic electrode and an N-type ohmic electrode on the exposed current spreading layer and the N-type semiconductor transmission layer, respectively.

As a preferred solution, in S2, 60%-80% of the N-type semiconductor transport layer is exposed.

As a preferred scheme, the N-type semiconductor transport layer is composed of _{Alx4Gay4In1 -x4-y4N} and _{Alx5Gay5In1 -x5- y5N} along the growth direction, wherein 0≤x4≤1, 0≤y4≤10, 0≤1-x4-y4≤1, 0≤x5≤1 _, 0≤y5≤1, 0≤1-x5-y5≤1 and x4＞x5; a multi-quantum well layer, a ferroelectric material and an N-type _ohmic electrode are arranged above the _{Alx5Gay5In1 -x5-y5N} layer.

As a preferred solution, the thickness of the _{Alx4Gay4In1 -x4-y4N is} 50nm-5μm, and the thickness of the _{Alx5Gay5In1 -x5-y5N is} 50nm-2μm.

As a preferred solution, the ferroelectric material is AlScN.

As a preferred solution, the thickness of the ferroelectric material is 5-100 nm.

The present application deposits a layer of ferroelectric material on the surface of the N-semiconductor transmission layer of the VCSEL, and adopts an N-region composition with a specific component gradient, making full use of the piezoelectric properties and polarization effect of the ferroelectric material to act as a double-gate effect to control the opening and closing of the conductive channel; the current control capability of the VCSEL can be enhanced, the reverse leakage of the device can be effectively prevented, the leakage level of the active area can be suppressed, and the reliability and stability of the device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of device current when no bias is applied to the ferroelectric material;

FIG2 is a schematic diagram of device current when a reverse bias is applied to a ferroelectric material;

FIG3 is a schematic diagram of device current when a forward bias is applied to a ferroelectric material;

FIG4 is a schematic diagram of a semiconductor laser structure with dual-gate control according to the present application;

FIG5 is a schematic diagram of the epitaxial wafer structure in which a step is made on a P-type semiconductor transport layer by photolithography and etching processes to expose an N-type semiconductor transport layer in the present invention;

FIG6 is a schematic diagram of an epitaxial wafer structure in which an insulating layer is grown by deposition on a P-type semiconductor transmission layer and a current limiting hole structure layer is photoetched in the present invention;

FIG7 is a schematic diagram of the structure of an epitaxial wafer for producing a patterned current spreading layer by photolithography and etching in the present invention;

FIG8 is a schematic diagram of the structure of an epitaxial wafer of a patterned ferroelectric material produced by photolithography and etching in the present invention;

Among them, 101, substrate; 102, buffer layer; 103, nitride epitaxial DBR; 104, N-type semiconductor transport layer; 106, ferroelectric material; 107, multi-quantum well layer; 108, P-type current blocking layer; 109, P-type semiconductor transport layer; 110, current limiting pore structure layer; 111, current spreading layer; 112, dielectric DBR; 113, P-type ohmic electrode; 114, N-type ohmic electrode; 115, ferroelectric material electrode.

DETAILED DESCRIPTION

The specific implementation of the present invention is described in detail below in conjunction with Figures 1 to 8. It should be noted that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

Embodiment 1:

The present invention provides a semiconductor laser structure with dual-gate control, wherein the dual gates refer to two layers of AlGaN with different components constituting an N-type semiconductor transport layer as polarization gates, and another gate of a ferroelectric material 106; that is, one of the gates is controlled by a ferroelectric material electrode 115, and the other gate is formed by polarization negative charges formed at the interface between the two specific components of the two N-type semiconductor transport layers, which plays a role in depleting electrons.

The semiconductor laser comprises a circular substrate 101, a buffer layer 102, a nitride epitaxial DBR 103, and an N-type semiconductor transmission layer 104 in sequence along the epitaxial growth direction. Preferably, the material of the substrate 101 is one of sapphire, SiC, Si, AlN, GaN or quartz glass, and the substrate 101 can be divided into a polar surface substrate and a semi-polar surface substrate along the epitaxial growth direction; the material of the buffer layer 102 is Al _x1 Ga _y1 In _1-x1-y1 N, wherein 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 10-500nm; the material of the nitride epitaxial DBR 103 is composed of Al _x2 Ga _y2 In _1-x2-y2 N and Al _x3 Ga _y3 In _1-x3-y3 N alternately, and Al _x2 Ga _y2 In _1-x2-y2 N and Al _x3 Ga _y3 In The thickness of _1-x3-y3 N is one quarter of the wavelength of the desired luminous wavelength in the medium, and the number of periods is greater than or equal to 1; wherein, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1;

A multi-quantum well layer 107 is arranged on the upper part of the N-type semiconductor transmission layer 104. Preferably, the multi-quantum well layer 107 is composed of quantum wells _{Alx6Iny6Ga1 -x6-y6N and} quantum barriers _Alx7Iny7Ga1 - _{x7-y7N ,} wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the _quantum well, and the number of quantum wells is greater than or equal to 1; the thickness of the quantum well _{Alx6Iny6Ga1 -x6-y6N} is 1-10nm, and the thickness of the quantum barrier _{Alx7Iny7Ga1 -x7-y7N is} 5-50nm;

The exposed N-type semiconductor transmission layer 104 is provided with a ferroelectric material 106 and an N-type ohmic electrode 114 on the upper part. The ferroelectric material 106 is AlScN, and the thickness of the ferroelectric material 106 is 5-100nm; the annular N-type ohmic electrode 114 is located outside the exposed part of the N-type semiconductor transmission layer 104, and the width is preferably 0.1-1μm. The material of the N-type ohmic electrode is Al/Au or Cr/Au; the ferroelectric material 106 is provided with a ferroelectric material electrode 115 on the upper part, and the P-type current blocking layer 108 and the P-type semiconductor transmission layer 109 are sequentially provided on the upper part of the multi-quantum well layer 107. Preferably, the material of the P-type current blocking layer 108 is Al _x8 In _y8 Ga _1-x8-y8 N, wherein 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8≤1; the thickness of the P-type current blocking layer 108 is 10-100nm, the material of the P-type semiconductor transmission layer 109 is Al _x9 In _y9 Ga _1-x9-y9 N, wherein 0≤x9≤1, 0≤y9≤1, 0≤1-x9-y9≤1, and the thickness of the P-type semiconductor transmission layer 109 is 50-300nm; the outer side of the upper surface of the P-type semiconductor transmission layer 109 is an annular insulating layer, which serves as a current limiting hole structure layer 110. The current limiting hole structure layer 110 is a high dielectric constant insulating layer, and the material is preferably SiO ₂ , the thickness of the current limiting hole structure layer 110 is 10-100nm; the width of the ring is 2-200μm; the current spreading layer 111 covers the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110; preferably, the material of the current spreading layer 111 is one of ITO, Ni/Au, zinc oxide, graphene, aluminum or metal nanowires, and the thickness of the current spreading layer 111 is 10-100nm; a dielectric DBR 112 and a P-type ohmic electrode 113 are arranged on the upper side of the current spreading layer 111, and the projection area of the dielectric DBR 112 is smaller than the area of the current spreading layer 111. Preferably, the projection area of the dielectric DBR 112 is 0.5-0.9 of the area of the current spreading layer 111; the material of the dielectric DBR 112 is Ta ₂ O ₅ /SiO ₂ or TiO ₂ /SiO ₂ ; when Ta ₂ O ₅ /SiO ₂ is used, Ta ₂ O ₅ , and SiO ₂ are respectively one-fourth of the wavelength of the desired light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; when TiO ₂ /SiO ₂ is used, the thicknesses of TiO ₂ and SiO ₂ are respectively one-fourth of the wavelength of the desired light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; the annular P-type ohmic electrode 113 is located outside the current spreading layer 111, with a width of 0.1-2 μm, and the material of the P-type ohmic electrode 113 is one of Ni/Au, Cr/Au, Pt/Au, and Ni/Al.

The N-type semiconductor transport layer 104 is composed of Al _x4 Ga _y4 In _1-x4-y4 N and Al _x5 Ga _y5 In _1-x5-y5 N along the growth direction, wherein 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1; 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4＞x5, the thickness of Al _x4 Ga _y4 In _1-x4-y4 N is 50nm-5μm, and the thickness of Al _x5 Ga _y5 In _1-x5-y5 N is 50nm-2μm; a ferroelectric material 106 of 5-100nm is deposited on the Al _x5 Ga _y5 In _1-x5-y5 N layer, and the ferroelectric material 106 is preferably AlScN; the composition gradient will cause Al _x4 Ga _y4 In _1-x4-y4 N/Al _x5 Ga _y5 In There are a large number of negatively polarized interface charges at the _1-x5-y5 N interface, which forms a space depletion for electrons; secondly, the type and concentration of interface charges between the ferroelectric material 106 and the Al _x5 Ga _y5 In _1-x5-y5 N layer vary with the direction and intensity of the external electric field.

The device in this embodiment deposits a layer of _{ferroelectric} material 106 on the N-type semiconductor transport layer 104. On the one hand, _{Alx4Gay4In1 -x4-y4N is used as the polarization gate. A negative interface charge is formed at the interface due to the difference in composition, thereby forming a depletion effect on electrons, as shown in FIG1 . On the other hand, a layer of ferroelectric material 106 is etched and deposited on the low Al component Alx5Gay5In1 - x5-y5N} layer. The ferroelectric material 106 has special piezoelectric properties, which makes its interface polarization charge and polarization intensity change with the direction and intensity of the external electric field, thereby affecting the accumulation and depletion of electrons thereunder, as shown in FIG2 . Therefore, under the joint action of the upper and lower double gate electrodes, the opening and closing control effect of the N-side electron transport channel can be achieved, thereby regulating the electron transport efficiency, which can not only suppress the electron leakage problem in the active area, but also greatly reduce the reverse leakage of the device.

Embodiment 2:

This embodiment provides a method for preparing a semiconductor laser structure with dual-gate control, comprising the following steps:

S1, in a MOCVD reactor, baking the substrate 101 at 1250° C.-1350° C., removing foreign matter on the surface of the substrate 101, and then growing a buffer layer 102, a nitride epitaxial DBR 103, an N-type semiconductor transport layer 104, a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transport layer 109 on the surface of the substrate 101;

S2, on the P-type semiconductor transmission layer 109, a step is formed by photolithography and etching process to expose the N-type semiconductor transmission layer 104, preferably, 60% to 80% of the N-type semiconductor transmission layer 104 is exposed;

S3, depositing and growing a current limiting hole structure layer 110 on the P-type semiconductor transmission layer 109; preferably, the thickness of the current limiting hole structure layer 110 is 10-100 nm, and the insulating material used for the current limiting hole structure layer 110 is SiO ₂ , and then etching a ring pattern on the insulating material using photolithography technology, the pattern covers along the edge of the P-type semiconductor transmission layer 109, and the width of the ring is 2-200 μm;

S4, evaporating a current spreading layer 111 on the current limiting hole structure layer 110; forming a patterned current spreading layer 111 by photolithography and wet etching, the patterned current spreading layer 111 is located above the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110;

S5, atomic layer deposition (ALD) of dielectric DBR 112 on the current spreading layer 111;

S6, based on S5, depositing a ferroelectric material 106 on the exposed N-type semiconductor transmission layer 104 through a photolithography process and an etching technology, wherein the ferroelectric material 106 is AlScN, and stripping off the remaining photoresist;

S7, evaporating and photolithography to form a ferroelectric material electrode 115 on the ferroelectric material 106; and evaporating and photolithography to form a P-type ohmic electrode 113 and an N-type ohmic electrode 114 on the exposed current spreading layer 111 and the N-type semiconductor transport layer 104, respectively.

According to the above method, a semiconductor laser structure with a dual-gate control function is obtained.

Embodiment three:

The present invention provides a specific structure of a semiconductor laser structure with dual-gate control and a preparation method thereof, specifically:

A semiconductor laser structure with dual-gate control, wherein the dual gates refer to a polarization gate composed of Al _0.8 Ga _0.2 N and Al _0.6 Ga _0.4 N, and another gate composed of a ferroelectric material AlScN; the device comprises a circular substrate 101, a buffer layer 102, a nitride epitaxial DBR 103 and an N-type semiconductor transmission layer 104 in sequence along the epitaxial growth direction; wherein the N-type semiconductor transmission layer 104 has two layers, Al _0.8 Ga _0.2 N and Al _0.6 Ga _0.4 N, and a layer of ferroelectric material 106 is inserted in the Al _0.6 Ga _0.4 N, and the ferroelectric material 106 is AlScN;

The upper layer of the Al _0.6 Ga _0.4 N is composed of a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transmission layer 109 in sequence; the outer side of the upper surface of the P-type semiconductor transmission layer 109 is a ring-shaped high dielectric constant insulating layer, which serves as a current limiting hole structure layer 110. The material of the current limiting hole structure layer 110 is SiO ₂ , the thickness is 20 nm, and the width of the ring is 2.5 μm;

The current spreading layer 111 covers the P-type semiconductor transmission layer 109 and the insulating current limiting aperture structure layer 110; the dielectric DBR 112 is located on the current spreading layer 111, and its projected area is 0.6 of the area of the current spreading layer 111; the annular P-type ohmic electrode 113 is located on the outside of the current spreading layer 111, and has a width of 0.5 μm; the annular N-type ohmic electrode 114 is located on the outside of the exposed portion of the N-type semiconductor transmission layer 104, and has a width of 0.5 μm; the annular ferroelectric material electrode 115 is located on the ferroelectric material 106, and has a width of 0.5 μm.

The preparation method of the semiconductor laser structure with dual-gate control is as follows:

S1, in an MOCVD reactor, baking the substrate 101 at a high temperature of 1300° C., removing foreign matter on the surface of the substrate 101, and then growing a buffer layer 102, a nitride epitaxial DBR 103, an N-type semiconductor transport layer 104, a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transport layer 109 respectively; wherein the buffer layer 102 is made of GaN, the nitride epitaxial DBR 103 is made of AlN/GaN, the N-type semiconductor transport layer 104 is made of GaN, the multi-quantum well layer 107 is made of ten pairs of In _0.21 Ga _0.79 N/GaN; the P-type current blocking layer 108 is made of Al _0.1 Ga _0.9 N; and the P-type semiconductor transport layer 109 is made of GaN;

S2, based on the P-type semiconductor transmission layer 109 obtained in S1, a step is made by photolithography and etching process to expose the N-type semiconductor transmission layer 104;

S3, depositing and growing a current limiting hole structure layer 110 on the P-type semiconductor transmission layer 109 obtained in S1, the insulating material used in the current limiting hole structure layer 110 is SiO ₂ with a thickness of 20 nm; then etching a ring pattern on the insulating material using photolithography technology, the pattern covers along the edge of the P-type semiconductor transmission layer 109, and has a width of 2.5 μm;

S4, based on the current limiting hole structure layer 110 obtained in S3, a current spreading layer 111 is evaporated, the material of the current spreading layer 111 is ITO, and the thickness is 40nm; and a patterned current spreading layer 111 is manufactured by photolithography and wet etching, and is located above the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110;

S5, based on the current spreading layer 111 obtained in S3, an atomic layer deposition (ALD) dielectric DBR 112 is formed, and the thickness of the dielectric DBR 112 is 1.27 μm; the dielectric DBR 112 uses 10 pairs of Ta ₂ O ₅ /SiO ₂ ;

S6, depositing a layer of ferroelectric material 106 on the N-type semiconductor transmission layer 104 through photolithography and etching processes, wherein the ferroelectric material 106 is made of AlScN with a thickness of 5-10 nm, and stripping off the remaining photoresist;

S7 , evaporating and photolithography to form a P-type ohmic electrode 113 , an N-type ohmic electrode 114 and a ferroelectric material electrode 115 .

The implementation of the present invention is based on the basic design idea of VCSEL laser, combining the polarization properties of III-V nitride materials with the piezoelectric properties of ferroelectric materials, and synergistically regulating the accumulation and depletion of electrons, thereby achieving good results; specifically, a specific component gradient is used to generate negative interface charges at the interface of the N-type semiconductor transport layer, thereby repelling and depleting negatively charged electrons; at the same time, the charge of the interface charge between the ferroelectric material and the N-type semiconductor transport layer is selectively adjusted by regulating the external electric field, thereby achieving the accumulation and depletion of electrons, controlling the opening and closing of the conductive channel, and thus suppressing the leakage current phenomenon of the device; the present application deposits a layer of ferroelectric material on the surface of the N-semiconductor transport layer of the VCSEL, and adopts an N-region composition with a specific component gradient, fully utilizing the piezoelectric characteristics and polarization effect of the ferroelectric material to act as a double-gate effect, and controlling the opening and closing of the conductive channel; the current control capability of the VCSEL can be enhanced, the reverse leakage of the device can be effectively prevented, the leakage level of the active area can be suppressed, and the reliability and stability of the device can be improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings; however, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, a variety of simple modifications can be made to the technical solution of the present application, and these simple modifications all fall within the protection scope of the present application.

It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the various possible combinations of this application will not be described separately.

In addition, the various implementation modes of the present application may be arbitrarily combined, and as long as they do not violate the concept of the present application, they should also be regarded as the contents disclosed in the present application.

Claims (10)

1. A semiconductor laser structure with dual-gate control, the semiconductor laser comprising a substrate (101), a buffer layer (102), a nitride epitaxial DBR (103), and an N-type semiconductor transmission layer (104) in sequence along the epitaxial growth direction, characterized in that a multi-quantum well layer (107) is arranged on the upper part of the N-type semiconductor transmission layer (104), a ferroelectric material (106) and an N-type ohmic electrode (114) are arranged on the upper part of the exposed N-type semiconductor transmission layer (104), a ferroelectric material electrode (115) is arranged on the upper part of the ferroelectric material (106), and the A P-type current blocking layer (108) and a P-type semiconductor transmission layer (109) are sequentially arranged on the upper part of the multi-quantum well layer (107); a current limiting hole structure layer (110) is arranged on the upper surface of the P-type semiconductor transmission layer (109); a current expansion layer (111) covers the P-type semiconductor transmission layer (109) and the current limiting hole structure layer (110); a dielectric DBR (112) and a P-type ohmic electrode (113) are arranged on the upper side of the current expansion layer (111); and a projection area of the dielectric DBR (112) is smaller than an area of the current expansion layer (111). 2. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that the projection area of the dielectric DBR (112) is 0.5-0.9 of the area of the current spreading layer (111). 3. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that the material of the nitride epitaxial DBR (103) is composed of _{Alx2Gay2In1 -x2-y2N and Alx3Gay3In1} - _{x3 -y3N} alternately, the thickness of _Alx2Gay2In1 - _x2 - _y2N and _Alx3Gay3In1 - _{x3 -yN are} respectively one-fourth of the wavelength of the required light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; wherein, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1. 4. The semiconductor laser structure with dual-gate control according to claim 1, characterized in that the N-type semiconductor transmission layer (104) is composed of Al _x4 Ga _y4 In _1-x4-y4 N and _{Alx5Gay5In1 -x5-y5N ,} where 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1, 0≤x5 ≤1, _0≤y5≤1 , 0≤1-x5-y5≤1 and x4＞x5; a multi-quantum well layer (107), a ferroelectric material (106) and an N-type ohmic electrode (114) are arranged above the _{Alx5Gay5In1 -x5-y5N} layer. 5. A semiconductor laser structure with dual-gate control according to claim 4, characterized in that the thickness of _{the Alx4Gay4In1 -x4-y4N} is 50nm-5μm, and the thickness of the _{Alx5Gay5In1 -x5- y5N} is 50nm-2μm. 6. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that the multi-quantum well layer (107) is composed of quantum wells _{Alx6Iny6Ga1 -x6-y6N and} quantum barriers _{Alx7Iny7Ga1 -x7-y7N ,} wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of quantum wells is greater than or equal to 1. 7. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that the ferroelectric material (106) is AlScN. 8. A method for preparing a semiconductor laser structure with dual-gate control according to any one of claims 1 to 7, characterized in that it comprises the following steps: S1, in an MOCVD reactor, growing a buffer layer (102), a nitride epitaxial DBR (103), an N-type semiconductor transmission layer (104), a multi-quantum well layer (107), a P-type current blocking layer (108), and a P-type semiconductor transmission layer (109) on the surface of a substrate (101); S2, forming a step on the P-type semiconductor transmission layer (109) by photolithography and etching processes to expose the N-type semiconductor transmission layer (104); S3, depositing and growing a current limiting aperture structure layer (110) on the P-type semiconductor transport layer (109); S4, evaporating a current spreading layer (111) on the current limiting aperture structure layer (110); S5, atomically depositing a dielectric DBR (112) on the current spreading layer (111); S6, based on S5, depositing a ferroelectric material (106) on the exposed N-type semiconductor transport layer (104) through a photolithography process and an etching technique; S7, evaporating and photolithography to form a ferroelectric material electrode (115) on the ferroelectric material (106); and evaporating and photolithography to form a P-type ohmic electrode (113) and an N-type ohmic electrode (114) on the exposed current spreading layer (111) and the N-type semiconductor transmission layer (104), respectively. 9. The method for preparing a semiconductor laser structure with dual-gate control according to claim 8, characterized in that in said S2, 60%-80% of the N-type semiconductor transmission layer (104) is exposed. 10. The method for preparing a semiconductor laser structure with dual-gate control according to claim 8, characterized in that the N-type semiconductor transmission layer (104) is composed of _{Alx4Gay4In1 -x4- y4N} and _{Alx5Gay5In1 -x5-y5N} along the growth direction, wherein 0≤x4≤1, 0≤y4≤10, 0≤1-x4- _y4≤1 , 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and _x4 ＞x5; and a multi-quantum well layer (107), a ferroelectric material (106), and an N-type ohmic electrode (114) are arranged above the _{Alx5Gay5In1 -x5-y5N} layer.