CN118800656B - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- CN118800656B CN118800656B CN202411259730.3A CN202411259730A CN118800656B CN 118800656 B CN118800656 B CN 118800656B CN 202411259730 A CN202411259730 A CN 202411259730A CN 118800656 B CN118800656 B CN 118800656B
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Abstract
The embodiment of the application provides a semiconductor device manufacturing method and a semiconductor device; when the embodiment of the application is used for manufacturing a semiconductor device, after the dielectric layer is manufactured, photoetching windows with various widths can be formed on the dielectric layer through photoetching, then groove structures with different depths are formed at the photoetching windows through dry etching, then the dielectric layer is subjected to wet etching, so that adjacent groove structures are communicated, a plurality of step structures with different depths are further formed, and then structures such as metal field plates and the like can be manufactured on the step structures to obtain the semiconductor device; the scheme can greatly reduce the process cost and time and improve the manufacturing efficiency and the reliability of devices.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a semiconductor device manufacturing method and a semiconductor device.
Background
Gallium nitride high electron mobility transistor (GaN HEMT, gaN High Electron Mobility Transistors), abbreviated as gallium nitride power device, is representative of Wide Bandgap power semiconductor device, and has great potential in high frequency power application. In the design of gallium nitride power devices, the withstand voltage capability of the device is a very important performance parameter. The main withstand voltage structure of the gallium nitride power device is a depletion region between a Gate (G) and a Drain (D, drain) when the device is turned off. Under the same depletion region size, the electric field distribution determines the magnitude of the withstand voltage, and because the electric field concentration effect exists at the corner of the gate near the drain side, there is an electric field peak, when the electric field peak reaches a certain critical value, electric field breakdown occurs, and thus the reliability of the device is affected, even irreversible damage occurs.
In the prior art, in order to improve the voltage endurance capability of the device, a field plate structure is generally adopted. The field plate has the main function of adjusting the electric field distribution of the drift region, weakening the electric field peak originally existing near the grid electrode and improving the withstand voltage of the device. Although the introduction of the field plate reduces the original electric field peak, a new electric field peak is generated at the end of the field plate, so that in order to realize the ideal electric field distribution, a multi-stage field plate structure is generally adopted to modulate the electric field distribution. By using the method, each layer of field plate from the gate electrode to the drain electrode can further modulate the electric field peak generated by the previous field plate, and by adjusting the length and the height of each layer of field plate, an optimized electric field distribution can be obtained, thereby realizing higher pressure resistance and reliability.
However, in the research and practice of the prior art, the inventor of the present application found that in order to implement the multi-layer field plate structure during the manufacturing process of the device, it is often necessary to etch the multi-layer dielectric and metal and perform multiple lithography, for example, in some structures commonly used in the industry, each time one layer of field plate is added, at least one lithography and etching step needs to be added, so as to increase the process cost and time cost significantly as the number of field plates increases, that is, the prior art has a higher process cost and a lower manufacturing efficiency.
Disclosure of Invention
The embodiment of the application provides a semiconductor device manufacturing method and a semiconductor device, which can reduce the process cost and time for manufacturing a multi-layer field plate structure and improve the manufacturing efficiency.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps:
Setting a substrate;
manufacturing an epitaxial layer on the substrate, and manufacturing a gate dielectric layer and a first dielectric layer on the epitaxial layer;
forming a source metal and a drain metal on the epitaxial layer and the first dielectric layer;
disposing a second dielectric layer over the first dielectric layer, source metal, and drain metal;
providing a photoetching mask on the second dielectric layer, wherein the photoetching mask is provided with photoetching windows with various widths;
dry etching the second dielectric layer and the first dielectric layer to form corresponding groove structures at photoetching windows of the second dielectric layer and the first dielectric layer, wherein the depth and the width of the groove structures are positively correlated with the width of the corresponding photoetching windows;
Wet etching is carried out on the first dielectric layer and the second dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed;
and manufacturing a metal layer on the step structure to form a grid metal and a metal field plate structure, so as to obtain the semiconductor device.
Correspondingly, the embodiment of the application also provides another manufacturing method of the semiconductor device, which comprises the following steps:
Setting a substrate;
Manufacturing an epitaxial layer on the substrate, and manufacturing a P-GaN grid electrode and a first dielectric layer on the epitaxial layer;
Manufacturing source metal and drain metal on the epitaxial layer and the first dielectric layer, and manufacturing gate metal on the P-GaN gate;
providing a second dielectric layer over the first dielectric layer, the source metal, the drain metal, and the gate metal;
providing a photoetching mask on the second dielectric layer, wherein the photoetching mask is provided with photoetching windows with various widths;
Dry etching is carried out on the second dielectric layer, so that a corresponding groove structure is formed at the photoetching window of the second dielectric layer, and the depth and the width of the groove structure are positively correlated with the width of the corresponding photoetching window;
Wet etching is carried out on the second dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed;
and manufacturing a metal field plate structure on the step structure to obtain the semiconductor device.
In addition, the embodiment of the application also provides a semiconductor device which is manufactured by adopting any one of the manufacturing methods of the semiconductor device provided by the embodiment of the application.
When the embodiment of the application is used for manufacturing a semiconductor device, after a dielectric layer is manufactured, photoetching windows with various widths can be formed on the dielectric layer through photoetching, then, groove structures are formed at the photoetching windows through dry etching, the depth and the width of the groove structures are positively related to the width of the corresponding photoetching windows, then, the dielectric layer is subjected to wet etching, so that adjacent groove structures are communicated, a plurality of step structures with different depths are further formed, and then, structures such as metal field plates and the like can be manufactured on the step structures to obtain the semiconductor device; because the manufacturing method can realize any multi-layer field plate structure by using two photoetching processes, compared with the prior art that each layer of field plate is added, the manufacturing method can greatly reduce the process cost and time and improve the manufacturing efficiency in terms of the process of adding at least one photoetching and etching step; in addition, as the deposition of the medium and the metal and the etching times are reduced, the possibility of etching damage can be reduced, the medium quality under the field plate is higher, and the reliability of the device is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2 is a diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present application;
fig. 3 is a diagram illustrating another example of a method for fabricating a semiconductor device according to an embodiment of the present application;
fig. 4 is a diagram illustrating another exemplary method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 5 is a diagram illustrating another exemplary method for manufacturing a semiconductor device according to an embodiment of the present application;
Fig. 6 is another flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application;
Fig. 7 is a diagram showing another example of a method for manufacturing a semiconductor device according to an embodiment of the present application;
Fig. 8 is a diagram illustrating another exemplary method for manufacturing a semiconductor device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
The embodiment of the application provides a semiconductor device manufacturing method and a semiconductor device. The following will describe in detail.
A method for manufacturing a semiconductor device includes: a setting Substrate (Substrate); fabricating an epitaxial layer (Epitaxial Layer) on the substrate; forming a gate dielectric layer and a first dielectric layer (DIELECTRIC LAYER) on the epitaxial layer; fabricating a source metal (Source Ohmic Metal) and a drain metal (Drain Ohmic Metal) on the epitaxial layer and on the first dielectric layer; disposing a second dielectric layer over the epitaxial layer, source metal, and drain metal; providing a lithography mask on the second dielectric layer, the lithography mask having lithography windows of various widths; dry etching the second dielectric layer and the first dielectric layer so that corresponding groove structures are formed at the photoetching windows of the second dielectric layer and the first dielectric layer, wherein the depth and the width of the groove structures are positively correlated with the width of the corresponding photoetching windows; wet etching is carried out on the first dielectric layer and the second dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed; a metal layer is formed on the step structure to form a gate metal (GATE METAL) and a metal field plate structure (FIELD PLATE) to obtain a semiconductor device.
As shown in fig. 1, the flow of the method for manufacturing the semiconductor device may specifically be as follows:
S101, arranging a substrate.
Specifically, depending on the desired semiconductor material and device properties, a suitable single crystal substrate is selected, which may include, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), gallium oxide (GaO), or the like, and then the substrate is cleaned to remove surface contaminants, oxides, and other impurities.
The cleaning method may be determined according to the requirements of practical application, and may include chemical cleaning, ultrasonic cleaning, vacuum heat treatment, and/or the like, for example.
S102, manufacturing an epitaxial layer on the substrate, and manufacturing a gate dielectric layer and a first dielectric layer on the epitaxial layer
The epitaxial layer is also called epitaxial growth, and the epitaxial growth method may include solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy, wherein the vapor phase epitaxy may further include chemical vapor phase epitaxy (CVE, chemical Vapor Epitaxy), molecular beam epitaxy (MBE, molecular Beam Epitaxy), and the like. Chemical vapor phase epitaxy refers to a process of depositing a thin film by chemically reacting a mixed gas on the surface of a wafer; and the molecular beam epitaxy is to directly spray the molecular beam or the atomic beam of the required element on the surface of the substrate under the ultra-high vacuum condition, and form a monocrystalline layer through the processes of surface adsorption, reaction, migration and the like. For example, the following can be mentioned:
(1) Chemical vapor epitaxy;
Introducing a precursor gas, such as silane, germane, etc., into the reaction chamber; at high temperature, the precursor gas chemically reacts on the surface of the substrate to generate a required monocrystalline layer; by controlling the flow, temperature, pressure, reaction time and other parameters of the reaction gas, the epitaxial layer with specific thickness, doping concentration and crystal quality can be grown.
(2) Molecular beam epitaxy;
The substrate is placed in a reaction chamber in ultrahigh vacuum, and molecular beams or atomic beams of required elements are sprayed to the surface of the substrate through a spraying system, so that adsorption, reaction, migration and other processes occur on the surface of the substrate, and a required epitaxial layer can be formed.
Of course, after the epitaxial layer is formed, some subsequent processes, such as annealing, cleaning, and detecting, may be performed, which will not be described herein.
A gate dielectric layer and a first dielectric layer are then fabricated directly on the epitaxial layer.
And S103, manufacturing a source metal and a drain metal on the epitaxial layer and the first dielectric layer.
For example, a metal electrode may be specifically prepared on a preset first area on the epitaxial layer and the first dielectric layer to form ohmic contact, where the metal electrode on the first area is the source metal; similarly, a metal electrode may be formed on a predetermined second region on the epitaxial layer to form an ohmic contact, where the metal electrode on the second region is drain metal, for example, see fig. 2 to 5.
Ohmic contact means that the contact resistance between the metal and the semiconductor is very small and almost negligible, so that it is ensured that the current does not generate a significant voltage drop at the contact surface. This process of forming a metal electrode on a specific region (e.g., source, drain, or gate) to form an ohmic contact is called an ohmic metal process.
S104, disposing a second dielectric layer on the first dielectric layer, the source metal and the drain metal.
For example, after the ohmic metal process is completed, a second dielectric layer may be formed by deposition on the dielectric, in particular on the first dielectric layer, the source metal and the drain metal.
The deposition method may be various, and may include thermal oxidation, chemical vapor deposition (CVD, chemical Vapor Deposition), atomic layer deposition (ALD, atomic Layer Deposition), and the like, for example. The specific deposition method can be determined according to the requirements of practical application.
It should be noted that, optionally, the substrate (i.e., the substrate on which the epitaxial layer, the source metal, and the drain metal are formed) may also be cleaned prior to deposition to remove surface contaminants, oxides, and other impurities. Optionally, surface treatments may be performed, such as special treatments of the substrate surface, such as oxidation, nitridation or deposition of a thin finish layer, as needed to improve adhesion and interface quality between the dielectric and the substrate.
In addition, after the deposition, some subsequent treatments, such as annealing treatment, cleaning, detection, etc., may be performed, which will not be described herein.
S105, a photoetching mask is arranged on the second dielectric layer, and the photoetching mask is provided with photoetching windows with various widths.
It should be noted that, in order to provide a plurality of metal field plate structures with different depths subsequently, a plurality of step structures with different depths need to be formed on the dielectric layer.
There are various processes for providing the photolithography mask, for example, a uniform photoresist (i.e., a photoresist) may be coated on a dielectric layer of a substrate, and then the photoresist-coated substrate may be exposed using a laser lithography machine or an electron beam lithography machine. During exposure, a laser or electron beam is passed through the mask pattern to transfer the pattern to the photoresist. After exposure, the photoresist in the exposed area is subjected to chemical change, and the pattern on the photoresist can be displayed by treatment of the developing solution, so that the required photoetching mask is obtained.
The mask pattern may be determined according to the requirements of practical applications. For example, the mask pattern may be: and a plurality of photoetching windows with different widths are arranged between the source electrode metal and the drain electrode metal, wherein the width of the photoetching window in the middle is maximum, and the two sides of the photoetching window are sequentially narrow, so that corresponding photoetching masks can be obtained on the substrate subsequently.
For example, referring to fig. 2, which is one example of a photolithographic mask, the photolithographic window may be located between the source metal and the drain metal, as shown in fig. 2, wherein the width of the photolithographic window located in the middle is maximized, and the widths of the photolithographic windows on both sides sequentially become narrower as the distance from the photolithographic window located in the middle increases.
Alternatively, the width and arrangement of the photolithography windows may be set according to the requirements of practical applications, for example, referring to fig. 3 and 4, the photolithography window with the largest width may be set at a position closer to the source metal, and similarly, the width of other photolithography windows may be set to sequentially narrow as the distance from the photolithography window with the largest width increases. For example, in fig. 3, the width of the photolithography window W3 is the largest, and the widths of the photolithography windows on both sides of the photolithography window W3 are sequentially reduced, for example, the widths thereof are as follows: w3> W2> W1, W3> "W4 and W5" "" W6, W7 and W8"> W9; for another example, in fig. 4, the width of the photolithographic window closest to the source location is greatest, while the other photolithographic windows sequentially narrow as the distance from the "greatest width" photolithographic window increases, and so on.
Alternatively, the widths of the photolithography windows may be different from each other, and two or more adjacent photolithography windows may be set to the same or similar width, for example, see fig. 3, in which the widths of the photolithography windows W4 and W5 are the same, the widths of the photolithography windows W6, W7 and W8 are the same, and so on.
The adjacent plurality of photoetching windows are arranged to be the same or similar in width, so that adjacent groove structures obtained after subsequent etching have the same or similar depth, and the adjacent groove structures can be effectively equivalent to a layer of longer field plate. In this way, the dimensions of the recess structures are arranged and combined to obtain any desired combination of depth and length of the field plate, as will be described in further detail below.
And S106, carrying out dry etching on the second dielectric layer and the first dielectric layer, so that corresponding groove structures are formed at photoetching windows of the second dielectric layer and the first dielectric layer, wherein the depth and the width of the groove structures are positively related to the width of the corresponding photoetching windows due to the loading effect of the dry etching.
That is, the wider the position of the lithography window, the wider the etching width and the deeper the etching depth, and the narrower the position of the lithography window, the narrower the etching width and the shallower the etching depth. For example, referring specifically to fig. 2 to 5, as the width of the photolithography window decreases in sequence, the width and depth of the corresponding groove structure also decrease in sequence.
For example, taking fig. 3 as an example, since the width of the photolithography window W3 is the largest, the width of the corresponding groove structure G3 is the largest and the depth is the deepest, and in other photolithography windows on the right of W3, since the widths of the photolithography windows W4 and W5 are narrower than W3, the widths of the groove structures G4 and G5 corresponding to the photolithography windows W4 and W5 are also narrower than G3 and the depth is shallower than G3; similarly, since the width of the photolithography windows W6, W7 and W8 is narrower than that of W4 and W5, the widths of the groove structures G6, G7 and G8 corresponding to the photolithography windows W6, W7 and W8 are also narrower than those of G4 and G5, and the depths are shallower than those of G4 and G5; by analogy, since the width of the photolithography window W9 is the narrowest, the width of the groove structure G9 corresponding to the photolithography window W9 is the narrowest, and the depth is the shallowest. Similarly, in other lithography windows to the left of W3, the width of the groove structure G1 corresponding to W1 is smaller than the groove structure G2 corresponding to W2, and G2 is smaller than G3, and so on.
Wherein, since the widths of the lithography windows W4 and W5 are the same, the widths and depths of their corresponding groove structures G4 and G5 are also approximately the same; similarly, since the widths of the photolithography windows W6, W7 and W8 are the same, the widths and depths of the corresponding groove structures G6, G7 and G8 are substantially identical, and are not described in detail herein with reference to fig. 3.
The loading effect of dry etching herein refers to a phenomenon in which when the size or shape of the etched area is changed, the etching rate is changed, i.e., the etching rate depends on the amount of the material of the etched surface, and generally includes three types: macroscopic loading effects (Macroloading), microscopic loading effects (Microloading), and deep Aspect Ratio dependent loading effects (ARDE, aspect Ratio DEPENDENT ETCHING). Among them, the ARDE mainly occurs in high aspect ratio structure etching, such as deep holes or deep trenches. In these structures, it is difficult for the etching material to enter the deep portion while the reaction product is difficult to overflow, resulting in a reduction in the etching rate of the bottom portion. The loading effect affects the accuracy of the shape and size of the structure, so that the structure is generally suppressed as much as possible, but the application utilizes the characteristic to manufacture groove structures with different widths and depths, and further changes the phenomenon which is originally harmful into a factor which is beneficial to the process.
Alternatively, the dry etching method may be determined according to the actual application requirement, for example, plasma etching (i.e. chemical dry etching), sputter etching (i.e. physical dry etching), or reactive ion etching (i.e. chemical physical dry etching), which will not be described herein.
And S107, wet etching is carried out on the second dielectric layer and the first dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed. For example, the following may be specifically mentioned:
After the groove structure is obtained in step S106, the groove structure may be pretreated, for example, ultrasonic cleaning, plasma treatment or the like may be adopted to remove impurities and oxides on the surface, so as to obtain a pretreated material, then the pretreated material is soaked in a pre-prepared etching solution, and parameters such as etching time, temperature and the like are controlled to enable the etching solution to react with the surface of the pretreated material, such as dissolution, oxidation reduction and the like, so as to remove unnecessary parts. For example, specifically, due to isotropy of wet etching, after the etching solution enters the groove structures, the etching solution etches the medium between the adjacent groove structures, so that the adjacent groove structures are communicated, the depth of each groove structure is further deepened, the side wall of the groove structure is more gentle, and a plurality of step structures with different depths are formed, for example, see S1, S2, S3, S4, S5, S6, S7, S8 and S9 in fig. 3.
Wherein the depth of the step structure closest to the gate metal (i.e., the location where the gate metal is to be fabricated) is the deepest and the depth of the step structure further from the gate metal is shallower.
For example, as shown in fig. 3, taking the case of fabricating the gate metal at the step structure S3, the depth of the step structure S3 is the deepest, the depths of the step structures S4 and S5 are next to each other on the right side of S3, and the step structures S6, S7 and S8 are next to each other, and the step structure S9 is the shallowest because it is the farthest from S3; similarly, on the left side of S3, the step structure depths are S2 and S1 in order from deep to shallow.
Since the widths and depths of the groove structures G4 and G5 are substantially the same, the heights of the corresponding step structures S4 and S5 are also substantially the same, so that the two step structures can be effectively equivalent to a longer step structure (a metal field plate structure can be manufactured later). Similarly, since the widths and depths of the groove structures G4 and G5 are substantially the same, the heights of the corresponding step structures S6, S7 and S8 are also substantially the same, so that the three step structures can be effectively equivalent to a longer step structure (a metal field plate structure can be manufactured later). It can be seen that, as described above, by arranging and combining the grooves of different sizes in this way, a metal field plate structure of arbitrary depth and length can be obtained.
Alternatively, as shown in fig. 3, a dielectric layer with a certain thickness may be reserved between the lower part of the deepest step structure (i.e. at the deepest groove, such as S3 in fig. 3) and the epitaxial layer as a gate dielectric (which may be called a gate dielectric layer) so as to manufacture gate metal later. The material of the gate dielectric layer is denser than that of the dielectric layer above, so that the wet etching speed on the gate dielectric layer can be effectively slowed down.
The shape of the groove structure can be continuous and gentle through wet etching, so that a better filling effect and a better modulation effect on an electric field can be ensured when gate metal is manufactured subsequently.
Optionally, to improve the quality of the step structure formed, after wet etching is completed, it may be further subjected to a cleaning and drying process to remove residual chemical reagents and reaction products.
S108, manufacturing a metal layer on the step structure to form a grid metal and a metal field plate structure, and obtaining the semiconductor device.
For example, the gate metal may be deposited in particular on the deepest step structure (e.g., on the gate dielectric).
Similarly, field plate metals can be deposited on other step structures except the deepest step structure, so that the field plate metals deposited on step structures with different heights can be used as field plates with different layers (namely, the field plate metals deposited on step structures with the same adjacent height are used as metal field plate structures with the same layer, and the field plate metals deposited on step structures with different heights are used as metal field plate structures with different layers), and then, photoetching and metal etching are performed on the field plate metals, so that a multi-layer metal field plate structure can be obtained.
Alternatively, a metal field plate structure may be provided on both sides of the gate metal, for example, see fig. 2 and 3; or the metal field plate structure may be disposed between the gate metal and the drain metal, for example, see fig. 4 and 5.
The selection of the gate metal and the field plate metal may depend on the requirements and the process conditions of the actual device, for example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni), or alloys or compounds thereof may be used, and the present invention is not limited thereto.
Alternatively, the specific deposition method may also be determined according to the actual application requirement, for example, physical vapor deposition or chemical vapor deposition may be used, which will not be described herein.
Optionally, in order to improve the quality of the device, the deposited gate metal and metal field plate structure may be planarized, cleaned, dried, and the like.
Optionally, the resulting semiconductor device may also be tested and evaluated in order to ensure that it meets design requirements and has good performance characteristics.
Alternatively, the connection between the gate metal and the metal field plate structure may be determined according to the requirements of practical applications.
For example, if a gate field plate is required, if a gate metal and a metal field plate structure are connected during deposition, for example, see fig. 2 and 3, then there is no need to connect the gate metal and the metal field plate structure additionally, and if the gate metal and the metal field plate structure are not connected, then the metal field plate structure can be connected with the gate metal; that is, after a metal layer is formed on the step structure to form a gate metal and a metal field plate structure, the method for manufacturing the semiconductor device may further include:
And connecting the metal field plate structure with the gate metal through the subsequent through holes and interconnection metal.
For another example, if a source field plate is required, if a gate metal and a metal field plate structure are already connected during deposition, for example, see fig. 2 and 3, then the gate metal and the metal field plate structure may be disconnected during metal etching, then an interconnection metal connecting the metal field plate structure and the source metal is fabricated on a new dielectric layer formed by a subsequent process, for example, a new dielectric layer is continuously fabricated on the structure, then a via hole is locally fabricated on the new dielectric layer, then an interconnection metal is fabricated, and the metal field plate structure and the source metal are connected by using the via hole and the interconnection metal; if the gate metal and the metal field plate structure are not connected, only an interconnection metal for connecting the metal field plate structure and the source metal is required to be manufactured on the dielectric layer. That is, after the step of fabricating the metal layer on the step structure to form the gate metal and metal field plate structure, the fabrication method of the semiconductor device may further include:
And manufacturing a through hole and interconnection metal on the new dielectric layer formed in the subsequent process, and connecting the metal field plate structure and the source metal through the interconnection metal.
It should be noted that, the manner of forming the interconnection metal connecting the metal field plate structure and the source metal may be varied, and the specific form thereof may be determined according to the actual application requirement and the current process condition, which is not limited herein.
Optionally, the semiconductor device manufactured in this embodiment may be a MIS-HEMT, a P-GaN HEMT (P-type gate enhancement GaN HEMT) or a recessed gate HEMT (high electron mobility transistor, high Electron Mobility Transistors), and the materials of the semiconductor device include, but are not limited to, gaN, siC, gaAs or GaO, which are not described herein.
As can be seen from the above, when manufacturing a semiconductor device, after manufacturing a dielectric layer, a photolithography window with various widths can be formed on the dielectric layer by photolithography, then, a groove structure is formed at the photolithography window by dry etching, the depth and width of the groove structure are positively correlated to the width of the corresponding photolithography window, then, the dielectric layer is subjected to wet etching, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed, and then, a gate metal and a metal field plate structure can be manufactured on the step structures to obtain the semiconductor device; because the manufacturing method can realize the grid electrode and any multi-layer field plate structure by using two photoetching processes, compared with the prior art that each layer of field plate is added, the manufacturing method can greatly reduce the process cost and time and improve the manufacturing efficiency in terms of the process of adding at least one photoetching and etching step; in addition, as the deposition of the medium and the metal and the etching times are reduced, the possibility of etching damage can be reduced, the medium quality under the field plate is higher, and the reliability of the device is greatly improved.
Alternatively, in some embodiments of the present application, the gate metal and the metal field plate structure may be fabricated separately, in addition to being fabricated together, that is, the embodiments of the present application further provide a semiconductor device fabrication method, including: setting a substrate; manufacturing an epitaxial layer on the substrate; manufacturing a P-GaN grid electrode and a first dielectric layer on the epitaxial layer; manufacturing a source metal and a drain metal on the epitaxial layer and the first dielectric layer, and manufacturing a gate metal on the P-GaN gate; disposing a second dielectric layer over the first dielectric layer, the source metal, the drain metal, and the gate metal; providing a lithography mask on the second dielectric layer, the lithography mask having lithography windows of various widths; dry etching is carried out on the second dielectric layer, so that a corresponding groove structure is formed at the photoetching window of the second dielectric layer, and the depth and the width of the groove structure are positively correlated with the width of the corresponding photoetching window; wet etching is carried out on the second dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed; and manufacturing a metal field plate structure on the step structure to obtain the semiconductor device.
For example, as shown in fig. 6, the specific flow of the method for manufacturing the semiconductor device may be as follows:
S201, a substrate is arranged, specifically, refer to S101, and details are not described herein.
S202, an epitaxial layer is fabricated on the substrate, and a P-GaN gate and a first dielectric layer are fabricated on the epitaxial layer, specifically, S102 is referred to, and details are not repeated here.
S203, manufacturing a source metal and a drain metal on the epitaxial layer and the first dielectric layer, and manufacturing a gate metal on the P-GaN gate.
For example, a metal electrode may be specifically prepared on a preset first area on the epitaxial layer and the first dielectric layer to form ohmic contact, where the metal electrode on the first area is the source metal; similarly, a metal electrode can be prepared on a preset second area on the epitaxial layer to form ohmic contact, wherein the metal electrode on the second area is drain metal; and preparing a metal electrode on the P-GaN gate to form ohmic contact, wherein the metal electrode on the P-GaN gate is gate metal, for example, see fig. 7 and 8.
S204, a second dielectric layer is provided on the first dielectric layer, the source metal, the drain metal, and the gate metal.
For example, a dielectric layer may be formed by dielectric deposition on the first dielectric layer, the source metal, the drain metal, and the gate metal.
The deposition method may be various, and may include thermal oxidation, chemical vapor deposition, atomic layer deposition, and the like.
Optionally, the substrate (i.e., the substrate on which the epitaxial layer, source metal, and drain metal are formed) may also be cleaned prior to deposition to remove surface contaminants, oxides, and other impurities. Optionally, surface treatments may be performed, such as special treatments of the substrate surface, such as oxidation, nitridation or deposition of a thin finish layer, as needed to improve adhesion and interface quality between the dielectric and the substrate.
In addition, after the deposition, some subsequent treatments, such as annealing treatment, cleaning, detection, etc., may be performed, which will not be described herein.
S205, a photo-etching mask is disposed on the second dielectric layer, the photo-etching mask has photo-etching windows with various widths, and the details of the step S105 are not described herein.
S206, performing dry etching on the second dielectric layer to form a corresponding groove structure at the photoetching window of the dielectric layer, wherein the depth and the width of the groove structure are positively correlated with the width of the corresponding photoetching window.
That is, the wider the position of the lithography window, the wider the etching width and the deeper the etching depth, and the narrower the position of the lithography window, the narrower the etching width and the shallower the etching depth. For example, referring specifically to fig. 7 and 8, as the width of the lithographic window decreases in sequence, the width and depth of the corresponding recess structure also decreases in sequence.
The step S206 is similar to the step S106, and the above embodiments can be referred to, and details are not repeated here.
S207, wet etching is carried out on the second dielectric layer, so that adjacent groove structures are communicated, and a plurality of step structures with different depths are formed.
The specific wet etching method may refer to step S107, and will not be described herein.
S208, manufacturing a metal field plate structure on the step structure to obtain the semiconductor device.
For example, field plate metals may be deposited on each step structure, so that the field plate metals deposited on the step structures with different heights may be used as field plates with different layers (i.e., the field plate metals deposited on the step structures with the same adjacent height are used as metal field plate structures with the same layer, and the field plate metals deposited on the step structures with different heights are used as metal field plate structures with different layers), and then, photolithography and metal etching are performed on the field plate metals, so as to obtain a multi-layer metal field plate structure, for example, see fig. 7 and 8.
The field plate metal may be selected according to the requirements and process conditions of the actual device, for example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni), or alloys or compounds thereof may be used, and the present invention is not limited thereto.
Alternatively, the specific deposition method may also be determined according to the actual application requirement, for example, physical vapor deposition or chemical vapor deposition may be used, which will not be described herein.
Optionally, in order to improve the quality of the device, planarization, clarity, drying and other treatments can be performed on the deposited metal field plate structure.
Alternatively, similar to the previous embodiments, in this embodiment, the connection between the gate metal and the metal field plate structure may be determined according to the requirements of practical applications.
For example, if a gate field plate is desired, the metal field plate structure may be connected to the gate metal; that is, after a metal layer is fabricated on the step structure to form a metal field plate structure, the fabrication method of the semiconductor device may further include:
The metal field plate structure is connected with the grid metal.
The connection mode can be various, for example, an interconnection metal for connecting the metal field plate structure and the gate metal can be manufactured on the dielectric layer; for another example, a photolithography window may also be disposed above the gate metal when step S205 (disposing a photolithography mask) is performed, for example, as shown in fig. 8, so that a corresponding recess structure may be formed at the photolithography window later on, so as to connect the gate metal and the metal field plate structure. Specifically, when metal is deposited on each step structure, the gate metal may be directly connected to the metal field plate structure, or the gate metal may be disconnected from the metal field plate structure, for example, referring to fig. 8, and then the metal field plate structure and the gate metal may be connected by making an interconnection metal when necessary, which is not described herein.
For another example, if a source field plate is desired, an interconnect metal connecting the metal field plate structure and the source metal may be fabricated on the dielectric layer. That is, after the step of fabricating the metal layer on the step structure to form the metal field plate structure, the fabrication method of the semiconductor device may further include:
And manufacturing a through hole and interconnection metal on the new dielectric layer formed in the subsequent process, and connecting the metal field plate structure and the source metal through the through hole and the interconnection metal.
The manner of forming the interconnection metal connecting the metal field plate structure and the source metal may be varied, and the specific form of the interconnection metal may be determined according to the actual application requirement and the current process condition, which is not limited herein.
As can be seen from the above, in the present embodiment, when manufacturing a semiconductor device, after manufacturing a dielectric layer, a gate electrode, a source electrode and a drain electrode, photolithography windows with various widths can be formed on the dielectric layer by photolithography, then, a groove structure is formed at the photolithography window by dry etching, and the depth and width of the groove structure are positively correlated with those of the corresponding photolithography window, then, by wet etching the dielectric layer, adjacent groove structures are communicated, and then, a plurality of step structures with different depths are formed, and thereafter, structures such as a metal field plate can be manufactured on the step structures to obtain the semiconductor device; because the manufacturing method can realize any multi-layer field plate structure by using two photoetching processes, compared with the prior art that each layer of field plate is added, the manufacturing method can greatly reduce the process cost and time and improve the manufacturing efficiency in terms of the process of adding at least one photoetching and etching step; in addition, as the deposition of the medium and the metal and the etching times are reduced, the possibility of etching damage can be reduced, the medium quality under the field plate is higher, and the reliability of the device is greatly improved.
Correspondingly, the embodiment of the application also provides a semiconductor device which can be manufactured by adopting any one of the manufacturing methods of the semiconductor device provided by the embodiment of the application.
For example, the semiconductor device may include a substrate, an epitaxial layer over the substrate, a source metal, a drain metal in the epitaxial layer, and a dielectric layer over the epitaxial layer; the dielectric layer is provided with a communicated groove structure, so that a plurality of step structures with different depths are formed; the step structure has a metal layer thereon such that the step structure forms a gate metal and metal field plate structure.
For another example, the semiconductor device may also include a substrate, an epitaxial layer over the substrate, a source metal, a drain metal, a gate metal in the epitaxial layer, and a dielectric layer over the epitaxial layer; the dielectric layer is provided with a communicated groove structure, so that a plurality of step structures with different depths are formed; the step structure has a metal layer thereon such that the step structure forms a metal field plate structure.
The recess structure may be formed by providing a photolithography mask having photolithography windows of various widths on the dielectric layer, and performing photolithography and etching based on the photolithography mask, that is, the recess structure may be formed by performing photolithography and etching at the photolithography windows.
The structure, connection manner, fabrication, etc. of the above parts can be specifically referred to the foregoing method embodiments, and are not described herein.
The semiconductor device provided in this embodiment may be manufactured by any one of the semiconductor device manufacturing methods provided in the embodiments of the present application, so that the semiconductor device may also achieve the beneficial effects that any one of the semiconductor device manufacturing methods provided in the embodiments of the present application can achieve, and the beneficial effects are specifically referred to the previous embodiments and are not described herein.
The foregoing has described in detail a method for fabricating a semiconductor device and a semiconductor device according to embodiments of the present application, and specific examples have been applied to illustrate the principles and embodiments of the present application, and the above description of the embodiments is only for aiding in understanding the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
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| US6221737B1 (en) * | 1999-09-30 | 2001-04-24 | Philips Electronics North America Corporation | Method of making semiconductor devices with graded top oxide and graded drift region |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
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| US6221737B1 (en) * | 1999-09-30 | 2001-04-24 | Philips Electronics North America Corporation | Method of making semiconductor devices with graded top oxide and graded drift region |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
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Denomination of invention: Semiconductor Device Manufacturing Methods and Semiconductor Devices Granted publication date: 20241119 Pledgee: Xiamen International Bank Co.,Ltd. Zhuhai branch Pledgor: Zhuhai GA Future Technology Co.,Ltd. Registration number: Y2024980060548 |