CN118796735A - High-speed memory bus timing adaptation method - Google Patents

Abstract

The present invention discloses a method for timing self-adaptation of a high-speed memory bus. In order to realize timing self-adaptation in a high-speed memory bus, the present invention sets a first channel and a second channel, as well as a corresponding idle mode and a normal working mode. When the timer reaches a preset duration, the channel in the idle mode begins to enter a margin test mode, and when the maximum margin of the timing of the signal to be sampled is not less than the timing deviation threshold in the margin test, the margin tuning mode is entered, and finally the delay of the signal to be sampled is fixed, and when the bus state is a self-refresh state, the modes of the two channels are switched. The present invention can realize timing self-adaptation without interrupting the read and write business.

Description

High-speed memory bus timing adaptation method

Technical Field

The invention relates to the field of memory bus, and in particular to a high-speed memory bus timing self-adaptation method.

Background Art

The fifth/sixth generation Double Data Rate 5/6 Synchronous Dynamic Random Access Memory (DDR5/6 SDRAM), the fifth/sixth generation Low Power Double Data Rate 5/6 Synchronous Dynamic Random Access Memory (LPDDR5/6 SDRAM) and the fifth/sixth generation Graphics Double Data Rate 5/6 Synchronous Dynamic Random Access Memory (GDDR5/6 SDRAM) are memory buses widely used for communication between computer processors (Central Processing Unit, CPU), graphics processors, field programmable gate arrays, digital signal processors, storage processors and memory particles.

The Registered Dual Inline Memory Module (RDIMM) driven by the Registered Clock involves Command and Address (CA) signals, Control (ConTRoL, CTRL) signals, Clock (CLocK, CLK) signals, Data (DQ) signals, and Data Strobe (DQS) signals. Among them, the CA signal and CLK signal are driven by the Register Clock Driver (RCD) and then sent to the memory particles again. The DQ signal is driven by the Data Buffer (DB) and then sent to the memory particles.

Timing training between CA signal and CLK signal, DQ signal and DQS signal will be performed between CPU and RCD, between RCD and Synchronous Dynamic Random Access Memory (SDRAM), between CPU and DB, and between DB and SDRAM. After the timing training is completed, the timing position will no longer change.

However, as the speed of the memory bus increases, the timing margin of the CA signal to the CLK signal and the DQ to the DQS signal becomes smaller and smaller. After the static timing training is completed, as the temperature and humidity change, the timing jitter becomes larger, and the offset of the CA signal relative to the CLK signal drifts.

When the SoC power is powered on, the timing of the CA signal and the CLK signal will be trained. However, during the operation of the read and write business, the external environment changes, but the timing is not trained in real time to compensate for the impact of the environmental changes.

Factors such as system on chip (SoC) compensation drift cause high risks in the timing of CA signals to CLK signals and the timing of DQ signals to DQS signals.

Therefore, with the development trend of high-speed memory, timing adaptation between CA signal and CLK signal, and between DQ signal and DQS signal, becomes more and more important.

Summary of the invention

In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

A high-speed memory bus timing self-adaptive method is used to adjust a signal to be sampled and a sampling clock signal. When the signal to be sampled is a CA signal or a CTRL signal, the sampling clock signal is a CLK signal. When the signal to be sampled is a DQ signal, the sampling clock signal is a DQS signal. When initially powered on, a first receiving sampler and a second receiving sampler are reset, a switching register is set to 0, an offset register is set to 0, and a channel selection register is set to 0. A first channel including the first receiving sampler is set to a normal working mode, and a second channel including the second receiving sampler is set to an idle mode. Timing training is performed on the first channel, and a counter is started when the training is completed. When the timer reaches a preset time length, the second channel enters a margin test mode, and in the margin test mode, the sampling clock signal phase is pulled left and the sampling clock signal phase is pulled right to measure the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled. The maximum timing margin of the signal to be sampled is calculated; if the maximum timing margin of the signal to be sampled is less than K, the second channel returns to the idle state until the next time the counter reaches the preset duration, and the second channel enters the margin test mode; otherwise, the offset register is set to 1, the second channel enters the margin tuning mode, and in the margin tuning mode, the delay of the signal to be sampled is adjusted with the set step size, and the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled are measured, and the maximum timing margin of the signal to be sampled is calculated, and when the maximum timing margin of the signal to be sampled is less than K, the delay of the signal to be sampled is fixed, and the switching register is set to 1, where K is the timing deviation threshold configured in the register; when the offset register is 1, the switching register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, the second channel is set to the normal working mode, and the first channel is set to the idle mode.

Furthermore, if the maximum timing margin of the signal to be sampled is less than K, the second channel returns to the idle state, which means: the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled are measured at least twice, and the maximum timing margins of the signal to be sampled calculated at least twice are both less than K, then the second channel returns to the idle state.

Furthermore, the delay of the signal to be sampled is adjusted with a set step length, wherein the set step length is a result of rounding K/2 and a result of rounding -K/2.

Furthermore, the first channel includes a first delay module, a second delay module, a first receiving sampler and a first verification module; the second channel includes a third delay module, a fourth delay module, a second receiving sampler and a second verification module; wherein, the signal to be sampled is used as the input signal of the first receiving sampler after passing through the first delay module, and the sampling clock signal is used as the input signal of the first receiving sampler after passing through the second delay module; the signal to be sampled is used as the input signal of the second receiving sampler after passing through the third delay module, and the sampling clock signal is used as the input signal of the second receiving sampler after passing through the fourth delay module; the first verification module receives the output signal of the first receiving sampler and uses it as the input signal of the multiplexer; the second verification module receives the output signal of the second receiving sampler and uses it as the input signal of the multiplexer.

Further, after the first channel enters the idle mode, when the timer reaches a preset duration, the first channel enters the margin test mode.

Furthermore, after the first channel enters the margin test mode, if the maximum margin of the signal timing to be sampled is not less than K, the first channel enters the margin tuning mode; and, when the offset register is 1, the switch register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, the first channel is set to the normal working mode, and the second channel is set to the idle mode.

Further, adjusting the delay of the signal to be sampled with a set step length refers to: adjusting the delay time length of the third delay module with a set step length.

The technical solution of the present invention has one or more of the following beneficial technical effects:

(1) Without interrupting the memory read and write business and without relying on the SoC test mode, fast and real-time timing adaptation between CA signals, CTRL signals to CLK signals, and DQ signals to DQS signals is achieved.

(2) Improve the dynamic timing margin between CA signal, CTRL signal and CLK signal, and DQ signal and DQS signal. The margin can be read online.

(3) Dynamic margin does not depend on the host device, and the solution is independently controllable.

(4) Low power consumption and can be updated in real time.

In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of timing adjustment in RDIMM of the prior art;

FIG. 2 is a schematic diagram of timing adjustment in the RDIMM of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

FIG1 is a schematic diagram of timing adjustment in the prior art RDIMM. The scheme is for two different situations. In situation 1, delay module 1 receives a CA signal or a CTRL signal, and delay module 2 receives a CLK signal, and after sampling by a receiving sampler and verification by a verification module, a CA signal or a CTRL signal is output. In situation 2, delay module 1 receives a DQ signal, and delay module 2 receives a DQS signal, and after sampling by a receiving sampler and verification by a verification module, a DQ signal is output.

Fig. 2 is a schematic diagram of timing adjustment in RDIMM of the present invention. In the present invention, different signal types can be targeted, for example, in case 1, the CA signal or the CTRL signal is sampled by the CLK signal; in case 2, the DQ signal is sampled by the DQS signal.

The CA signal or the CTRL signal and the DQ signal are signals to be sampled, and the CLK signal and the DQS signal are sampling clock signals.

The invention comprises a first channel and a second channel. The first channel comprises a first delay module, a second delay module, a first receiving sampler and a first verification module. The second channel comprises a third delay module, a fourth delay module, a second receiving sampler and a second verification module.

When the path selection signal is configured to different values, such as 0 or 1, the multiplexer selects the output signal of the first channel or the output signal of the second channel as the final output signal.

The CA signal, CTRL signal or DQ signal is used as the input signal of the first receiving sampler after passing through the first delay module, and the CLK signal or DQS signal is used as the input signal of the first receiving sampler after passing through the second delay module.

The CA signal, CTRL signal or DQ signal is used as the input signal of the second receiving sampler after passing through the third delay module, and the CLK signal or DQS signal is used as the input signal of the second receiving sampler after passing through the fourth delay module.

The first verification module receives the output signal of the first receiving sampler and uses it as one of the input signals of the multiplexer. The second verification module receives the output signal of the second receiving sampler and uses it as one of the input signals of the multiplexer.

The specific sampling process is performed by the first receiving sampler or the second receiving sampler. The first checking module and the second checking module determine whether there is an error according to the sampling result.

Taking the CA signal and the CLK signal as an example, the high-speed memory bus timing self-adaptation method of the present invention includes the following steps:

At initial power-up, the first receive sampler and the second receive sampler are reset, the switch register is set to 0, the offset register is set to 0, and the channel selection register is set to 0.

In the present invention, releasing the reset means setting the reset signal to an invalid state, thereby releasing the reset state.

The first channel including the first receiving sampler is set to a normal operating mode, and the second channel including the second receiving sampler is set to an idle mode.

Keep the second channel in idle mode; perform timing training for the first channel and start the counter when the training is completed.

At this time, the first channel is the main data channel and performs data transmission function; the second channel is reset and is in idle mode, which often consumes less energy.

When the counter reaches the preset duration, the second channel enters the margin test mode. In the margin test mode, first gradually pull the CLK signal phase to the left until the second verification module indicates an error from 0 to a certain moment, and the maximum margin of the left timing of the CA signal is measured to be A0. Then, gradually pull the CLK signal phase to the right until the second verification module indicates an error from 0 to a certain moment, and the maximum margin of the right timing of the CA signal is measured to be B0. Calculate A0-B0 and save. Repeat the above steps to obtain the A1-B1 result, where A1 is the maximum margin of the left timing of the CA signal measured again, and B1 is the maximum margin of the right timing of the CA signal.

In the present invention, the phase of the sampling clock signal (such as CLK signal) pulled to the left refers to advancing the phase of the sampling clock signal relative to the current phase, and the phase of the sampling clock signal (such as CLK signal) pulled to the right refers to lagging the phase of the sampling clock signal relative to the current phase.

If |A0-B0|<K and |A1-B1|<K, the second channel returns to the idle state until the next time the counter reaches the preset duration, the second channel enters the margin test mode again, where K is the timing deviation threshold that can be configured in the register.

If |A0-B0|≥K and |A1-B1|≥K, the offset register is set to 1, and the second channel enters the margin tuning mode to adjust the delay of the CA signal.

In the present invention, |A0-B0| or |A1-B1| is the maximum timing margin of the signal to be sampled, and is also the absolute value of the difference between the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled. In this example, the signal to be sampled is a CA signal, and may also be a CTRL signal or a DQ signal.

Optionally, the registers A0 and A1 storing the maximum left timing margins and the registers B0 and B1 storing the maximum right timing margins may be reset to zero.

After the second channel enters the margin tuning mode, the delay time of the third delay module is adjusted with a set step size (such as the result after rounding K/2 and the result after rounding -K/2), thereby adjusting the delay of the CA signal, and testing the maximum margin of the left timing of the CA signal and the maximum margin of the right timing of the CA signal of the second channel. If the maximum margin of the CA signal timing < K appears twice in succession, the configuration of the delay time of the third delay module at this time will be fixed, and the switching register will be set to 1. Fixing the configuration of the delay time of the third delay module at this time means fixing the delay of the CA signal.

For example, the registers for storing the left maximum timing margins A0 and A1 and the registers for storing the right maximum timing margins B0 and B1 are used as described above. If |A0-B0|<K and |A1-B1|<K, the configuration of the delay time length of the third delay module is fixed.

When the offset register is 1, the switch register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, and the second channel is used as the main data channel, that is, the normal working mode, and the data transmission function is performed.

For example, the channel selection register may be controlled to be 1 through a path selection signal, so as to achieve the purpose of setting the second channel as the main data channel.

When the second channel is set as the data master channel, the second receiving sampler samples normally, the third delay module is in static state, the first channel is set to idle state, and the counter starts timing. When the counter reaches the preset time, the first channel enters the margin test mode, and when |A0-B0|≥K and |A1-B1|≥K, it enters the margin tuning mode.

Then, set the offset register to 0 and the switch register to 0.

So far, the change of switching the data main channel from the first channel to the second channel has been successfully achieved.

Thereafter, according to the same mode as above, when the timing deviation is large, the data main channel can also be switched from the second channel to the first channel.

For example, after the first channel enters the idle mode, when the timer reaches a preset duration, the first channel enters the margin test mode.

After the first channel enters the margin test mode, if the maximum margin of the timing of the signal to be sampled is not less than K, the first channel enters the margin tuning mode. In addition, when the offset register is 1, the switch register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, the first channel is set to the normal working mode, and the second channel is set to the idle mode.

Although the present invention takes the CA signal and the CLK signal as an example, it is also applicable to other signal combinations, such as the CTRL signal and the CLK signal, and the DQ signal and the DQS signal.

“0” or “1” in the present invention refers to any signal that can indicate logic “0” or “1”.

In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (7)

1. A high-speed memory bus timing adaptive method for adjusting a signal to be sampled and a sampling clock signal, characterized in that: When the signal to be sampled is a CA signal or a CTRL signal, the sampling clock signal is a CLK signal; when the signal to be sampled is a DQ signal, the sampling clock signal is a DQS signal; At the initial power-on, the first receiving sampler and the second receiving sampler are reset, the switch register is set to 0, the offset register is set to 0, and the channel selection register is set to 0; Setting the first channel including the first receiving sampler to a normal working mode, and setting the second channel including the second receiving sampler to an idle mode; Perform timing training for the first channel and start the counter when the training is completed; When the timer reaches the preset duration, the second channel enters the margin test mode, and in the margin test mode, the sampling clock signal phase is pulled left and the sampling clock signal phase is pulled right to measure the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled, and the maximum timing margin of the signal to be sampled is calculated; If the maximum timing margin of the signal to be sampled is less than K, the second channel returns to the idle state until the next time the counter reaches the preset duration, and the second channel enters the margin test mode; otherwise, the offset register is set to 1, and the second channel enters the margin tuning mode, and in the margin tuning mode, the delay of the signal to be sampled is adjusted with the set step size, and the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled are measured, and the maximum timing margin of the signal to be sampled is calculated, and when the maximum timing margin of the signal to be sampled is less than K, the delay of the signal to be sampled is fixed, and the switching register is set to 1, where K is the timing deviation threshold configured in the register; When the offset register is 1, the switch register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, the second channel is set to the normal working mode, and the first channel is set to the idle mode. 2. The high-speed memory bus timing adaptive method according to claim 1, characterized in that: If the maximum timing margin of the signal to be sampled is less than K, the second channel returns to the idle state, which means: the maximum left timing margin of the signal to be sampled and the maximum right timing margin of the signal to be sampled are measured at least twice, and the maximum timing margins of the signal to be sampled calculated at least twice are both less than K, then the second channel returns to the idle state. 3. The high-speed memory bus timing adaptive method according to claim 2, characterized in that: The delay of the signal to be sampled is adjusted by setting a step length, wherein the set step length is a result of rounding K/2 and a result of rounding -K/2. 4. The high-speed memory bus timing adaptive method according to claim 3, characterized in that: The first channel includes a first delay module, a second delay module, a first receiving sampler and a first verification module; The second channel includes a third delay module, a fourth delay module, a second receiving sampler and a second verification module; wherein, The signal to be sampled is used as the input signal of the first receiving sampler after passing through the first delay module, and the sampling clock signal is used as the input signal of the first receiving sampler after passing through the second delay module; The signal to be sampled is used as the input signal of the second receiving sampler after passing through the third delay module, and the sampling clock signal is used as the input signal of the second receiving sampler after passing through the fourth delay module; The first verification module receives the output signal of the first receiving sampler and uses it as the input signal of the multiplexer; the second verification module receives the output signal of the second receiving sampler and uses it as the input signal of the multiplexer. 5. The high-speed memory bus timing self-adaptation method according to claim 4, characterized in that: After the first channel enters the idle mode, when the timer reaches a preset time length, the first channel enters the margin test mode. 6. The high-speed memory bus timing adaptive method according to claim 5, characterized in that: After the first channel enters the margin test mode, if the maximum margin of the timing of the signal to be sampled is not less than K, the first channel enters the margin tuning mode; and, When the offset register is 1, the switch register is 1, and the bus state is in the self-refresh state, the channel selection register is set to 1, the first channel is set to the normal working mode, and the second channel is set to the idle mode. 7. The high-speed memory bus timing self-adaptation method according to claim 6, characterized in that: The adjusting the delay of the signal to be sampled with a set step length refers to: adjusting the delay time length of the third delay module with a set step length.