CN118796278A - Processor instruction fetching method, device, equipment and storage medium - Google Patents

Abstract

The present invention provides a processor instruction fetching method, device, equipment and storage medium, and relates to the field of computer technology. The method is applied to a processor in an electronic device, and the electronic device comprises a processor and a memory, and the memory comprises a cache memory. The method comprises: receiving an instruction fetching request; the instruction block of the instruction fetching request comprises ordinary instructions and compressed instructions; determining a valid result of the instruction fetching request according to the instruction fetching request; the valid result is used to characterize whether the instruction fetching request needs to fetch instructions across rows from the cache memory, and the cache memory comprises an odd-body storage body and an even-body storage body; when the valid result is valid, fetching a target instruction from two consecutive cache memory lines where the instruction block is located according to the instruction fetching request; the instruction block is determined based on an instruction fetching address in the instruction fetching request; when the valid result is invalid, fetching the target instruction from the cache memory line where the instruction block is located according to the instruction fetching request.

Description

Processor instruction fetching method, device, equipment and storage medium

Technical Field

The present invention relates to the field of computer technology, and in particular to a processor instruction fetching method, device, equipment and storage medium.

Background Art

In the design of instruction set architecture (ISA) of modern processors, compressed instructions (C instructions for short) are introduced to reduce the size of program code and improve code density. These compressed instructions can reduce the miss rate of instruction cache, thereby improving processor performance, reducing power consumption, and reducing chip area and cost.

For example, the use of the compressed instruction subset (RVC, including RV64C and RV32C) of the RISC-V instruction set (Reduced Instruction Set Computer Five, the fifth generation of reduced instruction set) can reduce the size of the program code segment by 25% to 30%, and reduce the instruction cache miss by 20% to 25%, which is equivalent to a performance improvement of doubling the instruction cache capacity. Advanced RISC Machines (ARM) and Microprocessor without Interlocked Pipeline Stages (MIPS) also reduce code size by providing 16-bit compressed instruction sets (such as ARM's Thumb and Thumb2, MIPS's MIPS16 and microMIPS). Compared with their 32-bit standard instruction sets, the compressed ISA can reduce the code size by about 25% to 30%.

However, the use of compressed instructions brings new problems: due to the different lengths of ordinary instructions and compressed instructions, there is a situation where an instruction spans two cache lines, which increases the difficulty of designing the instruction fetch unit.

Therefore, how to implement cross-cache line instruction fetching has become a technical problem that urgently needs to be solved in the industry.

Summary of the invention

The present invention provides a processor instruction fetching method, device, equipment and storage medium, which effectively realizes cross-cache line instruction fetching and improves processor performance.

The present invention provides a processor instruction fetching method, which is applied to a processor in an electronic device, wherein the electronic device comprises the processor and a memory, wherein the memory comprises a cache memory; the method comprises the following steps:

receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions;

Determine, according to the instruction fetch request, a valid result of the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

According to a processor instruction fetching method provided by the present invention, determining a valid result of the instruction fetching request according to the instruction fetching request includes:

Determine the identification bit of the instruction block according to the instruction fetch address; the identification bit is used to mark whether the instruction block contains a cross-line instruction, and the cross-line instruction is that all bytes of the cross-line instruction fall in two different cache lines;

A valid result of the instruction fetch request is determined according to the identification bit of the instruction block.

According to a processor instruction fetching method provided by the present invention, the value of the identification bit includes 1 or 0, and determining the valid result of the instruction fetching request according to the identification bit of the instruction block includes:

When the value of the flag bit is 1, the valid result is determined to be valid;

When the value of the flag bit is 0, the valid result is determined to be invalid.

According to a processor instruction fetching method provided by the present invention, the instruction fetching request includes the instruction fetching address, the instruction fetching address is the access address of the target cache line corresponding to the instruction fetching request, the instruction fetching address includes a tag, an index, and a block offset, the tag is used to perform a multi-way tag comparison with the cache line in the cache, the index is used to indicate the row number of the cache line corresponding to the instruction fetching request, the index includes a high-order index and a low-order index, the high-order index is used to indicate the row address of the cache line, the low-order index is used to indicate the address of a storage body, and the block offset (Block Offset) is used to indicate the specific position of the instruction block of the instruction fetching request in the cache line;

The fetching of the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request comprises:

Determining a way corresponding to the instruction fetch request according to a tag in the instruction fetch address;

Determine the cache line and the corresponding storage body corresponding to the instruction fetch request according to the index in the instruction fetch address and the corresponding way; wherein each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line, the tag storage body is used to store tag information of each cache line, and the data storage body is used to store instructions in each cache line;

The target instruction is fetched according to the cache line corresponding to the instruction fetch request, the corresponding storage bank, and the offset within the block.

According to a processor instruction fetching method provided by the present invention, before receiving an instruction fetching request, the method further includes:

receiving an instruction prefetch request, wherein the instruction prefetch request includes a prefetch address of the prefetch request;

Searching the pre-fetched address in the cache to obtain a matching result;

When the matching result is no match, an instruction prefetch operation is performed.

According to a processor instruction fetching method provided by the present invention, the memory further includes a next-level storage system; the instruction prefetching operation includes:

Sending an allocation request to a cross-cache line prefetch item by using an instruction prefetcher, wherein the allocation request is used for the cross-cache line prefetch item to apply for allocation of a prefetch item for the prefetch request;

According to the prefetch item, the prefetch request is sent to the next-level storage system; the prefetch request is used for the next-level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line; the instruction access request includes an access request for a single cache line or an access request across cache lines.

According to a processor instruction fetching method provided by the present invention, sending the prefetch request to the next-level storage system according to the prefetch item includes:

The prefetch flag of the prefetch request is predicted according to the prefetch item; the prefetch flag is used to indicate whether the prefetch request needs to perform a prefetch instruction across cache lines.

According to a processor instruction fetching method provided by the present invention, predicting a prefetch flag of the prefetch request according to the prefetch item includes:

Initially setting the prefetch flag bits of all cache lines corresponding to the prefetch request to 1;

When a first target number of times that no cross-row prefetch instruction occurs in any cache line corresponding to the prefetch request reaches a first number threshold, the prefetch flag bit of the cache line is determined to be 0; the prefetch flag bit of the cache line being 0 indicates that no cross-row prefetch instruction is performed on the cache line;

When a second target number of cross-row prefetch instructions occurs in any cache line corresponding to the prefetch request reaches a second number threshold, the prefetch flag of the cache line is determined to be 1; the prefetch flag of the cache line being 1 indicates that the cache line resumes the cross-row prefetch instruction.

According to a processor instruction fetching method provided by the present invention, the pre-fetching address is queried in the cache to obtain a matching result, including:

Using a prefetcher to record addresses of prefetch requests that have been sent;

The pre-fetch address is matched with the address of the sent pre-fetch request. If no match is found, the pre-fetch address is queried in the cache to obtain a matching result.

In a second aspect, the present invention further provides a processor instruction fetching device, which is applied to a processor in an electronic device, wherein the electronic device comprises the processor and a memory, wherein the memory comprises a cache memory; the device comprises the following modules:

A receiving module, used for receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions;

an instruction fetch module, for determining a valid result of the instruction fetch request according to the instruction fetch request; the valid result is used to characterize whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor instruction fetching method described above is implemented.

In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the processor instruction fetching methods described above.

In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the processor instruction fetching method described in any one of the above is implemented.

The present invention provides a processor instruction fetching method, device, equipment and storage medium. The method is applied to a processor in an electronic device. The electronic device includes a processor and a memory. The memory includes a cache. The method includes: first, receiving an instruction fetching request, wherein the instruction block of the instruction fetching request includes ordinary instructions and compressed instructions; then, determining a valid result of the instruction fetching request according to the instruction fetching request, wherein the valid result is used to characterize whether the instruction fetching request needs to fetch instructions across rows from the cache. The cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies; further, when the valid result is valid, fetching a target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetching request, wherein the instruction block is determined based on the instruction fetching address in the instruction fetching request; on the contrary, when the valid result is invalid, fetching the target instruction from the cache line where the instruction block is located according to the instruction fetching request.

The cache in the present invention includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-body storage bodies. The effective result of the instruction fetch request is determined according to the instruction fetch request, that is, whether it is necessary to fetch instructions across lines from the cache. When it is necessary to fetch instructions across lines, the target instruction is fetched from two consecutive cache lines where the instruction block is located according to the instruction fetch request. When it is determined that it is not necessary to fetch instructions across lines, a single-line read instruction operation is performed, which can achieve the goal of simultaneously fetching instructions across cache lines, thereby improving processor performance.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic flow chart of a processor instruction fetching method provided by the present invention.

FIG. 2 is a schematic diagram showing the principle of instructions crossing cache lines provided by the present invention.

FIG. 3 is a schematic diagram showing the principle of a cache memory provided by the present invention.

FIG. 4 is a schematic diagram showing the principle of the instruction fetch address provided by the present invention.

FIG5 is a schematic diagram showing the principle of the processor prefetch instruction method provided by the present invention.

FIG6 is a schematic diagram of the structure of a processor instruction fetching device provided by the present invention.

FIG. 7 is a schematic diagram of the structure of an electronic device provided by the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first" and "second" are generally a class, and the number of objects is not limited. For example, the first node can be one or more. In addition, "and/or" in the specification and claims represents at least one of the connected objects, and the character "/" generally represents that the front and back associated objects are in an "or" relationship.

The processor instruction fetching method, apparatus, device and storage medium of the present invention are described below in conjunction with FIG. 1 to FIG. 7 .

FIG1 is a flow chart of a processor instruction fetching method provided by the present invention, which is applied to a processor in an electronic device, wherein the electronic device includes a processor and a memory, and the memory includes a cache. As shown in FIG1 , the method includes the following steps:

Step 101, receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions;

Specifically, it should be noted that the processor instruction fetching method provided by the present invention is applicable to the scenario of processor instruction fetching, in particular, to the scenario of processor instruction fetching supporting compressed instructions. The execution subject of the method can be a processor in an electronic device, and the electronic device includes not only a processor but also an advanced cache.

Among them, the processor, such as the central processing unit (CPU), the cache memory (Cache, referred to as "cache"), is also a first-level storage system, which is set between the processor and the memory. Cache is a small-capacity cache memory composed of fast static random access memory (SRAM) storage elements, which can be directly integrated into the CPU chip. In the cache, the active program blocks and data blocks that are frequently accessed in the memory are copied to the cache to increase the speed of the CPU to read and write instructions and data. Due to the locality of program access, in most cases, the CPU can directly obtain instructions and data from the cache without accessing the memory. And with the development of technology, more and more data processing relies on a multi-level cache storage hierarchy (Cache Hierarchy) system. Correspondingly, the memory includes a next-level storage system such as (L2 Cache), and the capacity of the L2 Cache is relatively large.

It is understandable that for a processor that supports compressed instructions, it is possible that the range of an instruction spans two cache lines. For example, the cache line size of the processor is 64 bytes (i.e., 512 bits), wherein the cache line stores both compressed instructions (assuming that the compressed instruction RVC is 16 bits, 16-bit instruction) and ordinary instructions (assuming that the ordinary instruction RVI is 32 bits, 32-bit instruction), so it is possible that ordinary instructions span cache lines. FIG2 is a schematic diagram of the principle of instructions spanning cache lines provided by the present invention. As shown in FIG2, assuming that a 512-bit instruction cache line is a 32-bit ordinary instruction from the 0th to the 279th bit, the 480th to the 495th bit is a 16-bit ordinary instruction, and the next 32-bit ordinary instruction from the 496th bit onwards, there will be a situation where the cache line spans, that is, 16 bits of this ordinary instruction are in one cache line, and the other 16 bits are in the next cache line. In the processor instruction fetching method provided by the present invention, the cache supports fetching two cache lines at a time to ensure processor performance.

First, an instruction fetch request is received. The instruction fetch request contains an instruction fetch address. The instruction block of the instruction fetch request includes ordinary instructions and compressed instructions. Whether the instruction is a compressed instruction can be determined based on the compressed instruction identification bit in the instruction encoding. For example, in the RISC-V instruction set, the lowest two bits of the instruction encoding, i.e., Instruction[1:0]==2’b11 (binary 11), are ordinary 32-bit instructions, otherwise they are compressed instructions (also called RVC instructions).

Step 102: determining a valid result of the instruction fetch request according to the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

Specifically, after receiving the instruction fetch request, it can be further determined whether it is a valid request according to the flag bit of the instruction block in the instruction fetch request, that is, whether it is necessary to fetch instructions across rows from the cache.

It should be noted that the tag storage body and data storage body of the cache in the present invention are divided into odd and even bodies. FIG3 is a schematic diagram of the principle of the cache storage body provided by the present invention. As shown in FIG3, the cache storage body is divided into 2 bodies, 4 bodies, ..., 2 power ( ²ⁿ ) bodies, and the storage body address is represented by the low bit of the cache index (Index). If it is divided into 2 bodies, the body address is the lowest 1 bit of the cache index (Index); if it is divided into 4 bodies, the body address is the lowest 2 bits of the cache index (Index); if it is divided into n bodies, the body address is the lowest n bits of the cache index (Index), and n is a positive integer.

It can be seen that the use of the above-mentioned parity method can ensure that two consecutive cache line addresses are in two different cache storage bodies, odd and even. A single-port static random access memory (SRAM) can be used to implement cross-cache line instruction fetching, which greatly saves the power consumption and area of the processor.

Furthermore, in the case where the last instruction is not a common instruction across cache lines, only a read request for a cache line will be sent, which is considered to be an invalid signal.

Step 103: if the valid result is valid, fetch the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

Specifically, when the processor determines in step 102 that the instruction fetch request is a valid request, an operation of fetching instructions across rows is performed.

For example, a cross-row access request is issued to the cache memory according to the instruction fetch address in the instruction fetch request, and the instruction fetch address can be used to determine the cache row address, storage body address, and block offset corresponding to the cross-row access request. Then, based on the cache row address, storage body address, and block offset corresponding to the cross-row access request, the corresponding target instruction is fetched from the corresponding access address in the cache memory, so as to implement cross-cache row instruction fetching, thereby improving processor performance.

Step 104: When the valid result is invalid, fetch the target instruction from the cache line where the instruction block is located according to the instruction fetch request.

Specifically, when the processor determines in step 102 that the instruction fetch request is an invalid request, a single-line read instruction operation is performed.

For example, a single-line access request is issued to the cache memory according to the instruction fetch address in the instruction fetch request, and the instruction fetch address can be used to determine the cache line address, storage body address, and block offset corresponding to the single-line access request. Then, based on the cache line address, storage body address, and block offset corresponding to the single-line access request, the corresponding target instruction is fetched from the corresponding access address in the cache memory to implement a cache line read operation, thereby greatly saving the power consumption and area of the processor.

The method provided in this embodiment is applied to a processor in an electronic device, the electronic device includes a processor and a memory, the memory includes a cache, and the method includes: first, receiving an instruction fetch request, wherein the instruction block of the instruction fetch request includes ordinary instructions and compressed instructions; then, determining a valid result of the instruction fetch request according to the instruction fetch request, wherein the valid result is used to characterize whether the instruction fetch request needs to fetch instructions across rows from the cache, the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies; then, when the valid result is valid, fetching a target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request, the instruction block being determined based on the instruction fetch address in the instruction fetch request; conversely, when the valid result is invalid, fetching the target instruction from the cache line where the instruction block is located according to the instruction fetch request.

The cache in the present invention includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-body storage bodies. The effective result of the instruction fetch request is determined according to the instruction fetch request, that is, whether it is necessary to fetch instructions across lines from the cache. When it is necessary to fetch instructions across lines, the target instruction is fetched from two consecutive cache lines where the instruction block is located according to the instruction fetch request. When it is determined that it is not necessary to fetch instructions across lines, a single-line read instruction operation is performed, which can achieve the goal of simultaneously fetching instructions across cache lines, thereby improving processor performance.

According to a processor instruction fetching method provided by the present invention, determining a valid result of the instruction fetching request according to the instruction fetching request includes:

According to the instruction fetch address, the identification bit of the instruction block is determined; the identification bit is used to mark whether the instruction block contains a cross-line instruction, and the cross-line instruction is a cross-line instruction whose entire bytes fall into two different cache lines;

The valid result of the instruction fetch request is determined based on the identification bit of the instruction block.

Specifically, in some embodiments, the specific implementation process of step 102 determining the valid result of the instruction fetch request according to the instruction fetch request includes the following steps:

First, according to the instruction fetch address, determine the identification bit of the instruction block. It should be noted that the identification bit is used to mark whether the instruction block contains cross-line instructions, and the cross-line instructions are cross-line instructions whose all bytes fall in two different cache lines. Specifically, for example, first determine the instruction block of the instruction fetch request according to the instruction fetch address, and the instruction block is also an instruction set. When an instruction block finds that its last 2 bytes (2 bytes, i.e. 16 bits) are the first half of a normal instruction (RVI) instruction during the instruction fetch stage, a identification bit is set. In this case, two cache lines are fetched at the same time to ensure that the second half can be fetched. Otherwise, only one cache line is fetched to save instruction fetch bandwidth.

Furthermore, the valid result of the instruction fetch request can be determined based on the identification bit of the instruction block. For example, the value of the identification bit and the valid results corresponding to each different value can be preset, and then, after the identification bit is determined, the valid result of the instruction fetch request can be determined by simply matching the identification bit value with the identification meaning of the value, that is, judging whether the instruction fetch request requires fetching instructions across rows from the cache.

The method provided in this embodiment first determines the identification bit of the instruction block according to the instruction fetch address of the instruction fetch request, wherein the identification bit is used to mark whether the instruction block contains cross-line instructions, and the cross-line instructions are cross-line instructions whose all bytes fall in two different cache lines; then, according to the identification bit of the instruction block, the valid result of the instruction fetch request is determined, that is, the signal of whether each request is valid is identified by the flag bit, because for the case where the last instruction is not an ordinary instruction across cache lines, only a cache line read request will be sent, thereby realizing the processor to fetch instructions across lines, while avoiding wasting bandwidth and reducing the power consumption of the processor.

According to a processor instruction fetching method provided by the present invention, the value of the identification bit includes 1 or 0, and determining the valid result of the instruction fetching request according to the identification bit of the instruction block includes:

When the value of the flag bit is 1, the valid result is determined to be valid;

When the value of the flag bit is 0, the valid result is determined to be invalid.

Specifically, in some embodiments, the identification bit can preset all possible values and pre-store corresponding rules, the rules representing different meanings of valid results corresponding to different identification bit values. For example, the possible values of the preset identification bit include 1 or 0, and the value of the instruction fetch request is 1, which represents that the valid result is valid, and the value of the instruction fetch request is 0, which represents that the valid result is invalid.

Correspondingly, in some embodiments, the specific implementation process of determining the valid result of the instruction fetch request according to the identification bit of the instruction block includes the following steps:

The flag bit request of the instruction fetch request is matched with a preset value to obtain a corresponding valid result. For example, when the value of the flag bit is 1, the valid result is determined to be valid, and when the value of the flag bit is 0, the valid result is determined to be invalid, thereby determining whether the instruction fetch request is a valid request based on the flag bit, thereby determining whether to perform a cross-row instruction fetch operation, improving the performance of the processor and avoiding wasting bandwidth.

The method provided in this embodiment determines the valid result as valid when the value of the flag bit is 1, and determines the valid result as invalid when the value of the flag bit is 0. This method determines whether the instruction fetch request is a valid request based on the flag bit, thereby determining whether to perform a cross-row instruction fetch operation, thereby improving the performance of the processor and avoiding wasting bandwidth.

According to a processor instruction fetching method provided by the present invention, an instruction fetching request includes an instruction fetching address, which is an access address of a target cache line corresponding to the instruction fetching request, and includes a tag, an index, and an offset within a block. The tag is used to perform a multi-way tag comparison with a cache line in a cache memory, and the index is used to indicate the row number of the cache line corresponding to the instruction fetching request. The index includes a high-order index and a low-order index, and the high-order index is used to indicate the row address of the cache line, and the low-order index is used to indicate the address of a storage body. The block offset (Block Offset) is used to indicate the specific position of the instruction block of the instruction fetching request in the cache line;

According to the instruction fetch request, a target instruction is fetched from two consecutive cache lines where the instruction block is located, including:

Determine the way corresponding to the instruction fetch request according to the tag in the instruction fetch address;

According to the index in the instruction fetch address and the corresponding way, determine the cache line and the corresponding storage body corresponding to the instruction fetch request; wherein each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line, the tag storage body is used to store the tag information of each cache line, and the data storage body is used to store the instruction in each cache line;

The target instruction is fetched according to the cache line corresponding to the instruction fetch request, the corresponding storage bank and the offset within the block.

Specifically, in some embodiments, the instruction fetch request includes an instruction fetch address, which is an access address of a target cache line corresponding to the instruction fetch request, so as to facilitate fetching the target instruction of the corresponding address according to the instruction fetch address.

Exemplarily, Figure 4 is a schematic diagram of the principle of the instruction fetch address provided by the present invention. As shown in Figure 4, the instruction fetch address includes a tag, an index, and a block offset. The tag is used to perform multi-way tag comparison with the cache line in the cache memory, and the index is used to indicate the row number of the cache line corresponding to the instruction fetch request. In the present invention, the index includes a high-order index and a low-order index. The high-order index is used to indicate the row address of the cache line, and the low-order index is used to indicate the address of the storage body. The block offset is used to indicate the specific position of the instruction block of the instruction fetch request in the cache line, that is, the specific position of the content of the access instruction cache in the cache line.

It should be noted that, in this embodiment, each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line. The tag storage body is used to store the tag information of each cache line, and the data storage body is used to store the instructions in each cache line. The tag storage body and the data storage body of the instruction cache are divided into odd and even bodies, such as 2 bodies, 4 bodies, ..., 2 power ( ²ⁿ ) bodies, and the storage body address is represented by the low bit of the cache index (Index). If it is divided into 2 bodies, the body address is the lowest 1 bit of the cache index (Index); if it is divided into 4 bodies, the body address is the lowest 2 bits of the cache index (Index); if it is divided into ²ⁿ bodies, the body address is the lowest n bits of the cache index (Index), and n is a positive integer. The instruction cache virtual address index, two adjacent cache lines in the virtual address space will be divided into different odd and even bodies to realize the reading of two cache lines at a time, ensuring that two adjacent cache lines can be accessed simultaneously in one clock cycle.

Correspondingly, in step 103, the target instruction is fetched from two consecutive cache lines where the instruction block is located according to the instruction fetch request, including:

First, the way corresponding to the instruction fetch request is determined according to the tag in the instruction fetch address, that is, the tag in the instruction fetch address is used to perform multi-way tag comparison to match the corresponding way.

Further, according to the index in the instruction fetch address and the corresponding way, the cache line and the corresponding storage body corresponding to the instruction fetch request are determined; wherein, after the corresponding way is determined, the cache line and the corresponding storage body corresponding to the instruction fetch request can be determined in combination with the index in the instruction fetch address. wherein, the index includes a high-order index and a low-order index, the high-order index is used to indicate the row address of the cache line, and the low-order index is used to indicate the address of the storage body.

Furthermore, the target instruction is retrieved according to the cache line corresponding to the instruction fetch request, the corresponding storage body and the offset within the block. Based on the above steps, the storage body corresponding to the instruction fetch request has been determined, and the corresponding target instruction is further accessed according to the offset within the block, that is, the address within the block, to implement the cross-line instruction fetch operation. Two adjacent cache lines in the virtual address space will be divided into different parity bodies to implement the reading of two cache lines at a time, which can ensure that two adjacent cache lines can be accessed simultaneously in one clock cycle to implement cross-line instruction fetching.

The method provided by this embodiment comprises an instruction fetch request including an instruction fetch address, which is an access address of a target cache line corresponding to the instruction fetch request, and the instruction fetch address includes a tag, an index, and an offset within a block. The tag is used to perform a multi-way tag comparison with a cache line in a cache memory, and the index is used to indicate the row number of the cache line corresponding to the instruction fetch request. The index includes a high-order index and a low-order index, and the high-order index is used to indicate the row address of the cache line, and the low-order index is used to indicate the address of the storage body. The offset within the block is used to indicate the specific position of the instruction block of the instruction fetch request within the cache line. When the effective result of the instruction fetch request is effective, the present invention determines the way corresponding to the instruction fetch request according to the tag in the instruction fetch address, and determines the cache line and the corresponding storage body corresponding to the instruction fetch request according to the index in the instruction fetch address and the corresponding way, wherein each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line, and the tag storage body is used to store the tag information of each cache line, and the data storage body is used to store the instruction in each cache line; further, the target instruction is fetched according to the cache line corresponding to the instruction fetch request, the corresponding storage body, and the offset within the block. The present invention can ensure that two adjacent Cache Lines can be accessed simultaneously in one clock cycle, thereby realizing cross-cache line instruction fetching and further improving processor performance.

According to a processor instruction fetching method provided by the present invention, before receiving an instruction fetching request, the method further includes:

receiving an instruction prefetch request, wherein the instruction prefetch request includes a prefetch address of the prefetch request;

The pre-fetched address is searched in the cache to obtain a matching result;

When the matching result is no match, an instruction prefetch operation is performed.

Specifically, in some embodiments, before receiving the instruction fetch request before step 102, the method further includes: instruction prefetching. That is, in addition to supporting cross-cache line instruction fetching of compressed instructions, the present invention also supports cross-cache line prefetching. The benefit of supporting instruction prefetching is that instruction throughput can be guaranteed while avoiding bandwidth waste, thereby improving processor performance and reducing processor power consumption and area.

Exemplarily, the pre-fetch mechanism is as follows:

First, an instruction prefetch request is received, wherein the instruction prefetch request includes a prefetch address of the prefetch request, such as an access address.

Furthermore, after receiving the instruction prefetch request, the processor searches the cache memory based on the prefetch address to obtain a matching result. It is understandable that the matching results include the following two types: the first type: the prefetch address is matched in the cache memory, and the second type: the prefetch address is not matched in the cache memory. A prefetch pointer is added to the instruction fetch target queue, and the position of the pointer is between the prediction pointer and the instruction fetch pointer. The prefetch pointer reads the target address of the current instruction packet (if jumping, it is the jump target, if not jumping, it is the starting address of the next instruction packet in sequence), and sends it to the prefetcher.

For the first matching result, it means that the address to be pre-fetched already exists in the cache. In order to reduce the power consumption of the processor, the pre-fetch request is cancelled.

For the second matching result, it means that the address to be pre-fetched does not exist in the cache. In order to ensure instruction throughput, if the matching result is not matched, the instruction pre-fetch operation is performed. That is, if the address cannot be found in the first-level storage system (such as L1 Cache, that is, the cache), it is necessary to query the next-level storage system (such as L2Cache, that is, the second-level cache) for pre-fetching.

That is, the prefetcher will complete the address translation and access the tag storage body ITAG SRAM of the instruction cache. If it is found that the address is already in the instruction cache, the prefetch request will be canceled.

The method provided in this embodiment includes a prefetch mechanism, for example, receiving an instruction prefetch request, the instruction prefetch request includes a prefetch address of the prefetch request, querying the prefetch address in a cache, obtaining a matching result, and performing an instruction prefetch operation when the matching result is no match. The cache in the present invention supports fetching two cache lines at a time, and can prefetch cache lines, which can ensure instruction throughput in this case, while avoiding wasting bandwidth, thereby improving processor performance and reducing processor power consumption and area.

According to a processor instruction fetching method provided by the present invention, the memory also includes a next-level storage system; performing an instruction prefetch operation includes:

Sending an allocation request to the cross-cache line prefetch item by using the instruction prefetcher, the allocation request being used for the cross-cache line prefetch item to apply for allocation of a prefetch item for the prefetch request;

According to the prefetch items, a prefetch request is sent to the next level storage system; the prefetch request is used for the next level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line; the instruction access request includes an access request for a single cache line or an access request across cache lines.

Specifically, in some embodiments, prefetching refers to prefetching cache lines from the next level storage system in the memory. The next level storage system can be all accessible data storages of the computer. In this embodiment, the next level storage system is, for example, a second-level cache L2 Cache. L2 Cache is an important component in the CPU cache architecture. It is located after the first-level cache (L1 Cache) of the CPU core and usually has a larger storage capacity than L1 Cache, but the access speed is relatively slow. The role of L2 Cache is to further reduce the number of times the CPU accesses the memory, thereby improving the operating efficiency of the computer. In practical applications, the size and performance of L2 Cache have a significant impact on the overall performance of the CPU.

Correspondingly, the specific implementation process of the processor performing instruction prefetching operation in the prefetch mechanism can be implemented through the following steps. FIG. 5 is a schematic diagram of the principle of the processor prefetching instruction method provided by the present invention. As shown in FIG. 5 , the prefetch mechanism includes:

First, an allocation request is sent to a cross-cache line prefetch item by using an instruction prefetcher, where the allocation request is used for the cross-cache line prefetch item to apply for allocation of a prefetch item for the prefetch request, for example, to apply for allocation of an item to a prefetch item (RrefetchEntry).

Furthermore, according to the prefetch entry, a prefetch request is sent to the next level storage system. Specifically, the prefetch entry (RrefetchEntry) sends a prefetch request to the next level storage system, such as the secondary cache L2 Cache, to prefetch the corresponding cache line to the next level storage system, such as L2 Cache. Among them, the prefetch request is used for the next level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line. The instruction access request includes an access request for a single cache line or an access request across cache lines. In this way, the required instruction cache lines can be prefetched in time, and the memory access bandwidth can be saved by prefetching only the adjacent cache lines that need to be fetched.

The method provided in this embodiment queries the prefetch address in the cache to obtain a matching result. When the matching result is no match, an instruction prefetcher is used to send an allocation request to the cross-cache line prefetch item. The allocation request is used for the cross-cache line prefetch item to apply for a prefetch item for the prefetch request. Then, according to the prefetch item, a prefetch request is sent to the next-level storage system; the prefetch request is used for the next-level storage system to obtain an instruction access request based on the prefetch request and the historical flag of the cache line, wherein the instruction access request includes an access request for a single cache line or an access request for a cross-cache line, so that the required instruction cache line can be prefetched in time, and the memory access bandwidth can be saved, and only the adjacent cache lines that need to be fetched can be prefetched. The present invention can prefetch cache lines, can ensure the instruction throughput in the case of supporting cross-line instruction fetching, and avoid wasting bandwidth, which not only improves the processor performance, but also reduces the power consumption and area of the processor.

According to a processor instruction fetching method provided by the present invention, a prefetching request is sent to a next-level storage system according to a prefetching item, comprising:

According to the prefetch item, the prefetch flag of the prefetch request is predicted; the prefetch flag is used to indicate whether the prefetch request needs to perform a prefetch instruction across cache lines.

Specifically, in some embodiments, sending a pre-fetch request to a next-level storage system according to the pre-fetch item may be implemented by the following steps, including:

It is understandable that the prefetch request is used for the next level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line, and the instruction access request includes a single cache line access request or a cross-cache line access request.

In other words, for each prefetch request, the flag bit indicating whether cross-cache line prefetch is required is also predicted to determine whether to issue a cache line access request or a cross-cache line access request at the same time. In this way, the required instruction cache line can be prefetched in time, and only the adjacent cache lines that need to be fetched can be prefetched without wasting memory access bandwidth.

In the method provided in this embodiment, the required instruction cache lines can be pre-fetched in time, and only the adjacent cache lines that need to be fetched can be pre-fetched without wasting memory access bandwidth.

According to a processor instruction fetching method provided by the present invention, a prefetch flag bit of a prefetch request is predicted according to a prefetch item, comprising:

Initially set the prefetch flag bits of all cache lines corresponding to the prefetch request to 1;

When a first target number of times that no cross-row prefetch instruction occurs in any cache line corresponding to the prefetch request reaches a first number threshold, the prefetch flag bit of the cache line is determined to be 0; the prefetch flag bit of the cache line being 0 indicates that no cross-row prefetch instruction is performed on the cache line;

When the second target number of cross-row prefetch instructions occurs in any cache line in the cache lines corresponding to the prefetch request reaches the second number threshold, the prefetch flag of the cache line is determined to be 1; the prefetch flag of the cache line is 1, indicating that the cache line resumes the cross-row prefetch instruction.

Specifically, in some embodiments, an example of a process of predicting whether a flag of a prefetch request needs to perform prefetching across cache lines is as follows:

For each cache line in each prefetch request, a flag bit may be used to predict whether cross-cache line prefetching is required based on historical information.

For example, all cross-cache line prefetch flags are initialized to 1, and a saturation counter is used for counting. When the cache line does not have an instruction cross-cache line situation for a certain number of times, the cross-cache line prefetch flag of the cache line is set to 0, and cross-cache line prefetch is no longer performed until the cache line has an instruction cross-cache line situation for a certain number of times, and then the cross-cache line prefetch flag of the cache line is set to 1 to resume cross-cache line prefetch.

In the method provided in this embodiment, the flag bit of whether cross-cache line prefetching is needed can be predicted through historical information, so that the required instruction cache lines can be prefetched in time, and only the adjacent cache lines that need to be fetched can be prefetched without wasting memory access bandwidth.

According to a processor instruction fetching method provided by the present invention, a pre-fetch address is queried in a cache to obtain a matching result, including:

Using a prefetcher to record addresses of prefetch requests that have been sent;

The pre-fetch address is matched with the address of the sent pre-fetch request. If no match is found, the pre-fetch address is searched in the cache to obtain a matching result.

Specifically, in some embodiments, in the instruction prefetch operation, the prefetch address is queried in the cache to obtain a matching result, which can be implemented by the following process, and the implementation steps include:

It should be noted that, in order to ensure that the prefetch request is not repeatedly sent to the next level storage system, such as L2 Cache, in this embodiment, the prefetcher is used to record the address of the sent prefetch request, that is, the physical address of the sent prefetch request.

Furthermore, when a prefetch request is received, before the prefetch request is sent to the next level storage system, a match is first performed in the address of the prefetch request that has been sent. If no match is found, the prefetch address is queried in the cache to obtain a matching result. In other words, any prefetch request will check the record of the address of the prefetch request that has been sent before applying for a cross-cache line prefetch item. If it is found that the cache line address is the same as the prefetch request that has been sent, the current prefetch request will be canceled. In this way, the required instruction cache line can be prefetched in time, and the memory access bandwidth can be saved by prefetching only the adjacent cache lines that need to be fetched.

The method provided in this embodiment uses a prefetcher to record the address of the prefetch request that has been sent. When receiving the prefetch request, the prefetch address is first matched with the address of the prefetch request that has been sent. If no match is found, the prefetch address is queried in the cache. The advantage of this is that it can ensure that the prefetch request is not repeatedly sent to the next level storage system such as L2 Cache, saving the power consumption of the processor. The processor instruction fetching device provided by the present invention is described below. The processor instruction fetching device described below and the processor instruction fetching method described above can be referred to each other.

FIG6 is a schematic diagram of the structure of a processor instruction fetching device provided by the present invention, which is applied to a processor in an electronic device, wherein the electronic device includes the processor and a memory, wherein the memory includes a cache memory; as shown in FIG6 , the processor instruction fetching device 600 includes the following modules.

The receiving module 610 is used to receive an instruction fetch request; the instruction block of the instruction fetch request includes ordinary instructions and compressed instructions;

The instruction fetch module 620 is used to determine the effective result of the instruction fetch request according to the instruction fetch request; the effective result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

The device provided in this embodiment is applied to a processor in an electronic device, the electronic device includes a processor and a memory, the memory includes a cache, and the device includes: a receiving module 610, used to receive an instruction fetch request, wherein the instruction block of the instruction fetch request includes ordinary instructions and compressed instructions; then, an instruction fetch module 620, used to determine the valid result of the instruction fetch request according to the instruction fetch request, wherein the valid result is used to characterize whether the instruction fetch request needs to fetch instructions across rows from the cache, the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies; then, when the valid result is valid, the target instruction is fetched from the two consecutive cache lines where the instruction block is located according to the instruction fetch request, and the instruction block is determined based on the instruction fetch address in the instruction fetch request; on the contrary, when the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

The cache in the present invention includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-body storage bodies, and the effective result of the instruction fetch request is determined according to the instruction fetch request, that is, whether it is necessary to fetch instructions across lines from the cache. When it is necessary to fetch instructions across lines, the target instruction is fetched from two consecutive cache lines where the instruction block is located according to the instruction fetch request, which can achieve the goal of simultaneously fetching cross-line instructions across cache lines, thereby improving processor performance.

According to a processor instruction fetching device 600 provided by the present invention, the instruction fetching module 620 is specifically used for:

Determine the identification bit of the instruction block according to the instruction fetch address; the identification bit is used to mark whether the instruction block contains a cross-line instruction, and the cross-line instruction is that all bytes of the cross-line instruction fall in two different cache lines;

A valid result of the instruction fetch request is determined according to the identification bit of the instruction block.

According to a processor instruction fetching device 600 provided by the present invention, the value of the flag bit includes 1 or 0, and the instruction fetching module 620 is further used for:

When the value of the flag bit is 1, the valid result is determined to be valid;

When the value of the flag bit is 0, the valid result is determined to be invalid.

According to a processor instruction fetching device 600 provided by the present invention, the instruction fetching request includes the instruction fetching address, the instruction fetching address is the access address of the target cache line corresponding to the instruction fetching request, the instruction fetching address includes a tag, an index, and a block offset, the tag is used to perform a multi-way tag comparison with the cache line in the cache, the index is used to indicate the row number of the cache line corresponding to the instruction fetching request, the index includes a high-order index and a low-order index, the high-order index is used to indicate the row address of the cache line, the low-order index is used to indicate the address of the storage body, and the block offset (Block Offset) is used to indicate the specific position of the instruction block of the instruction fetching request in the cache line;

The instruction fetch module 620 is further used for:

Determining a way corresponding to the instruction fetch request according to a tag in the instruction fetch address;

Determine the cache line and the corresponding storage body corresponding to the instruction fetch request according to the index in the instruction fetch address and the corresponding way; wherein each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line, the tag storage body is used to store tag information of each cache line, and the data storage body is used to store instructions in each cache line;

The target instruction is fetched according to the cache line corresponding to the instruction fetch request, the corresponding storage bank, and the offset within the block.

According to a processor instruction fetching device 600 provided by the present invention, the device further comprises an instruction prefetching module;

The pre-fetch instruction module is used for:

receiving an instruction prefetch request, wherein the instruction prefetch request includes a prefetch address of the prefetch request;

Searching the pre-fetched address in the cache to obtain a matching result;

When the matching result is no match, an instruction prefetch operation is performed.

According to a processor instruction fetching device 600 provided by the present invention, the memory further includes a next-level storage system; the pre-fetch instruction module is specifically used for:

Sending an allocation request to a cross-cache line prefetch item by using an instruction prefetcher, wherein the allocation request is used for the cross-cache line prefetch item to apply for allocation of a prefetch item for the prefetch request;

According to the prefetch item, the prefetch request is sent to the next-level storage system; the prefetch request is used for the next-level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line; the instruction access request includes an access request for a single cache line or an access request across cache lines.

According to a processor instruction fetching device 600 provided by the present invention, the pre-fetch instruction module is further used for:

The prefetch flag of the prefetch request is predicted according to the prefetch item; the prefetch flag is used to indicate whether the prefetch request needs to perform a prefetch instruction across cache lines.

According to a processor instruction fetching device 600 provided by the present invention, the pre-fetch instruction module is further used for:

Initially setting the prefetch flag bits of all cache lines corresponding to the prefetch request to 1;

When a first target number of times that no cross-row prefetch instruction occurs in any cache line corresponding to the prefetch request reaches a first number threshold, the prefetch flag bit of the cache line is determined to be 0; the prefetch flag bit of the cache line being 0 indicates that no cross-row prefetch instruction is performed on the cache line;

When a second target number of cross-row prefetch instructions occurs in any cache line corresponding to the prefetch request reaches a second number threshold, the prefetch flag of the cache line is determined to be 1; the prefetch flag of the cache line being 1 indicates that the cache line resumes the cross-row prefetch instruction.

According to a processor instruction fetching device 600 provided by the present invention, the pre-fetch instruction module is further used for:

Using a prefetcher to record addresses of prefetch requests that have been sent;

The pre-fetch address is matched with the address of the sent pre-fetch request. If no match is found, the pre-fetch address is queried in the cache to obtain a matching result.

FIG7 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG7 , the electronic device may include: a processor 710, a communications interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communications interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the processor instruction fetching method, which is applied to a processor in an electronic device, the electronic device includes the processor and the memory, the memory includes a cache; the method includes: receiving an instruction fetching request; the instruction block of the instruction fetching request includes ordinary instructions and compressed instructions;

Determine, according to the instruction fetch request, a valid result of the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the processor instruction fetching method provided by the above methods, applied to a processor in an electronic device, the electronic device includes the processor and a memory, the memory includes a cache; the method includes:

receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions;

Determine, according to the instruction fetch request, a valid result of the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, the computer program being implemented when executed by a processor to execute the processor instruction fetching method provided by the above methods, and being applied to a processor in an electronic device, the electronic device comprising the processor and a memory, the memory comprising a cache; the method comprising:

receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions;

Determine, according to the instruction fetch request, a valid result of the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies;

When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request;

When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request.

The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM/RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (12)

1. A processor instruction fetching method, characterized in that it is applied to a processor in an electronic device, the electronic device comprises the processor and a memory, the memory comprises a cache; the method comprises: receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions; Determine, according to the instruction fetch request, a valid result of the instruction fetch request; the valid result is used to indicate whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies; When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request; When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request. 2. The processor instruction fetching method according to claim 1, wherein determining a valid result of the instruction fetching request according to the instruction fetching request comprises: Determine the identification bit of the instruction block according to the instruction fetch address; the identification bit is used to mark whether the instruction block contains a cross-line instruction, and the cross-line instruction is that all bytes of the cross-line instruction fall in two different cache lines; A valid result of the instruction fetch request is determined according to the identification bit of the instruction block. 3. The processor instruction fetching method according to claim 2, wherein the value of the flag bit includes 1 or 0, and the determining the valid result of the instruction fetching request according to the flag bit of the instruction block includes: When the value of the flag bit is 1, the valid result is determined to be valid; When the value of the flag bit is 0, the valid result is determined to be invalid. 4. The processor instruction fetching method according to claim 1, characterized in that the instruction fetch request includes the instruction fetch address, the instruction fetch address is the access address of the target cache line corresponding to the instruction fetch request, the instruction fetch address includes a tag, an index, and an offset within a block, the tag is used to perform a multi-way tag comparison with the cache line in the cache, the index is used to indicate the row number of the cache line corresponding to the instruction fetch request, the index includes a high-order index and a low-order index, the high-order index is used to indicate the row address of the cache line, the low-order index is used to indicate the address of a storage body, and the offset within the block is used to indicate the specific position of the instruction block of the instruction fetch request in the cache line; The fetching of the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request comprises: Determining a way corresponding to the instruction fetch request according to a tag in the instruction fetch address; Determine the cache line and the corresponding storage body corresponding to the instruction fetch request according to the index in the instruction fetch address and the corresponding way; wherein each cache line corresponds to a tag storage body of the cache line and a data storage body of the cache line, the tag storage body is used to store tag information of each cache line, and the data storage body is used to store instructions in each cache line; The target instruction is fetched according to the cache line corresponding to the instruction fetch request, the corresponding storage bank, and the offset within the block. 5. The processor instruction fetching method according to any one of claims 1 to 4, characterized in that before receiving the instruction fetching request, it also includes: receiving an instruction prefetch request, wherein the instruction prefetch request includes a prefetch address of the prefetch request; Searching the pre-fetched address in the cache to obtain a matching result; When the matching result is no match, an instruction prefetch operation is performed. 6. The processor instruction fetching method according to claim 5, wherein the memory further comprises a next-level storage system; and the instruction prefetching operation comprises: Sending an allocation request to a cross-cache line prefetch item by using an instruction prefetcher, wherein the allocation request is used for the cross-cache line prefetch item to apply for allocation of a prefetch item for the prefetch request; According to the prefetch item, the prefetch request is sent to the next-level storage system; the prefetch request is used for the next-level storage system to predict the instruction access request based on the prefetch request and the historical flag of the cache line; the instruction access request includes an access request for a single cache line or an access request across cache lines. 7. The processor instruction fetching method according to claim 6, wherein sending the prefetch request to the next-level storage system according to the prefetch item comprises: The prefetch flag of the prefetch request is predicted according to the prefetch item; the prefetch flag is used to indicate whether the prefetch request needs to perform a prefetch instruction across cache lines. 8. The processor instruction fetching method according to claim 7, wherein predicting the prefetch flag of the prefetch request according to the prefetch item comprises: Initially setting the prefetch flag bits of all cache lines corresponding to the prefetch request to 1; When a first target number of times that no cross-row prefetch instruction occurs in any cache line corresponding to the prefetch request reaches a first number threshold, the prefetch flag bit of the cache line is determined to be 0; the prefetch flag bit of the cache line being 0 indicates that no cross-row prefetch instruction is performed on the cache line; When a second target number of cross-row prefetch instructions occurs in any cache line corresponding to the prefetch request reaches a second number threshold, the prefetch flag of the cache line is determined to be 1; the prefetch flag of the cache line being 1 indicates that the cache line resumes the cross-row prefetch instruction. 9. The processor instruction fetching method according to claim 5, wherein the step of querying the pre-fetched address in the cache to obtain a matching result comprises: Using a prefetcher to record addresses of prefetch requests that have been sent; The pre-fetch address is matched with the address of the sent pre-fetch request. If no match is found, the pre-fetch address is queried in the cache to obtain a matching result. 10. A processor instruction fetching device, characterized in that it is applied to a processor in an electronic device, the electronic device comprises the processor and a memory, the memory comprises a cache; the device comprises: A receiving module, used for receiving an instruction fetch request; the instruction block of the instruction fetch request includes common instructions and compressed instructions; an instruction fetch module, for determining a valid result of the instruction fetch request according to the instruction fetch request; the valid result is used to characterize whether the instruction fetch request needs to fetch instructions across rows from the cache; the cache includes an odd-body storage body and an even-body storage body, so that the addresses of two consecutive cache lines in the cache are located on two different odd-even-body storage bodies; When the valid result is valid, fetching the target instruction from two consecutive cache lines where the instruction block is located according to the instruction fetch request; the instruction block is determined based on the instruction fetch address in the instruction fetch request; When the valid result is invalid, the target instruction is fetched from the cache line where the instruction block is located according to the instruction fetch request. 11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the processor instruction fetching method as claimed in any one of claims 1 to 9 when executing the computer program. 12. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor instruction fetching method according to any one of claims 1 to 9 is implemented.