CN118783932A - Double-tailed dynamic comparator - Google Patents

Abstract

The present disclosure relates to a dual tail dynamic comparator comprising an input stage and a latch stage. Wherein the input stage comprises a PMOS input stage and an NMOS input stage connected in parallel, each having a separate voltage rail, the PMOS input stage and the NMOS input stage being adapted to receive the same differential input signal and to output a first amplified signal and a second amplified signal, respectively. The latch stage is electrically connected with the PMOS input stage and the NMOS input stage and is used for receiving the first amplified signal and the second amplified signal for latching, keeping the latch state and outputting the comparison result. According to the double-tail dynamic comparator, the combined structure of the PMOS input stage and the NMOS input stage is arranged in the comparator so as to widen the common-mode input range of the comparator, and the rail-to-rail signal input is supported, so that the double-tail dynamic comparator has the advantages of being simple in structure, convenient to produce and manufacture and wider in application scene.

Description

Double-tailed dynamic comparator

Technical Field

The present disclosure relates to the technical field of integrated circuits, and in particular to a double-tail dynamic comparator.

Background Art

In recent years, with the development of 5G technology and the advent of the Internet of Things era, the scale of data has begun to expand rapidly, and people's demand for high-speed communication systems has become increasingly higher. Comparators are the most basic and indispensable modules for most analog-to-digital converters and other analog and digital interface circuits. The topological structures of comparators are divided into several categories, such as static latch comparators, class AB latch comparators, and dynamic comparators. Among these topological structures, dynamic comparators have fast operation speeds and low power consumption compared to static circuits. As an important component of most mixed-signal circuit applications today, dynamic comparators are widely used in high-speed communication systems, especially in analog-to-digital converters (ADCs), high-speed data transmission (serializers/deserializers, SerDes, SERializers/DESerializers) and other circuits.

At present, the mainstream dynamic comparator is implemented as a dual-tail dynamic comparator, which was proposed by D. Schinkel et al. in 2007. Compared with the traditional dynamic comparator, the dual-tail dynamic comparator alleviates the problem that the conventional comparator is difficult to operate at low voltage by separating the preamplifier from the latch. This structure allows a larger input common mode range to be achieved (for example, the minimum value of the input common mode range of the PMOS input differential pair is closer to 0). In addition, by providing separate dual tail tubes, one for the preamplifier and one for the latch, independent control is provided for the common mode current of the preamplifier and the regeneration time of the latch stage. The output node of the preamplifier in the dual-tail dynamic comparator can be fully charged to the power supply voltage Vdd at the end of the comparison.

However, in some widely used application scenarios (such as Advanced Package), the input signal of the receiving end RX is directly input to the comparator, and its common mode voltage Vcm can reach (where Vdd represents the power supply voltage), which puts forward higher requirements on the range of input common-mode voltage supported by the comparator. When the receiving end of the comparator is a PMOS tube, high common-mode voltage input will reduce the gate-source voltage difference |Vgs| and reduce the gain of the input tube; when Vcm is higher, it will cause the gate-source voltage difference |Vgs| of the PMOS tube to be less than its cut-off threshold voltage |Vthp|, causing the input tube to be turned off and the comparator to fail to work properly. When the receiving end of the comparator is an NMOS tube, low common-mode voltage input will reduce Vgs and reduce the gain of the input tube; when Vcm is lower, it will cause the gate-source voltage difference Vgs of the NMOS tube to be less than its cut-off threshold voltage Vthn, causing the input tube to be turned off and the comparator to fail to work properly. Therefore, it is necessary to propose a comparator that can support a wider common-mode voltage input range.

Summary of the invention

In order to solve at least part of the aforementioned technical problems, the present disclosure proposes a novel dual-tail dynamic comparator, which is based on the characteristics that NMOS tubes work at high common-mode levels and PMOS tubes work at low common-mode levels, and sets a combined structure of PMOS input stages and NMOS input stages in the comparator to broaden the common-mode input range of the comparator. The novel dual-tail dynamic comparator supports rail-to-rail signal input, has the advantages of simple structure, easy production and manufacturing, and wider application scenarios.

According to one embodiment of the present disclosure, a double-tail dynamic comparator is provided, comprising: an input stage, comprising a PMOS input stage and an NMOS input stage connected in parallel, each having a separate voltage rail, the PMOS input stage and the NMOS input stage being used to receive the same differential input signal and output a first amplified signal and a second amplified signal, respectively; a latch stage, electrically connected to the PMOS input stage and the NMOS input stage, and being used to receive the first amplified signal and the second amplified signal for latching, maintaining a latched state and outputting a comparison result.

In one implementation of this embodiment, the PMOS input stage supports a first common mode voltage range, the NMOS input stage supports a second common mode voltage range, and the first common mode voltage range and the second common mode voltage range have an overlapping range.

In one implementation of this embodiment, the output end of the PMOS input stage is connected to the gate of the input tube of the latch stage, and the output end of the NMOS input stage is connected to the drain of the input tube of the latch stage.

In one implementation of the present embodiment, the PMOS input stage includes a first tail current source, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the gates of the first PMOS tube and the second PMOS tube are used to receive the differential input signal, the sources of the first PMOS tube and the second PMOS tube are connected to the first tail current source, the drains of the first PMOS tube and the second PMOS tube are respectively connected to the drains of the first NMOS tube and the second NMOS tube, the sources of the first NMOS tube and the second NMOS tube are grounded, and the gates of the first NMOS tube and the second NMOS tube receive the first clock signal.

In one implementation of the present embodiment, the NMOS input stage includes a second tail current source, a third NMOS tube, a fourth NMOS tube, a third PMOS tube and a fourth PMOS tube, wherein the gates of the third NMOS tube and the fourth NMOS tube are used to receive the differential input signal, the sources of the third NMOS tube and the fourth NMOS tube are connected to the second tail current source, the drains of the third NMOS tube and the fourth NMOS tube are respectively connected to the drains of the third PMOS tube and the fourth PMOS tube, the sources of the third PMOS tube and the fourth PMOS tube are connected to the power supply voltage, and the gates of the third PMOS tube and the fourth PMOS tube receive a second clock signal, and the second clock signal is inverted with the first clock signal.

In one implementation of the present embodiment, the first tail current source is a PMOS tube, whose source is connected to the power supply voltage, whose gate receives the first clock signal, and whose drain is connected to the sources of the first PMOS tube and the second PMOS tube; the second tail current source is an NMOS tube, whose source is grounded, whose gate receives the second clock signal, and whose drain is connected to the sources of the third NMOS tube and the fourth NMOS tube.

In one implementation of the present embodiment, the latch stage includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the gate of the fifth PMOS tube is connected to the drain of the sixth NMOS tube and the sixth PMOS tube, the source of the fifth PMOS tube is connected to the power supply voltage, the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube, the gate of the sixth PMOS tube and the gate of the sixth NMOS tube, and the source of the sixth PMOS tube is connected to the power supply voltage.

In one implementation of the present embodiment, the latch stage also includes a seventh NMOS tube and an eighth NMOS tube, the gates of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the drains of the first PMOS tube and the second PMOS tube, the sources of the seventh NMOS tube and the eighth NMOS tube are grounded, and the drains of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the sources of the fifth NMOS tube and the sixth NMOS tube.

In one implementation of this embodiment, the sources of the fifth NMOS tube and the sixth NMOS tube are connected to the drains of the third NMOS tube and the fourth NMOS tube respectively.

In one implementation of the present embodiment, the comparator further includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and a tenth PMOS tube, wherein sources of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the power supply voltage, gates of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the second clock signal, and drains of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are respectively connected to the source of the fifth NMOS tube, the drain of the fifth PMOS tube, the drain of the sixth PMOS tube and the source of the sixth NMOS tube.

Based on the characteristics that NMOS tubes work at high common-mode levels and PMOS tubes work at low common-mode levels, the present invention sets a combined structure of PMOS input stage and NMOS input stage in the comparator to broaden the common-mode input range of the comparator. The new double-tail dynamic comparator supports rail-to-rail signal input, has the advantages of simple structure, easy production and manufacturing, and wider application scenarios.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the present disclosure will be better understood through the following preferred embodiments described in detail in conjunction with the accompanying drawings, in which:

FIG. 1 shows a circuit diagram of an exemplary double-tail dynamic comparator according to an embodiment of the present disclosure.

FIG. 2 shows a circuit diagram of an input stage of an exemplary comparator according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

In the following specific description of the preferred embodiments, reference will be made to the attached drawings that form a part of the present disclosure. The attached drawings show, by way of example, specific embodiments that can implement the present disclosure. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present disclosure. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made without departing from the scope of the present disclosure. Therefore, the following specific description is not restrictive, and the scope of the present disclosure is defined by the attached claims.

As mentioned above, in order to solve the technical problem that the input common-mode voltage range supported by the double-tail dynamic comparator in the prior art is small, resulting in the comparator not being able to work properly in some wider application scenarios (such as Advanced Package), the present disclosure proposes a novel double-tail dynamic comparator.

The novel double-tail dynamic comparator includes an input stage and a latch stage. The input stage includes a PMOS input stage and an NMOS input stage connected in parallel, each having a separate voltage rail, and the PMOS input stage and the NMOS input stage are used to receive the same differential input signal and output a first amplified signal and a second amplified signal respectively. The latch stage is electrically connected to the PMOS input stage and the NMOS input stage, and is used to receive the first amplified signal and the second amplified signal for latching, maintain the latched state, and output a comparison result.

Based on the characteristics of NMOS tube working at high common mode level and PMOS tube working at low common mode level, the novel dual-tail dynamic comparator sets a combination structure of PMOS input stage and NMOS input stage in the comparator to broaden the common mode input range of the comparator. The novel dual-tail dynamic comparator has the advantages of simple structure, easy production and manufacturing, and wider application scenarios.

In some embodiments, the PMOS input stage supports a differential input signal in a first common-mode voltage range, the NMOS input stage supports a differential input signal in a second common-mode voltage range, and the first common-mode voltage range and the second common-mode voltage range overlap. It can be seen that, in comparison, the first common-mode voltage range is a low common-mode voltage range, the second common-mode voltage range is a high common-mode voltage range, and the maximum value in the first common-mode voltage range should be greater than the minimum value in the second common-mode voltage range.

In some embodiments, the output of the PMOS input stage is connected to the gate of the input tube of the latch stage, and the output of the NMOS input stage is connected to the drain of the input tube of the latch stage. This connection method is an effective method for applying the combination of the PMOS input stage and the NMOS input stage to the double-tail dynamic comparator to widen the common mode voltage range.

1 , an embodiment of the present invention provides a circuit diagram of a dual-tail dynamic comparator. The comparator includes a PMOS input stage, which includes a first tail current source M1, a first PMOS tube M2, a second PMOS tube M3, a first NMOS tube M4, and a second NMOS tube M5, wherein the gates of the first PMOS tube and the second PMOS tube are used to receive a differential input signal (Vinp, Vinn), the sources of the first PMOS tube and the second PMOS tube are connected to the first tail current source, the drains of the first PMOS tube and the second PMOS tube are respectively connected to the drains of the first NMOS tube and the second NMOS tube, the sources of the first NMOS tube and the second NMOS tube are grounded (Vssa), and the gates of the first NMOS tube and the second NMOS tube receive a first clock signal (clkb).

The comparator also includes an NMOS input stage. The NMOS input stage includes a second tail current source M10, a third NMOS tube M8, a fourth NMOS tube M9, a third PMOS tube M6 and a fourth PMOS tube M7, wherein the gates of the third NMOS tube and the fourth NMOS tube are used to receive differential input signals (Vinp, Vinn), the sources of the third NMOS tube and the fourth NMOS tube are connected to the second tail current source, the drains of the third NMOS tube and the fourth NMOS tube are respectively connected to the drains of the third PMOS tube and the fourth PMOS tube, the sources of the third PMOS tube and the fourth PMOS tube are connected to the power supply voltage (Vdda), and the gates of the third PMOS tube and the fourth PMOS tube receive a second clock signal (clk), and the second clock signal (clk) is inverted with the first clock signal (clkb).

In some embodiments, the first tail current source is a PMOS tube, whose source is connected to the power supply voltage, whose gate receives the first clock signal, and whose drain is connected to the sources of the first PMOS tube and the second PMOS tube; the second tail current source is an NMOS tube, whose source is grounded, whose gate receives the second clock signal, and whose drain is connected to the sources of the third NMOS tube and the fourth NMOS tube.

The comparator also includes a latch stage. The latch stage includes a fifth PMOS tube M13, a sixth PMOS tube M14, a fifth NMOS tube M17 and a sixth NMOS tube M18, wherein the gate of the fifth PMOS tube is connected to the drain of the sixth NMOS tube and the sixth PMOS tube, the source of the fifth PMOS tube is connected to the power supply voltage, the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube, the gate of the sixth PMOS tube and the gate of the sixth NMOS tube, and the source of the sixth PMOS tube is connected to the power supply voltage.

In some embodiments, the latch stage further includes a seventh NMOS tube M19 and an eighth NMOS tube M20, the gates of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the drains of the first PMOS tube and the second PMOS tube, the sources of the seventh NMOS tube and the eighth NMOS tube are grounded, and the drains of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the sources of the fifth NMOS tube and the sixth NMOS tube. In some embodiments, the sources of the fifth NMOS tube and the sixth NMOS tube are respectively connected to the drains of the third NMOS tube and the fourth NMOS tube.

In some embodiments, the comparator further includes a seventh PMOS tube M11, an eighth PMOS tube M12, a ninth PMOS tube M15 and a tenth PMOS tube M16, wherein the sources of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the power supply voltage Vdda, the gates of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected to the second clock signal (clk), and the drains of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are respectively connected to the source of the fifth NMOS tube, the drain of the fifth PMOS tube, the drain of the sixth PMOS tube and the source of the sixth NMOS tube.

In some embodiments, the output of the NMOS input stage of the comparator is connected to the input of the latch stage by a transmission gate control, that is, the drains of the third NMOS tube M8 and the fourth NMOS tube M9 are connected to the sources of the fifth NMOS tube M17 and the sixth NMOS tube M18 through the transmission gate, respectively. The transmission gate is controlled by a clock signal, disconnected in the reset phase of the comparator, and turned on in the comparison phase (i.e., sampling phase, regeneration phase, and judgment phase) of the comparator. In other embodiments, the transmission gate can be replaced by other types of switch elements.

The comparator shown in FIG1 broadens the common-mode input range of the input signal and realizes rail-to-rail signal input by adding an NMOS input stage of opposite polarity on the basis of a conventional double-tail dynamic comparator with a PMOS input stage. It is worth mentioning that the present disclosure is not limited to conventional double-tail dynamic comparators with a PMOS input stage, but is also applicable to other types of double-tail dynamic comparators. For example, a PMOS input stage of opposite polarity can be added on the basis of a double-tail dynamic comparator with an NMOS input stage to broaden the common-mode input range of the input signal. The working principle of the comparator shown in FIG1 can be described as follows.

Reset Phase

The second clock signal clk is at a low level, the first clock signal clkb is at a high level, and the transmission gate is disconnected. For the PMOS input stage, the first tail current source M1 is disconnected, the first NMOS tube M4 and the second NMOS tube M5 are turned on, the output nodes o1p and o1m are discharged to 0, and the input tubes M19 and M20 of the latch stage remain closed. For the NMOS input stage, the second tail current source M10 is disconnected, the third PMOS tube M6 and the fourth PMOS tube M7 are turned on, and the output nodes o2p and o2m are charged to Vdda. At the same time, the enable tubes of the latch stage (the seventh PMOS tube M11, the eighth PMOS tube M12, the ninth PMOS tube M15 and the tenth PMOS tube M16) are all turned on, so that the output nodes Voutp and Voutn of the latch stage remain at a high level, and the intermediate nodes midp and midm remain at a high level.

Sampling stage

When the second clock signal clk turns high, the first clock signal clkb turns low, and the transmission gate is turned on. For the PMOS input stage, M4 and M5 are turned off, the first tail current source M1 is turned on, and the output nodes o1p and o1m start to charge at different rates, and the charging rate depends on the voltage difference between the two input nodes Vinp and Vinn. When the voltages Vo1p and Vo1m of the o1p/o1m nodes are charged to the threshold voltage Vthn of M19/M20, M19/M20 is turned on, and the midp/midm nodes start to discharge from Vdda at different rates. At this time, the gain of the PMOS input stage can be expressed as follows:

in, is the transconductance of the PMOS input tube, is the capacitance at point o1p/o1m.

The duration of this phase is defined as , is the time required for o1p/o1m to charge to the threshold voltage of M19/M20, which can be expressed as follows:

Wherein, Vthn represents the threshold voltage of M19/M20, represents the output current of the first tail current source M1 in the PMOS input stage.

For the NMOS input stage, M6 and M7 are turned off, the second tail current source M10 is turned on, and the output nodes o2p and o2m begin to discharge from Vdda at different rates. The discharge rate depends on the voltage difference between the two input nodes Vinp and Vinn. At this time, the gain of the NMOS input stage can be expressed as follows:

in, is the NMOS input tube transconductance, is the capacitance of the output node o2p/o2m.

At this time, the transmission gate is turned on, and the intermediate nodes midp/midm add a discharge path M8~M10, corresponding to o2m/o2p. The maintenance time of this stage is defined as , is the time required for o2p/o2m to discharge from Vdda to reduce a threshold voltage, which can be expressed as follows:

in, represents the output current of the second tail current source M10 in the NMOS input stage.

As the intermediate nodes midp/midm are discharged, when the voltages of the output nodes Voutp and Voutn of the latch drop to a level that is insufficient to maintain at Vdda, the latch enters a regeneration phase.

Regeneration and judgment stage

The output nodes Voutp and Voutn of the latch are charged at different rates, and the charging rate depends on the voltage difference between the two nodes midp and midm. The output voltage change curve of the comparator regeneration phase is exponential. Because of the positive feedback of the latch, the node with fast discharge will be quickly discharged to 0 level, on the contrary, the node with slow discharge will be pulled back to Vdda level. When |Voutp-Voutn|> When , the circuit is considered to have completed the regeneration phase. The time required for the regeneration phase is expressed as follows:

in, is the output node capacitance, is the equivalent transconductance, It is the voltage difference of the output node when M17 or M18 is turned on.

The positive feedback continues until the decision phase is completed. After the decision phase is completed, the circuit will wait for the clock signal clk to become a low level and re-enter the reset phase.

The common-mode voltage Vcm range of the differential input signal supported by the comparator shown in Figure 1 can be divided into three sections: (0, Vthn), (Vthn, Vdda-Vthp) and (Vdda-Vthp, Vdda). When 0<Vcm<Vthn, the PMOS input stage mainly works, and the NMOS input stage does not work; when Vthn<Vcm<(Vdda-Vthp), the PMOS input stage and the NMOS input stage work at the same time; when Vdda>Vcm>(Vdda-Vthp), the NMOS input stage mainly works, and the PMOS input stage does not work.

The present disclosure takes FIG. 1 as an example to explain in detail the implementation method of setting a combined structure of a PMOS input stage and an NMOS input stage in a comparator to broaden the common-mode input range of the comparator. However, it should be noted that FIG. 1 is only an exemplary description of the present disclosure, and the present disclosure is not limited to the circuit structure shown in FIG. 1.

As shown in FIG. 2 , another embodiment of the present disclosure proposes a circuit diagram of an input stage of another comparator, which can constitute a new comparator together with the latch stage shown in FIG. 1 , or can be combined with other types of latches to constitute a new comparator capable of rail-to-rail signal input.

The comparator shown in FIG2 includes a PMOS input stage and an NMOS input stage. The PMOS input stage includes a ninth NMOS tube M21, a tenth NMOS tube M22, and an eleventh NMOS tube M23, and also includes an eleventh PMOS tube M24, a twelfth PMOS tube M25, a thirteenth PMOS tube M26, and a fourteenth PMOS tube M27. The NMOS input stage includes a fifteenth PMOS tube M28, a sixteenth PMOS tube M29, and a seventeenth PMOS tube M30, and also includes a twelfth NMOS tube M31, a thirteenth NMOS tube M32, a fourteenth NMOS tube M33, and a fifteenth NMOS tube M34. Among them, the PMOS input stage and the NMOS input stage are connected in parallel.

The circuit structure of the PMOS input stage is as follows: the sources of M26 and M27 are connected to the power supply voltage Vdda (high level), the gates of M26 and M27 are grounded Vssa (low level), the drain of M26 is connected to the source of M24, the drain of M27 is connected to the source of M25, the gates of M24 and M25 are connected to the differential input signals (Vinp and Vinn), the drains of M24 and M25 are respectively connected to the drains of M22 and M23 and are the output nodes o1p and o1m respectively, the gates of M22 and M23 are respectively connected to the gates of M24 and M25, the sources of M22 and M23 are connected to the drain of M21, the source of M21 is grounded Vssa (low level), and the gate of M21 is connected to the clock signal clkb.

The circuit structure of the NMOS input stage is as follows: the source of M28 is connected to the power supply voltage Vdda, the gate of M28 is connected to the clock signal clk, and the drain of M28 is connected to the sources of M29 and M30; the drains of M29 and M30 are respectively connected to the drains of M31 and M32 and serve as output nodes o2p and o2m respectively, the gates of M29 and M30 are respectively connected to the gates of M31 and M32 and are respectively connected to the differential input signals (Vinp and Vinn); the sources of M31 and M32 are respectively connected to the drains of M33 and M34; the gates of M33 and M34 are respectively connected to the power supply voltage Vdda, and the sources of M33 and M34 are grounded Vssa.

The working principle of the circuit shown in FIG2 can be described as follows: For the PMOS input stage, the gates of M26 and M27 are connected to the low level Vssa and are in a long-on state. When clkb is at a high level, M21 is turned on, the circuit is in a comparison stage, the input signals Vinp and Vinn begin to charge at different rates, and the output voltages of the output nodes o1p and o1m also change at different rates and are transmitted to the latch stage. When clkb is at a low level, M21 is disconnected, and the circuit is in a reset stage. For the NMOS input stage, the gates of M33 and M34 are connected to the high level Vdda and are in a long-on state. When clk is at a low level, M28 is turned on, the circuit is in a comparison stage, the input signals Vinp and Vinn begin to charge at different rates, and the output voltages of the output nodes o2p and o2m also change at different rates and are transmitted to the latch stage; when clk is at a high level, M28 is disconnected, and the circuit is in a reset stage. The clock signal clkb is an inverted clock signal of the clock signal clk.

This article is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this article. Although the principles of this article have been shown in various embodiments, many modifications of structures, arrangements, proportions, elements, materials and components that are particularly suitable for specific environments and operational requirements can be used without departing from the principles and scope of this disclosure. The above modifications and other changes or modifications will be included in the scope of this article. The foregoing specific description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, consideration of this disclosure will be in an illustrative rather than restrictive sense, and all these modifications will be included in its scope. Similarly, the advantages, other advantages and solutions to the problems of various embodiments have been described above. However, the benefits, advantages, solutions to the problems and any elements that can produce these, or solutions that make them more clear should not be interpreted as critical, necessary or necessary. As used herein, the term "include" and any other variations thereof are non-exclusive inclusions, such that a process, method, article, or device that includes a list of elements includes not only those elements, but also other elements that are not explicitly listed or that are not part of the process, method, system, article, or device. In addition, as used herein, the term "coupled" and any other variations thereof refer to physical, electrical, magnetic, optical, communicative, functional, and/or any other connection.

Those skilled in the art will appreciate that many changes may be made to the details of the above-described embodiments without departing from the basic principles of the present disclosure. Therefore, the scope of the present disclosure should be determined solely by the claims.

Claims (10)

1. A two-tailed dynamic comparator, comprising:

an input stage comprising a PMOS input stage and an NMOS input stage connected in parallel, each having a separate voltage rail, the PMOS input stage and the NMOS input stage for receiving the same differential input signal and outputting a first amplified signal and a second amplified signal, respectively;

A latch stage electrically connected to the PMOS input stage and the NMOS input stage for receiving the first amplified signal and the second amplified signal for latching, maintaining a latch state and outputting a comparison result,

Wherein the PMOS input stage supports a first common-mode voltage range, the NMOS input stage supports a second common-mode voltage range, and the first and second common-mode voltage ranges have overlapping ranges.

2. The two-tailed dynamic comparator of claim 1, wherein an output of the PMOS input stage is connected to a gate of an input tube of the latch stage and an output of the NMOS input stage is connected to a drain of the input tube of the latch stage.

3. The dual-tail dynamic comparator of claim 1, wherein the PMOS input stage comprises a first tail current source, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein gates of the first PMOS tube and the second PMOS tube are used for receiving the differential input signal, sources of the first PMOS tube and the second PMOS tube are connected with the first tail current source, drains of the first PMOS tube and the second PMOS tube are respectively connected with drains of the first NMOS tube and the second NMOS tube, sources of the first NMOS tube and the second NMOS tube are grounded, and gates of the first NMOS tube and the second NMOS tube receive a first clock signal.

4. The dual tail dynamic comparator as claimed in claim 3, wherein the NMOS input stage comprises a second tail current source, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, wherein gates of the third NMOS transistor and the fourth NMOS transistor are configured to receive the differential input signal, sources of the third NMOS transistor and the fourth NMOS transistor are connected to the second tail current source, drains of the third NMOS transistor and the fourth NMOS transistor are respectively connected to drains of the third PMOS transistor and the fourth PMOS transistor, sources of the third PMOS transistor and the fourth PMOS transistor are connected to a power supply voltage, gates of the third PMOS transistor and the fourth PMOS transistor receive a second clock signal, and the second clock signal is inverted from the first clock signal.

5. The dual tail dynamic comparator of claim 4, wherein the first tail current source is a PMOS transistor having a source connected to a supply voltage, a gate receiving the first clock signal, and a drain connected to sources of the first PMOS transistor and the second PMOS transistor; the second tail current source is an NMOS tube, the source electrode of the second tail current source is grounded, the grid electrode of the second tail current source receives the second clock signal, and the drain electrode of the second tail current source is connected with the source electrodes of the third NMOS tube and the fourth NMOS tube.

6. The dual tail dynamic comparator of claim 4, wherein the latch stage comprises a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, wherein a gate of the fifth PMOS transistor is connected to the sixth NMOS transistor and a drain of the sixth PMOS transistor, a source of the fifth PMOS transistor is connected to a supply voltage, and a drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, a gate of the sixth PMOS transistor, and a gate of the sixth NMOS transistor, and a source of the sixth PMOS transistor is connected to the supply voltage.

7. The dual-tail dynamic comparator of claim 6, wherein the latch stage further comprises a seventh NMOS transistor and an eighth NMOS transistor, gates of the seventh NMOS transistor and the eighth NMOS transistor are respectively connected to drains of the first PMOS transistor and the second PMOS transistor, sources of the seventh NMOS transistor and the eighth NMOS transistor are grounded, and drains of the seventh NMOS transistor and the eighth NMOS transistor are respectively connected to sources of the fifth NMOS transistor and the sixth NMOS transistor; and the sources of the fifth NMOS tube and the sixth NMOS tube are respectively connected with the drains of the third NMOS tube and the fourth NMOS tube.

8. The dual-tail dynamic comparator according to claim 7, further comprising a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and a tenth PMOS tube, wherein sources of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected with a power supply voltage, gates of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are connected with the second clock signal, and drains of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are respectively connected with sources of the fifth NMOS tube, drains of the fifth PMOS tube, drains of the sixth PMOS tube and sources of the sixth NMOS tube.

9. The dual tail dynamic comparator of claim 1, wherein the PMOS input stage comprises a ninth NMOS transistor, a tenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor; the source electrodes of the thirteenth PMOS tube and the fourteenth PMOS tube are connected with power supply voltage, the grid electrodes of the thirteenth PMOS tube and the fourteenth PMOS tube are grounded, the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the drain electrode of the fourteenth PMOS tube is connected with the source electrode of the twelfth PMOS tube, the grid electrodes of the eleventh PMOS tube and the twelfth PMOS tube are connected with differential input signals, the drain electrodes of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected with the drain electrodes of the tenth NMOS tube and the eleventh NMOS tube, the grid electrodes of the tenth NMOS tube and the eleventh NMOS tube are respectively connected with the grid electrodes of the eleventh PMOS tube and the twelfth NMOS tube, the source electrode of the ninth NMOS tube is grounded, and the grid electrode of the ninth NMOS tube is connected with the first clock signal.

10. The dual tail dynamic comparator of claim 9, wherein the NMOS input stage comprises a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor; the source electrode of the fifteenth PMOS tube is connected with a power supply voltage, the grid electrode of the fifteenth PMOS tube is connected with a second clock signal, the drain electrodes of the fifteenth PMOS tube are connected with the source electrodes of the sixteenth PMOS tube and the seventeenth PMOS tube, the drain electrodes of the sixteenth PMOS tube and the seventeenth PMOS tube are respectively connected with the drain electrodes of the twelfth NMOS tube and the thirteenth NMOS tube, the grid electrodes of the sixteenth PMOS tube and the seventeenth PMOS tube are respectively connected with the grid electrodes of the twelfth NMOS tube and the thirteenth NMOS tube and are respectively connected with differential input signals, the source electrodes of the twelfth NMOS tube and the thirteenth NMOS tube are respectively connected with the drain electrodes of the fourteenth NMOS tube and the fifteenth NMOS tube, the grid electrodes of the fourteenth NMOS tube and the fifteenth NMOS tube are respectively connected with the power supply voltage, and the source electrodes of the fourteenth NMOS tube and the fifteenth NMOS tube are grounded.