CN118782679A - A method for passivation of the back side of a photodetector without openings - Google Patents

Abstract

The invention relates to a passivation method for a photoelectric detector without an opening on the whole back surface, belonging to the technical field of optoelectronic devices. The method takes intrinsic silicon as a processing object, and uses ion implantation to prepare a P-type region and an N-type region at two ends of the intrinsic silicon to form a PIN structure, a full back passivation tunneling functional layer is deposited on an N-type doping surface of the PIN structure, and the material of the full back passivation tunneling functional layer is oxide or nitride; and depositing N-type polycrystalline silicon on the full-back passivation tunneling functional layer, and annealing under the protective atmosphere condition, wherein the N-type polycrystalline silicon and the full-back passivation tunneling functional layer form the non-open-pore back passivation layer together. The method not only provides a back passivation technology without opening holes, effectively reduces dark current of the device, but also forms heterojunction on the back to promote multi-photon transmission, and improves the performance of the PIN photoelectric detector.

Description

A method for passivation of the back side of a photodetector without openings

Technical Field

The present invention relates to the technical field of optoelectronic devices, and more specifically, to a full back-side non-opening passivation method for a photoelectric detector.

Background Art

Photodetectors are one of the important devices in optoelectronic devices and are widely used in various fields. In the visible light or near-infrared band, they are mainly used for ray measurement and detection, industrial automatic control, photometry, etc.; in the infrared band, they are mainly used for missile guidance, infrared thermal imaging, infrared remote sensing, etc. In addition, photodetectors also play an important role in the fields of communication and networking. In optical fiber communication systems, photodetectors are used to detect transmitted optical signals and convert them into electrical signals to achieve data transmission and control. Because photodetectors have fast response and low noise performance, they are ideal for high-speed optical fiber communication systems. Among them, PIN photodetectors are a typical structure of photodetectors. Compared with traditional PN junctions, the additional intrinsic layer can provide an internal electric field, accelerate and increase the movement speed of carriers, and make the device respond to light more quickly. At the same time, the I layer of the PIN photodetector can also absorb photons and generate more electron-hole pairs, thereby improving the light conversion efficiency of the detector. Therefore, silicon-based PIN photodetectors have become the most widely used detectors in the field of optoelectronics due to their high sensitivity, high response speed, low noise and stable performance.

For photodetectors, the device's photoresponse and dark current have always been the main indicators for measuring device performance. As the main noise of the device, dark current will affect or even cover the photocurrent if it is too large, seriously affecting device performance. Therefore, how to reduce dark current is an eternal topic in the field of photodetector research. The main sources of dark current are the device's body dark current and surface dark current. Among them, the surface dark current is generated by the recombination of carriers on the device surface. Therefore, optimizing the surface structure of the device and reducing the recombination current are of great research significance.

For most photodetectors, the surface treatment is limited to the photosensitive surface, such as adding a passivation film and an anti-reflection film or using a light trapping structure. However, there is relatively little research on the back side of the photodetector. Therefore, it is of great significance to study the passivation method of the back side of the device.

Summary of the invention

The present invention solves the technical problems of excessive dark current and weak light response of photodetectors in the prior art. The present invention provides a method for back passivation of photodetectors. By preparing a non-opening back passivation layer formed by N-type polysilicon and a full back passivation tunneling functional layer on the back of the device, the interface is passivated while promoting the transmission of multi-carriers, reducing the dark current of the device and improving the light response of the device, thereby improving the efficiency of the device. At the same time, the non-opening method also greatly reduces the cost and time of the process, which is of great significance for optimizing the performance of the device.

According to the purpose of the present invention, a method for full back surface passivation of a photodetector is provided, comprising the following steps:

(1) Using an intrinsic silicon wafer as a substrate, ion implanting B element on one side of the substrate, and performing annealing after the implantation is completed to form a P-type doping; ion implanting P element on the other side of the substrate, and performing annealing after the implantation is completed to form an N-type doping, thereby forming a PIN structure;

(2) depositing a full back passivation tunneling functional layer on the N-type doped surface of the PIN structure obtained in step (1), wherein the material of the full back passivation tunneling functional layer is oxide or nitride;

(3) depositing N-type polysilicon on the full back passivation tunneling functional layer obtained in step (2), and annealing under protective atmosphere conditions, wherein the N-type polysilicon and the full back passivation tunneling functional layer together form a back passivation layer without openings.

Preferably, the oxide is SiO ₂ or Al ₂ O ₃ ; and the nitride is Si ₃ N ₄ .

Preferably, the thickness of the full back-side passivation tunneling functional layer is 0.5 nm to 1.5 nm.

Preferably, the gas source used for injecting the B element is BF ₃ .

Preferably, the gas source used for injecting the P element is PH ₃ .

Preferably, in step (3), the annealing temperature is 700-900° C. and the time is 20-30 min.

Preferably, in step (3), the protective atmosphere is nitrogen or argon.

Preferably, in step (3), the deposition method is low pressure chemical vapor deposition.

Preferably, the thickness of the N-type polysilicon is 50 nm to 150 nm.

Preferably, the intrinsic silicon resistivity is greater than or equal to 5000Ω/cm.

In general, the above technical solution conceived by the present invention has the following technical advantages compared with the prior art:

(1) The method of the present invention can effectively improve the light response and quantum efficiency of the photodetector, reduce surface recombination loss, reduce the dark current of the device, increase the interface passivation effect, and improve the performance of the photodetector.

(2) The method of the present invention can effectively reduce dark current. When the photodetector operates under a bias voltage of -5V, the dark current of the device is reduced by 5% to 10% compared with the device without a surface passivation layer.

(3) The method of the present invention can improve the photocurrent. After adding a full back passivation layer, the photocurrent of the device can be improved by nearly one order of magnitude in the absorption band of the photodetector when the light wavelength is 300nm to 1100nm.

(4) The method of the present invention provides a back-side passivation technology that does not require opening holes on the back side, which can reduce the process flow, reduce the process difficulty, and thus reduce the production cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of the preparation of a PIN photodetector and a back passivation layer without openings.

FIG. 2 is a cross-sectional view of a PIN photodetector and a back passivation layer device without openings.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

The technical method adopted by the present invention is as follows: first, a PIN structure is prepared, and then the structure is used as a processing object, and an atomic layer deposition layer is used to form a full back-side passivation tunneling functional layer (oxide layer or nitride layer). On the functional layer, a layer of N-type polysilicon layer is prepared by low-pressure chemical vapor deposition. The sample treated in this way forms a back-side passivation layer without openings on the back side, the back side is optimized, and the photocurrent of the prepared PIN photodetector is increased, the dark current is reduced, and the performance is significantly improved.

The non-perforated back passivation layer provided by the present invention first prepares a relatively thin tunneling functional layer (oxide layer or nitride layer), and the tunneling functional layer plays a role in full-surface passivation on the back of the device, which can reduce the surface recombination current and reduce the dark current. At the same time, due to the tunneling effect, carriers can pass through the tunneling functional layer and then be collected by the back electrode, achieving the effect of full-surface passivation without opening holes. In addition, after the full back passivation oxide tunneling layer is prepared, the present invention prepares a layer of N-type polycrystalline silicon by low-pressure chemical vapor deposition. P-doping of polycrystalline silicon by N-type polycrystalline silicon can increase the conductivity of polycrystalline silicon, thereby realizing the conduction of the device. At the same time, this layer of polycrystalline silicon forms a heterojunction with the N layer on the back of the PIN detector. Due to the introduction of the heterojunction of N-type polycrystalline silicon, the energy band of N-type silicon will bend downward at the interface, thereby preventing the transmission of holes and promoting the transmission of electrons, achieving the screening effect of carriers. When the photodetector is working, the photogenerated electrons generated in the space charge region pass through the N region, and the photogenerated holes pass through the P region and are absorbed by the electrode to generate the current. Therefore, screening the carriers in the N region can effectively increase the photocurrent of the device, thereby improving the performance of the device. The non-perforated back passivation layer designed by the present invention can reduce the dark current of the device while improving the light response of the device. At the same time, the technical method without perforations can also simplify the process and reduce costs.

Figure 1 is a flow chart of the preparation of a PIN photodetector and a back passivation layer without openings. An embodiment of the present invention provides a back passivation method for a photodetector, comprising the following steps:

S1: Provide an intrinsic silicon wafer, perform P doping on the front side and N doping on the back side to form a PIN structure;

S2: For the above-mentioned PIN structure, a full back passivation tunneling functional layer (oxide layer or nitride layer) is deposited on the back side thereof;

S3: For the above structure, a layer of N-type polysilicon is further deposited on the full back passivation tunneling functional layer, and annealed in a protective atmosphere, which together with the full back passivation silicon dioxide tunneling layer forms a non-opening back passivation layer.

A back passivation method for a photodetector provided in an embodiment of the present invention first provides an intrinsic double-polished silicon wafer, whose resistivity is generally above 5000Ω/cm. On this basis, the intrinsic silicon wafer is used as a substrate, and ion implantation of B element is performed on one side, and the gas source used is BF _3. After the implantation is completed to form P-type doping, ion implantation annealing is performed to repair lattice damage. Ion implantation of P element is performed on the other side, and the gas source used is PH _3. After the implantation is completed to form N-type doping, ion implantation annealing is performed to repair lattice damage to form a PIN structure. After the preparation of the above-mentioned PIN structure is completed, an atomic layer deposition is used to deposit a full back tunneling functional layer on its N-type surface, and a polysilicon layer is prepared on the tunneling functional layer using low-pressure chemical vapor deposition and annealing, thereby realizing the preparation of a back passivation layer without openings on the back of the PIN photodetector. The embodiment of the present invention performs the preparation of a back passivation layer without openings on the prepared PIN photodetector, which can effectively reduce the dark current of the device, improve the light response of the device, and also simplify the process. In addition, in the non-opening back passivation layer prepared by the present invention, the full back passivation functional layer provides the entire surface passivation of the back of the PIN detector, and at the same time allows carriers to pass through through the tunneling effect to form current; while the polysilicon layer can bend the energy band of the N region on the back of the detector, promote the transmission of majority carriers and inhibit the transmission of holes, play a role in screening carriers, thereby increasing the photocurrent. The non-opening back passivation layer prepared by the present invention, while playing the role of back passivation and reducing dark current, simplifies the device process, improves the light response of the device, and optimizes the performance of the device.

Specifically, in the above step S1, the silicon wafer is intrinsic silicon, and the resistivity needs to be greater than 5000Ω/cm. The P-type and N-type doping on both sides needs to be doped to more than 1×10 ¹⁸ cm ^-3 . On the one hand, a longer space charge region will be formed between the highly doped silicon (P-type silicon and N-type silicon on both sides) and the intrinsic silicon, which can ensure that the light absorption of the photodetector occurs in the space charge region. On the other hand, the selected intrinsic silicon wafer thickness should be able to completely cover the formed space charge region, so that the entire detector can absorb light. In addition, after ion implantation, the device needs to be annealed. After the P element is injected, annealing is required at 900°C for 30 minutes, and after the B element is injected, annealing is required at 1000°C for 30 minutes.

In some embodiments, in the above step S2, the thickness of the full back passivation tunneling functional layer (oxide layer or nitride layer) should be 0.5nm to 1.5nm. If the prepared functional layer is too thick, the tunneling effect may be weakened, thereby reducing the current and forming a short circuit. At the same time, if the weakly prepared functional layer is too thin, the passivation effect may be reduced.

In some embodiments, in the above step S3, N-type polysilicon is prepared by low-pressure chemical vapor deposition, and the thickness of the polysilicon is 50nm to 150nm. If the prepared polysilicon is too thick, the dark current of the device will increase, and if the prepared polysilicon is too thin, the effect of the non-opening back passivation layer on the light response of the device will be weakened.

In some embodiments, in the above step S3, low-pressure chemical vapor deposition is used to prepare N-type polysilicon, and the gases introduced are _SiH4 and _PH3 , and N-type polysilicon is directly prepared. After the N-type polysilicon contacts the N-side of the detector, the N-region energy band is bent downward, which plays a role in carrier screening. After the polysilicon is prepared, annealing treatment is required, and the annealing temperature is 700-900°C and the time is 20-30 minutes. By controlling the device annealing temperature and annealing atmosphere, the interface defects are reduced, and the purpose of passivation on the back of the device is achieved, thereby reducing the dark current of the device and improving the performance of the device.

The present invention designs the structure of a PIN photodetector, designs and prepares N-type polysilicon and a full back passivation tunneling functional layer to form a non-opening back passivation layer, so that a tunneling current is generated at the back of the device to achieve the purpose of carrier screening, thereby improving the light response and quantum efficiency of the device.

In some embodiments, the present invention uses an electron beam evaporation process to prepare two-terminal electrodes, and the electrode materials can be selected from Ti/Al/Au. The device structure of the PIN photodetector through back passivation of the present invention is from top to bottom: front electrode, P-type silicon layer, intrinsic silicon layer, N-type silicon layer, full back passivation functional layer, N-type polysilicon layer, back electrode. Figure 2 is a cross-sectional view of a PIN photodetector and a back passivation layer device without openings.

The following are specific embodiments

Example 1

A PIN photodetector and a method for preparing a back passivation layer without an opening, comprising the following steps:

The back of the cleaned weak n-type silicon wafer (resistivity 10000Ω/cm) was coated with glue and placed in the ion implantation tray. B ions were implanted with an implantation energy of 100KeV and an implantation dose of 9×10 ¹⁴ cm ^-3. After debonding, the wafer was annealed in a tubular annealing furnace for 30 minutes at a temperature of 1000°C. After annealing, the implanted side was protected with glue and the other side was ion implanted with an energy of 100KeV and an implantation dose of 1.3×10 ¹⁵ cm ^-3. After debonding, the wafer was annealed in a tubular annealing furnace for 30 minutes at a temperature of 900°C.

The PIN photodetector obtained above is placed on an atomic layer deposition tray, with the N region facing upward, and 1.5 nm of silicon dioxide is deposited. After the deposition is completed, the sample is placed on a low-pressure chemical vapor deposition tray, with the newly deposited full back passivation oxide layer facing upward, and the gas is set to SiH ₄ and PH ₃ , and 150 nm of N-type polysilicon is deposited. After the deposition is completed, annealing is performed in a tubular annealing furnace for 20 minutes at a temperature of 800°C. After the annealing is completed, photolithography is performed on the front side (P region) of the device and electrodes are deposited by electron beam evaporation, and then the electrode is deposited on the back side by turning over. After stripping the photoresist, annealing treatment is performed at 400°C for 30 minutes in a rapid annealing furnace, and a PIN photodetector with excellent performance and a back passivation layer without openings can be prepared.

The performance of the device was simulated and analyzed. When the incident light with a wavelength of 600nm and an optical power of 1W/ ^m2 was irradiated, the photocurrent of the device could reach 4.3× ^10-5A . For the photodetector without a full back passivation layer, under the same conditions, the photocurrent of the device was only 3.7× ^10-6A .

Example 2

A PIN photodetector and a method for preparing a back passivation layer without an opening, comprising the following steps:

The back of the cleaned intrinsic silicon wafer (resistivity 20000Ω/cm) was coated with glue and placed in the ion implantation tray. B ions were implanted with an implantation energy of 120KeV and an implantation dose of 9×10 ¹⁴ cm ^-3. After debonding, the wafer was annealed in a tubular annealing furnace for 30 minutes at a temperature of 1000°C. After annealing, the implanted side was protected with glue and the other side was ion implanted with an energy of 120KeV and an implantation dose of 1.3×10 ¹⁵ cm ^-3. After debonding, the wafer was annealed in a tubular annealing furnace for 30 minutes at a temperature of 900°C.

The PIN photodetector obtained above is placed on an atomic layer deposition tray, with the N region facing upward, and 1.5 nm of aluminum oxide is deposited. After the deposition is completed, the sample is placed on a low-pressure chemical vapor deposition tray, with the newly deposited full back passivation oxide layer facing upward, and the gas is set to SiH ₄ and PH ₃ , and 100 nm of N-type polysilicon is deposited. After the deposition is completed, annealing is performed in a tubular annealing furnace for 20 minutes at a temperature of 750°C. After the annealing is completed, photolithography is performed on the front side (P region) of the device and electrodes are deposited by electron beam evaporation, and then the electrode is deposited on the back side by turning over. After stripping the photoresist, annealing treatment is performed at 400°C for 30 minutes in a rapid annealing furnace, and a PIN photodetector with excellent performance and a back passivation layer without openings can be prepared.

The performance of the device was simulated and analyzed. When the reverse bias voltage of the photodetector was -5V, the dark current of the device without a full back passivation functional layer was 1.3× ^10-12A . When the above-prepared device was calculated and analyzed, the dark current of the device was reduced to 1.24× ^10-12A under the same conditions.

It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The full back passivation method of the photoelectric detector is characterized by comprising the following steps of:

(1) Taking an intrinsic silicon wafer as a substrate, carrying out ion implantation of B element on one surface of the substrate, and annealing after P-type doping is formed after implantation; ion implantation of P element is carried out on the other surface of the substrate, and annealing is carried out after N-type doping is formed after implantation is completed, so that a PIN structure is formed;

(2) Depositing a full-back passivation tunneling functional layer on the N-type doped surface of the PIN structure obtained in the step (1), wherein the material of the full-back passivation tunneling functional layer is oxide or nitride;

(3) And (3) depositing N-type polycrystalline silicon on the full-back passivation tunneling functional layer obtained in the step (2), and annealing under the protective atmosphere condition, wherein the N-type polycrystalline silicon and the full-back passivation tunneling functional layer jointly form an open-pore-free back passivation layer.

2. The full back passivation method of the photodetector of claim 1, wherein the oxide is SiO ₂ or Al ₂O₃; the nitride is Si ₃N₄.

3. The full back passivation method of a photodetector of claim 1, wherein said full back passivation tunneling functional layer has a thickness of 0.5nm to 1.5nm.

4. The method of claim 1, wherein the source of gas used to inject the element B is BF ₃.

5. The method of claim 1, wherein the source of gas used to inject the P element is PH ₃.

6. The method of passivating the entire back surface of a photodetector of claim 1, wherein in step (3), the annealing is performed at a temperature of 700 to 900 ℃ for 20 to 30 minutes.

7. The full back passivation method of a photodetector of claim 1, wherein in step (3), the protective atmosphere is nitrogen or argon.

8. The full back passivation method of a photodetector of claim 1, wherein in step (3), said deposition method is low pressure chemical vapor deposition.

9. The full back passivation method of a photodetector of claim 1, wherein said N-type polysilicon has a thickness of 50nm to 150nm.

10. The full back passivation method of a photodetector of claim 1, wherein said intrinsic silicon resistivity is equal to or greater than 5000 Ω/cm.