CN118782552A - Chip packaging structure and packaging method - Google Patents

Abstract

The present application discloses a chip packaging structure and packaging method. The chip packaging structure includes: a substrate; a chip, which is mounted on the substrate and electrically connected to the substrate; a plastic package, which is arranged on the upper surface of the substrate and encapsulates the chip; a heat dissipation cover, which covers the upper surface of the chip and the plastic package, and is connected to the upper surface of the chip and the plastic package through a thermally conductive material. The present application reduces the range of the chip encapsulated by the plastic package, connects the heat dissipation cover to the upper surface of the chip and the plastic package through a thermally conductive material, so that the heat generated during the operation of the chip can be transferred to the heat dissipation cover through the thermally conductive material, thereby greatly improving the thermal conductivity of the chip and the plastic package.

Description

Chip packaging structure and packaging method

Technical Field

The present application relates to the field of chip packaging, and in particular to a chip packaging structure and a packaging method.

Background Art

Wire bonding is a traditional packaging technology that places the back of the chip against the substrate and the front side facing up, that is, the side with solder bumps on the chip faces up, and the electrical connection between the solder bumps of the chip and the pads on the substrate is achieved through metal wires.

Flip chip is a technology that places the front of the chip facing the substrate and interconnects the chip with the substrate by aligning the solder bumps on the chip with the pads on the substrate. This technology can provide higher I/O density, shorter interconnection distance, and has better electrical performance than wire bonding technology, and is also conducive to reducing chip packaging size.

As packaging technology develops towards miniaturization and high integration. Wafer-Level Packaging (WLP) can further reduce the size of the packaging structure by packaging the chip as a whole on the wafer and then cutting it after packaging. Chip Scale Package (CSP) refers to the size of the packaged chip as close to the size of the bare chip as possible, reducing the space occupied by the package and improving the integration. Flip Chip Chip Scale Package (FCCSP) is a chip scale package that uses a flip chip method.

In traditional packaging technology, a plastic package is usually used to encapsulate the chip to protect the chip. However, as the market has higher and higher requirements for product heat dissipation, the existing packaging structure cannot meet the high heat dissipation requirements.

Summary of the invention

The purpose of this application is to propose a chip packaging structure and a packaging method to solve the problem that the existing chip packaging structure cannot meet high heat dissipation requirements.

The present application provides a chip packaging structure, comprising: a substrate; a chip, which is mounted on the substrate and electrically connected to the substrate; a plastic package, which is arranged on the upper surface of the substrate and encapsulates the chip; a heat dissipation cover, which covers the chip and the upper surface of the plastic package, and is connected to the chip and the upper surface of the plastic package through a thermally conductive material.

In some embodiments, the thermally conductive material includes a first thermally conductive material and a second thermally conductive material, the bonding force of the second thermally conductive material is higher than that of the first thermally conductive material, the thermal conductivity of the first thermally conductive material is higher than that of the second thermally conductive material, the upper surface of the plastic package includes a first area and a second area, the first area is bonded to the heat dissipation cover through the first thermally conductive material, and the second area is bonded to the heat dissipation cover through the second thermally conductive material.

In the above embodiment, the second area at least partially surrounds the first area, and the second area is located outside the upper surface of the plastic package body.

In some embodiments, the chip and the heat dissipation cover are bonded together by the first thermally conductive material.

In other embodiments, the thermally conductive material includes a third thermally conductive material and a fourth thermally conductive material, the third thermally conductive material is a metal material, the chip is mounted on the substrate by flip-chip method, the back side of the chip is welded to the heat dissipation cover by the third thermally conductive material, and the upper surface of the plastic package is bonded to the heat dissipation cover by the fourth thermally conductive material.

In some embodiments, a portion where the lower surface of the heat dissipation cover is connected to the chip is provided with a plurality of protrusions and/or recesses.

In some embodiments, the area other than the connection portion between the heat dissipation cover and the chip has a hollow structure, and the hollow portion of the hollow structure is filled with the thermal conductive material.

On the other hand, the present application provides a chip packaging method, including: mounting a chip on a substrate and electrically connecting the chip to the substrate; forming a plastic package on the upper surface of the substrate through a molding process, wherein the plastic package encapsulates the chip; connecting a heat dissipation cover to the chip and the upper surface of the plastic package through a thermally conductive material, and allowing the heat dissipation cover to cover the chip and the upper surface of the plastic package.

In some embodiments, the thermally conductive material includes a first thermally conductive material and a second thermally conductive material, the bonding force of the second thermally conductive material is higher than that of the first thermally conductive material, the thermal conductivity of the first thermally conductive material is higher than that of the second thermally conductive material, the upper surface of the plastic package includes a first area and a second area, and connecting the heat dissipation cover to the chip and the upper surface of the plastic package through the thermally conductive material includes: bonding the heat dissipation cover to the chip and the first area of the upper surface of the plastic package through the first thermally conductive material, and bonding the heat dissipation cover to the second area of the upper surface of the plastic package through the second thermally conductive material.

In the above embodiment, the second area at least partially surrounds the first area, and the second area is located at the edge of the upper surface of the plastic packaging body.

In other embodiments, the thermally conductive material includes a third thermally conductive material and a fourth thermally conductive material, the third thermally conductive material is a metal material, and mounting the chip on the substrate and electrically connecting the chip to the substrate includes: mounting the chip on the substrate by flip-chip means and electrically connecting the chip to the substrate; connecting the heat dissipation cover to the chip and the upper surface of the plastic package body by the thermally conductive material includes: welding the heat dissipation cover to the back side of the chip by the third thermally conductive material, and bonding the upper surface of the plastic package body and the heat dissipation cover by the fourth thermally conductive material.

In some embodiments, a portion where the lower surface of the heat dissipation cover is connected to the chip is provided with a plurality of protrusions and/or recesses.

In some embodiments, the area outside the connection portion between the heat dissipation cover and the chip has a hollow structure, and connecting the heat dissipation cover to the chip and the upper surface of the plastic package body through the thermal conductive material further comprises: filling the hollow part of the hollow structure with thermal conductive material.

In the above embodiment, before the heat dissipation cover is connected to the chip and the upper surface of the plastic package body through the thermal conductive material, the method further includes: coating the upper surface of the heat dissipation cover with a high temperature resistant film; after the heat dissipation cover is connected to the chip and the upper surface of the plastic package body through the thermal conductive material, the method further includes: removing the high temperature resistant film coated on the upper surface of the heat dissipation cover.

The chip packaging structure and packaging method of the present application connect the heat dissipation cover to the upper surface of the chip and the plastic package body through the thermal conductive material, so that the heat generated during the operation of the chip can be transferred to the heat dissipation cover through the thermal conductive material, which greatly improves the thermal conductivity of the chip and the plastic package body and can meet higher chip heat dissipation requirements. The present application designs the heat dissipation cover to be flat and adds several raised parts and/or recessed parts on the back, which can increase the bonding force with the thermal conductive material; the heat dissipation cover is designed to be a mesh hollow structure, which can better absorb its own stress and reduce warping, ensure the bonding of the heat dissipation cover and the thermal conductive material, and avoid the warping of the heat dissipation cover causing delamination with the thermal conductive material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 shows a schematic diagram of an existing FCCSP packaging structure;

FIG2 is a schematic cross-sectional view of an embodiment of a chip packaging structure 1 of the present application;

FIG3 shows a top view of a heat dissipation cover 40 according to another embodiment of the present application;

FIG4 is a schematic cross-sectional view of a chip packaging structure 1 using the heat dissipation cover 40 in FIG3 ;

FIG5 is a schematic cross-sectional view of another embodiment of a chip packaging structure 1 of the present application;

FIG6 is a schematic cross-sectional view of yet another embodiment of the chip packaging structure 1 of the present application;

FIG. 7 is a schematic diagram showing an embodiment of a chip packaging method 100 of the present application;

8A-8H are schematic diagrams showing various steps of the chip packaging method 100 of the present application;

FIG9 is a schematic diagram showing an optional step S20 of the chip packaging method 100 of the present application;

FIG. 10 is a schematic diagram showing an optional step S40 of the chip packaging method 100 of the present application.

DETAILED DESCRIPTION

The present application is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but are not intended to limit the present application in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements can also be made without departing from the concept of the present application. These all belong to the protection scope of the present application.

FIG1 shows a schematic diagram of an existing FCCSP packaging structure. As shown in the figure, the chip 20' is facing down and flipped on the substrate 10'. The metal bumps on the front of the chip 20' form an electrical connection with the pads on the substrate 10'. The solder balls 11' are soldered on the lower surface of the substrate 10', and the chip 20' forms an electrical connection with the solder balls 11' through the circuit in the substrate 10'. The plastic encapsulation body 30' is arranged on the upper surface of the substrate 10' and completely encapsulates the chip 20', thereby protecting the chip 20' and reducing the risk of chip damage. The plastic encapsulation material used for plastic encapsulation is usually selected from epoxy resin and the like. The bottom filling glue can be filled between the front of the chip 20' and the substrate, or it can be filled directly through the plastic encapsulation body 30'. In order to improve the heat dissipation effect, the upper surface of the plastic encapsulation body 30' is usually provided with auxiliary heat dissipation components such as a heat sink (not shown in the figure). Since the thermal conductivity of the plastic encapsulation body is relatively low, generally 1 to 3 watts/(meter·Kelvin), the heat dissipation effect is poor, and it is difficult to meet the increasingly high heat dissipation requirements of current chips.

The FCCSP packaging structure shown in FIG1 can be manufactured using an existing FCCSP packaging process. The existing FCCSP packaging process includes the following steps:

Flip the chip onto the front side of the substrate and make electrical connections through solder bumps;

Use plastic encapsulation compound to completely encapsulate the chip;

Solder balls on the back side of the substrate.

In the FCCSP packaging process, when using plastic encapsulation to encapsulate the chip, it is necessary to bake the plastic encapsulation to fully solidify it, and the temperature is relatively high. When soldering solder balls on the back of the substrate, a high-temperature reflow soldering process is generally used, and the temperature is relatively high. Due to the different thermal expansion coefficients of the materials of the plastic encapsulation body, chip, and substrate, temperature changes may cause the three to expand or contract at different rates and amounts. Since the three are closely combined, during the temperature rise and fall process, thermal stress mismatch problems will occur along the contact surface direction of the three, which may cause the packaging structure product to warp and deform, and even cause abnormal delamination of the entire or partial packaging structure (such as the contact surface between the heat dissipation cover and the plastic encapsulation body), affecting the yield of the product. Thermal stress is the stress generated inside the object when the expansion or contraction is hindered due to external constraints and mutual constraints between internal parts when the object expands or contracts due to temperature changes.

In view of the above problems, the present application proposes a new chip packaging structure, which can improve the heat dissipation performance of the product on the one hand, and improve the influence of thermal stress on the other hand. FIG. 2 shows a schematic diagram of a cross-section of an embodiment of the chip packaging structure 1 of the present application. In each embodiment of the present application, FCCSP is taken as an example to illustrate the chip packaging structure of the present application, but it can be understood that the present application is not limited to FCCSP.

As shown in FIG. 2 , the chip packaging structure 1 includes a substrate 10 , a chip 20 , a plastic package 30 and a heat dissipation cover 40 .

The substrate 10 is used to carry the chip and provide electrical connection. The material of the substrate 10 can be silicon material, ceramic material, organic material, etc. The substrate 10 is provided with welding areas, pins or circuits (not shown in the figure) matching the solder bumps 22 of the chip 20.

The chip 20 is mounted on the substrate 10 and electrically connected to the substrate 10. The chip 20 can be mounted on the substrate 10 in various ways, such as wire bonding or flip chip mounting. The figure shows a flip chip mounting method, where the front side 21 of the chip 20 is connected to the substrate 10 through solder bumps 22, and the front side of the chip is the active side of the chip. In some embodiments, in order to protect the solder bumps 22 and ensure good circuit contact between the chip and the substrate 10, a filling material 23 such as a filling glue can also be used to fill between the front side 21 of the chip and the substrate 10.

The plastic package 30 is disposed on the upper surface of the substrate 10 and encapsulates the chip 20, exposing the back side 24 of the chip, so that a more flexible and effective heat dissipation design can be adopted. In other embodiments, the chip is mounted on the substrate by wire bonding, and the plastic package encapsulates the chip and its leads.

The heat dissipation cover 40 covers the chip 20 and the upper surface 31 of the plastic package, and is connected to the chip 20 and the upper surface 31 of the plastic package through the heat conductive material 41. The heat conductivity of the heat conductive material 41 is greater than the heat conductivity of the plastic package 30, for example, greater than 3 watts/(meter Kelvin). The heat conductive material 41 can be selected from heat conductive adhesives with adhesive force such as epoxy resin system glue and silicone resin system glue. The heat dissipation cover 40 is connected to the back of the chip 20, and the heat conductive material 41 does not contact the solder bumps of the chip 20. The heat conductive adhesive can contain solid fillers, such as aluminum powder, aluminum oxide powder, silver powder, etc., to improve thermal conductivity. If the heat dissipation cover 40 is connected to the front of the chip 20, the heat conductive material 41 covers the upper surface 31 of the plastic package, and the heat conductive adhesive can contain solid fillers, such as aluminum powder, aluminum oxide powder, silver powder, etc., to improve thermal conductivity. In addition, the heat dissipation cover 40 has a flat shape for better heat dissipation. In order to ensure that the heat dissipation cover meets certain mechanical strength and has good heat dissipation performance, the thickness of the heat dissipation cover can be set to 0.8-1.2 mm.

In some embodiments, the heat dissipation cover can be made of a metal material with high thermal conductivity, such as aluminum, copper, etc. Furthermore, in order to enhance the anti-oxidation performance, an inert metal can be plated on a conventional metal material, such as copper-plated nickel, copper-plated gold-nickel, etc. In some embodiments, the outer edge of the heat dissipation cover 40 is flush with the outer edge of the upper surface 31 of the plastic package body 30, so that the outer contour of the chip packaging structure 1 is more neat and regular, which is convenient for cutting, storage, robot arm grasping, installation, etc. In some embodiments, the upper surface of the heat dissipation cover 40 is further connected to auxiliary heat dissipation components such as a radiator (not shown in the figure) to further improve the heat dissipation effect.

In some embodiments, the lower surface of the heat dissipation cover 40 is provided with a plurality of protrusions and/or depressions to increase the surface roughness, thereby enhancing the bonding force with the thermal conductive material 41. The protrusions and/or depressions can be set to various geometric shapes as required, such as one or more of triangles, squares, circles, plum blossoms, etc. Correspondingly, the portion where the chip 20 is connected to the heat dissipation cover and the upper surface 31 of the plastic package can also be increased in roughness by grinding or the like, thereby enhancing the bonding force with the thermal conductive material 41.

The chip packaging structure 1 of the present application reduces the range of the chip encapsulated by the plastic package body, and connects the heat dissipation cover 40 to the chip 20 and the upper surface 31 of the plastic package body 30 through a conductive material 41 with a higher thermal conductivity than the plastic package body 30, so that the heat generated during the operation of the chip can be transferred to the heat dissipation cover via the chip 20 and the upper surface 31 of the plastic package body through the thermal conductive material, thereby greatly improving the heat dissipation performance of the packaging structure 1.

The chip packaging structure 1 has better heat dissipation performance than the prior art, but there are still problems such as warping and delamination of the packaging structure product due to thermal stress mismatch. In order to further overcome the problems of warping and delamination of the packaging structure product, the present application further improves the structure of the heat dissipation cover, as shown in Figures 3 and 4.

FIG3 shows a top view of a heat dissipation cover 40 of another embodiment of the present application, and FIG4 shows a schematic diagram of a cross-section of a chip packaging structure 1 using the heat dissipation cover 40 in FIG3 . As shown in the figure, a hollow structure 42 is provided on the heat dissipation cover 40, and the hollow structure 42 can be provided in an area other than the connection part with the chip 20, and the hollow part of the hollow structure 42 is filled with a thermal conductive material 41. The hollow structure can have various forms, and the mesh shape of the grid-like hollow structure shown in FIG4 is a rectangle. In other embodiments, the hollow structure may not be in a grid shape, for example, a plurality of meshes are arranged in an arc shape, or arranged irregularly, etc. The mesh shape may be one or more of a square, a rectangle, a circle, an ellipse, a triangle, a pentagon, a plum blossom, and a star shape. The mesh shape using a polygonal shape, a plum blossom shape, a star shape, etc., which is more than a pentagon, is conducive to increasing the bonding strength with the filled thermal conductive material 41.

By providing a hollow structure on the heat dissipation cover 40, when the heat dissipation cover 40 expands or contracts due to temperature changes, the heat dissipation cover 40 body around the hollow part can be deformed in the direction of the hollow part without being hindered, so that the thermal stress exerted on the heat dissipation cover 40 along the flat direction can be released through the hollow structure, thereby reducing the problems of warping, deformation and delamination of the heat dissipation cover 40.

Furthermore, the heat generated during the operation of the chip 20 can be conducted to the heat sink disposed on the upper surface of the heat dissipation cover via the heat conductive material 41 of the hollowed-out portion without passing through the heat dissipation cover. Furthermore, a heat conductive material 41 having a higher thermal conductivity than the heat dissipation cover can be used, thereby further improving the heat conduction efficiency. FIG. 5 shows a schematic diagram of a cross section of another embodiment of the chip packaging structure 1 of the present application. In some embodiments, the heat conductive material 41 includes a first heat conductive material 411 and a second heat conductive material 412, the bonding force of the second heat conductive material 412 is higher than that of the first heat conductive material 411, and the thermal conductivity of the first heat conductive material 411 is higher than that of the second heat conductive material 412. For example, the first heat conductive material 411 can select a heat conductive material with high thermal conductivity but insufficient bonding force, such as film graphene, carbon fiber, liquid metal, phase change material, etc., while the second heat conductive material 412 can select a heat conductive material with low thermal conductivity but strong bonding force, such as epoxy resin system glue and silicone resin system glue. In some embodiments, the upper surface of the plastic package 30 includes a first area 311 and a second area 312. The first area 311 is bonded to the heat dissipation cover 40 through the first heat conductive material 411, and the second area 312 is bonded to the heat dissipation cover 40 through the second heat conductive material 412. In this way, by reasonably setting the first area 311 and the second area 312, such as setting the second area 312 to partially or completely surround the first area 311, and setting the second area 312 at the edge of the upper surface 31 of the plastic package (as shown in FIG. 5), the heat conduction effect can be greatly improved under the premise of ensuring that the upper surface of the plastic package is firmly combined with the heat dissipation cover 40. In some embodiments, the first area 311 and the second area 312 can also be set in other ways, such as at intervals. Since the chip 20 is located in the middle of the upper surface of the plastic package, in order to ensure the heat dissipation of the chip, in some embodiments, the chip 20 and the heat dissipation cover 40 are also bonded through the first heat conductive material 411. When the part where the chip is connected to the heat dissipation cover is the front of the chip, the first heat conductive material 411 should be an insulating material. In other embodiments, the chip 20 and the heat dissipation cover 40 may also be welded by other heat-conducting materials, such as metal materials such as indium sheets, to achieve both strong bonding and high thermal conductivity.

FIG6 shows a schematic diagram of a cross section of another embodiment of the chip packaging structure 1 of the present application. In this embodiment, the heat-conducting material 41 includes a third heat-conducting material 413 and a fourth heat-conducting material 414, the third heat-conducting material 413 is a metal material, the chip 20 is mounted on the substrate 10 by flip-chip mode, the back side 24 of the chip 20 is welded with the heat dissipation cover 40 through the third heat-conducting material 413, and the upper surface 31 of the plastic package 30 is bonded with the heat dissipation cover 40 through the fourth heat-conducting material 414. The metal material can be selected from high thermal conductivity metals such as indium sheets, one side of which is welded with the heat dissipation cover 40 and the other side is welded with the back side 24 of the chip, which can provide strong bonding force and high thermal conductivity. The fourth heat-conducting material 414 can be selected from heat-conducting materials with strong bonding force such as epoxy resin system glue and silicone resin system glue. The fourth heat-conducting material 414 surrounds the third heat-conducting material 413 to prevent the third heat-conducting material 413 from diffusing during the welding process.

In some embodiments, the lower surface of the substrate 10 may also include one or more of circuits, solder balls, pins, etc., for installation and circuit connection of the chip packaging structure 1. FIG2 exemplarily shows solder balls 11 on the lower surface of the substrate 10.

The present application connects the heat dissipation cover to the upper surface of the chip and the plastic package body through a thermally conductive material, so that the heat generated during the operation of the chip can be efficiently dissipated through the heat dissipation cover, greatly improving the heat dissipation effect of the package structure product. Furthermore, by setting a hollow structure on the heat dissipation cover, it is conducive to releasing stress, alleviating the problem of thermal stress mismatch between the plastic package body, the chip and the heat dissipation cover during the baking and curing or welding process of the thermal conductive material, reducing the risk of warping deformation and delamination, and also helping to improve the heat dissipation effect.

The present application also provides a chip packaging method 100, which can be used to manufacture various embodiments of the chip packaging structure 1 of the present application. FIG7 shows a schematic diagram of an embodiment of the chip packaging method 100 of the present application, and FIG8A to FIG8H show schematic diagrams of various steps of the chip packaging method 100 of the present application. Specifically, the method 100 includes the following steps:

S10, mounting the chip on the substrate and electrically connecting the chip to the substrate.

For example, the chip is mounted by wire bonding or flip-chip mounting. FIG8A shows a case where the chip 20 is mounted by flip-chip mounting, with the front side of the chip 20 facing the substrate, and the solder bumps 22 are connected to the pads or leads (not shown) on the substrate 10. In other embodiments, the chip is mounted on the substrate by wire bonding, with the back side facing the substrate, and the electrical connection between the solder bumps on the front side of the chip and the pads on the substrate is achieved by metal wires.

S30, forming a plastic package on the upper surface of the substrate through a molding process, the plastic package encapsulating the chip to expose the front side or the back side of the chip.

The molding process specifically includes methods such as mold injection molding, such as wrapping the substrate 10 and the chip 20 with materials such as epoxy resin to form a plastic package 30. For chips installed in a flip-chip manner, as shown in FIG8B , after the plastic package 30 encapsulates the chip 20, the back side 24 of the chip is fully or partially exposed. In an embodiment in which the chip is installed on the substrate by wire bonding, after the plastic package encapsulates the chip, the front side of the chip is fully or partially exposed. In some embodiments, the plastic package needs to be cured by high-temperature baking after encapsulation. In some embodiments, the upper surface 31 of the plastic package can be polished to increase the roughness, thereby increasing the bonding force with the thermal conductive material in subsequent processes.

S50, connecting the heat dissipation cover to the upper surfaces of the chip and the plastic package body through a thermally conductive material, and making the heat dissipation cover the upper surfaces of the chip and the plastic package body.

A heat conductive material 41 can be coated on the lower surface of the heat dissipation cover 40 (as shown in FIG. 8C ), and then connected to the upper surface 31 of the plastic package and the chip 20. A heat conductive material 41 can also be coated on the upper surface 31 of the plastic package and the chip 20 (as shown in FIG. 8D ), and then connected to the lower surface of the heat dissipation cover 40. Both of the above methods can obtain the chip packaging structure 1 shown in FIG. 4 .

The thermal conductive material 41 can be selected from epoxy resin system glue, silicone resin system glue and other thermal conductive glues with strong bonding force, which are not easy to flow even if coated with sufficient thickness. The thermal conductivity of the thermal conductive material 41 is preferably greater than the thermal conductivity of the plastic package material, for example, greater than 3 W/(m·Kelvin).

In some embodiments, a portion of the lower surface of the heat dissipation cover 40 connected to the chip is provided with a plurality of protrusions and/or depressions, which can increase the surface roughness and thus enhance the bonding force with the thermal conductive material 41 .

In some embodiments, the heat dissipation cover 40 has a hollow structure 42, and the hollow part of the hollow structure 42 is filled with a heat conductive material 41. The heat conductive material 41 can be first filled in the hollow part of the hollow structure 42 (see FIG. 8C) and then bonded to the upper surface 31 of the plastic package and the chip 20. If the heat conductive material 41 is a heat conductive adhesive, after the heat dissipation cover 40 is bonded to the upper surface 31 of the plastic package and the chip 20, in order to cure the heat conductive adhesive, the chip packaging structure 1 needs to be baked as a whole. The baking temperature can be selected from 100 to 200 degrees Celsius, and the baking time can be selected from 1 to 2 hours. The heat conductive material 41 can also be first arranged on the upper surface 31 of the plastic package and the chip 20, and then bonded to the heat dissipation cover. The heat conductive material 41 is squeezed and filled into the hollow part of the hollow structure 42 (see FIG. 8D). If the heat conductive material 41 is a heat conductive adhesive, a baking and curing process also needs to be added. Both of the above methods can connect the heat dissipation cover 40 to the chip 20 and the upper surface 31 of the plastic package. In some implementations of step S50, thermally conductive materials with different physical properties may be used to connect the heat dissipation cover to different regions of the upper surface of the plastic package. The chip packaging structure 1 shown in FIG5 may be obtained through this implementation.

In this embodiment, the first thermal conductive material 411 is used to bond the heat dissipation cover 40 to the chip 20 and the first area 311 on the upper surface of the plastic package, and the second thermal conductive material 412 is used to bond the heat dissipation cover 40 to the second area 312 on the upper surface of the plastic package. The second thermal conductive material 412 has a higher bonding force than the first thermal conductive material 411, and the first thermal conductive material 411 has a higher thermal conductivity than the second thermal conductive material 412.

Similarly, the second thermally conductive material 412 can first cover the portion of the lower surface of the heat dissipation cover corresponding to the second area 312 of the upper surface of the plastic package, and the first thermally conductive material 411 can be filled in the hollow part of the hollow structure 42 and cover other portions of the lower surface of the heat dissipation cover (see FIG. 8E ), and then bonded to the upper surface of the plastic package and the chip 20. If the thermally conductive material includes thermally conductive glue, a baking and curing process is required. Alternatively, the second thermally conductive material 412 can be first arranged in the second area 312 of the upper surface of the plastic package, and the first thermally conductive material 411 can be arranged in the first area 311 of the upper surface of the plastic package and the chip 20 (see FIG. 8F ), and then bonded to the heat dissipation cover. The first thermally conductive material 411 is squeezed and filled into the hollow part of the hollow structure 42. If the thermally conductive material includes thermally conductive glue, a baking and curing process is required. Both of the above methods can obtain the chip packaging structure 1 shown in FIG. 5 .

In some embodiments, the second region 312 is located outside the first region 311, so that a more stable bonding effect can be obtained. In some embodiments, the second region 312 surrounds the first region 311 in whole or in part, and the second region 312 is located at the edge of the upper surface of the plastic package (as shown in FIG. 8F ).

Furthermore, in some implementations of step S50, different heat-conducting materials and different connection methods may be used to connect the heat dissipation cover to the upper surface of the chip and the plastic package. The chip packaging structure 1 shown in FIG6 may be obtained through this implementation.

In this embodiment, the thermal conductive material includes a third thermal conductive material and a fourth thermal conductive material. The third thermal conductive material 413 is made of a metal with high thermal conductivity, such as an indium sheet, and the fourth thermal conductive material 414 is made of a thermal conductive adhesive such as an epoxy resin system glue or a silicone resin system glue. The chip is mounted on the substrate in a flip-chip manner and is electrically connected to the substrate. The third thermal conductive material 413 is used to weld the heat dissipation cover 40 to the back side 24 of the chip, and the fourth thermal conductive material 414 is used to bond the heat dissipation cover 40 to the upper surface 31 of the plastic package.

Similarly, the third thermally conductive material 413 can be first welded to the position of the lower surface of the heat dissipation cover 40 corresponding to the back side 24 of the chip, and the fourth thermally conductive material 414 can be filled in the hollow part of the hollow structure 42 and cover other parts of the lower surface of the heat dissipation cover 40 (see Figure 8G), and then fit with the back side 24 of the chip and the upper surface 31 of the plastic package, and then the third thermally conductive material 413 can be welded to the back side 24 of the chip, and the welding method can be reflow soldering. The maximum temperature of reflow soldering is determined according to the melting point of the metal thermally conductive material, generally between 100 and 300 degrees Celsius. Because the high temperature environment of reflow soldering can cure the fourth thermally conductive material 414 at the same time, there is no need to perform a separate process of baking and curing the thermal conductive adhesive. Alternatively, the third thermally conductive material 413 may be first disposed on the back side 24 of the chip, solder may be arranged on both sides of the third thermally conductive material 413 (without prior soldering), and the fourth thermally conductive material 414 may be disposed on the upper surface 31 of the plastic package (see FIG. 8H ), and then fitted with the heat dissipation cover 40, and after the fourth thermally conductive material 414 is squeezed and filled into the hollow part of the hollow structure 42, the third thermally conductive material 413 may be heated and soldered to the heat dissipation cover 40 and the back side 24 of the chip at the same time. The above two methods can obtain the chip packaging structure 1 shown in FIG. 6 . However, the latter method only requires one soldering, and the process is simpler.

In some embodiments, in order to protect the connection between the solder bump 22 and the substrate 10 and prevent the solder bump 22 from being broken or oxidized in subsequent processes, thereby causing poor contact between the chip 20 and the substrate 10, before step S30, the method 100 further includes step S20, using an insulating material 60, such as bottom filler, to fill the gap between the chip 20 and the substrate 10. FIG9 shows a schematic diagram of step S20.

In some embodiments, before step S50, the method 100 may further include step S40, and after step S50, the method 100 may further include step S60. In step S40, a high temperature resistant film 50 is applied to the upper surface of the heat dissipation cover 40, as shown in FIG10 . In step S60, the high temperature resistant film 50 applied to the upper surface of the heat dissipation cover 40 is removed. By applying a film on the upper surface of the heat dissipation cover 40, it is possible to prevent the heat conductive material filled in the hollow part 42 in the subsequent process from overflowing from the upper surface of the heat dissipation cover 40. It should be pointed out that the high temperature resistant film 50 should be able to withstand the high temperature environment of the baking or reflow soldering process in step S50. According to the specific process, it is generally necessary to withstand a temperature of at least 200 degrees Celsius or 300 degrees Celsius to avoid melting or damage in a high temperature environment.

The chip packaging structure and packaging method of the present application reduce the range of the chip encapsulated by the plastic package, and use a thermally conductive material with a higher thermal conductivity than the plastic package to connect the heat dissipation cover to the upper surface of the chip and the plastic package. By selecting and combining thermally conductive materials, the advantages of various thermally conductive materials are fully utilized to improve the heat dissipation effect of the chip and the plastic package, and can meet higher chip heat dissipation requirements.

The present application also reduces problems such as warping, deformation and delamination caused by the difference in thermal expansion coefficient between the heat dissipation cover material and the plastic package body material during temperature changes by arranging a hollow structure on the heat dissipation cover.

In addition, although the present application uses the FCCSP packaging structure as an example to illustrate the chip packaging structure 1 and the packaging method 100, those skilled in the art can understand that the chip packaging structure and packaging method of the present application can be applicable to other types of chip packaging that use a plastic package to encapsulate the chip, such as a quad flat no-lead flip chip (Quad Flat No-lead Flip Chip, referred to as QFNFC) packaging, a land grid array (LGA) packaging with a wire bonding method, a quad flat package (Quad Flat Package), etc.

A person skilled in the art can understand and implement other changes to the disclosed embodiments, including adapting the structures and methods to other packaging types, by reading the specification, the disclosed contents, the drawings and the attached claims. In the claims, the wording "comprising" does not exclude other elements and steps, and the words "a" and "an" do not exclude the plural. In the actual application of this application, a part may perform the functions of multiple technical features cited in the claims. Any figure marks in the claims should not be construed as limiting the scope.

Claims (14)

1. A chip package structure, comprising:

A substrate;

The chip is mounted on the substrate and is electrically connected with the substrate;

the plastic package body is arranged on the upper surface of the substrate and encapsulates the chip;

And the heat dissipation cover covers the upper surfaces of the chip and the plastic package body and is connected to the upper surfaces of the chip and the plastic package body through a heat conduction material.

2. The chip package structure of claim 1, wherein the thermally conductive material comprises a first thermally conductive material and a second thermally conductive material, the second thermally conductive material having a higher adhesion than the first thermally conductive material, the first thermally conductive material having a higher thermal conductivity than the second thermally conductive material, the upper surface of the molded body comprising a first region and a second region, the first region being bonded to the heat sink cap by the first thermally conductive material, the second region being bonded to the heat sink cap by the second thermally conductive material.

3. The chip package structure of claim 2, wherein the second region at least partially surrounds the first region, and the second region is located at an edge of an upper surface of the plastic package body.

4. The chip package structure of claim 2, wherein the chip and the heat spreader lid are bonded by the first thermally conductive material.

5. The chip package structure of claim 1, wherein the heat conductive material comprises a third heat conductive material and a fourth heat conductive material, the third heat conductive material is a metal material, the chip is mounted on the substrate in a flip-chip manner, the back surface of the chip is welded with the heat dissipation cover through the third heat conductive material, and the upper surface of the plastic package body is bonded with the heat dissipation cover through the fourth heat conductive material.

6. The chip packaging structure according to claim 1, wherein a plurality of protruding portions and/or recessed portions are provided at a portion of the lower surface of the heat dissipation cover, where the lower surface of the heat dissipation cover is connected to the chip.

7. The chip package structure according to any one of claims 1 to 6, wherein an area other than a connection portion between the heat dissipation cover and the chip has a hollowed-out structure, and a hollowed-out portion of the hollowed-out structure is filled with a heat conductive material.

8. A method of chip packaging, comprising:

Mounting a chip on a substrate and electrically connecting the chip with the substrate;

forming a plastic package body on the upper surface of the substrate through a molding process, wherein the plastic package body encapsulates the chip;

and connecting a heat dissipation cover to the upper surfaces of the chip and the plastic package body through a heat conduction material, and enabling the heat dissipation cover to cover the upper surfaces of the chip and the plastic package body.

9. The chip packaging method according to claim 8, wherein the heat conductive material includes a first heat conductive material and a second heat conductive material, the second heat conductive material having a higher adhesion than the first heat conductive material, the first heat conductive material having a higher heat conductivity than the second heat conductive material, the upper surface of the plastic package body including a first region and a second region, and connecting the heat dissipation cap to the chip and the upper surface of the plastic package body by the heat conductive material includes:

And bonding the heat dissipation cover with the chip and a first area of the upper surface of the plastic package body through the first heat conduction material, and bonding the heat dissipation cover with a second area of the upper surface of the plastic package body through the second heat conduction material.

10. The chip packaging method of claim 9, wherein the second region at least partially surrounds the first region, and the second region is located at an edge of an upper surface of the plastic package.

11. The chip packaging method of claim 8, wherein the thermally conductive material comprises a third thermally conductive material and a fourth thermally conductive material, the third thermally conductive material being a metallic material, the mounting the chip on the substrate and electrically connecting with the substrate comprising:

Mounting a chip on a substrate in a flip-chip manner and electrically connecting the chip with the substrate;

connecting the heat dissipation cap to the upper surfaces of the chip and the plastic package body through a heat conductive material includes:

And welding the heat dissipation cover to the back surface of the chip through the third heat conduction material, and bonding the upper surface of the plastic package body and the heat dissipation cover through the fourth heat conduction material.

12. The chip packaging method according to claim 8, wherein a plurality of protruding portions and/or recessed portions are provided at a portion of the lower surface of the heat dissipating cover where the chip is connected.

13. The method of any one of claims 8-12, wherein the area outside the connection portion between the heat dissipating cover and the chip has a hollowed-out structure, and connecting the heat dissipating cover to the upper surfaces of the chip and the plastic package body by a heat conducting material further comprises:

and filling heat conducting materials in the hollow part of the hollow structure.

14. The chip packaging method of claim 13, wherein prior to attaching the heat spreading cover to the chip and the upper surface of the plastic package body by a thermally conductive material, the method further comprises:

a high temperature resistant film is adhered to the upper surface of the heat radiation cover;

After the heat-dissipating cover is attached to the chip and the upper surface of the plastic package by the thermally conductive material, the method further comprises:

and removing the high-temperature-resistant film attached to the upper surface of the heat dissipation cover.