CN118782548A - Package and method of forming the same - Google Patents

Abstract

In an embodiment, a package includes: an integrated circuit die including a first insulating bonding layer and a first semiconductor substrate; and an interposer including a second insulating bonding layer, a first sealing ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with a dielectric-to-dielectric bond, and wherein the integrated circuit die overlaps the first sealing ring. The sidewalls of the integrated circuit die are exposed at the outer sidewalls of the package. Embodiments of the present disclosure also relate to a method of forming a package.

Description

Package and method of forming the same

Technical Field

Embodiments of the present disclosure relate to packages and methods of forming the same.

Background Art

Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) In most cases, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

These integration improvements are essentially two-dimensional (2D) in nature, as the area occupied by the integrated components is substantially on the surface of the semiconductor wafer. The increased density of integrated circuits and the corresponding reduction in area have generally outstripped the ability to bond integrated circuit chips directly to substrates. Interposers have been used to redistribute ball contact areas from the ball contact areas of the chips to larger areas of the interposer. In addition, interposers have allowed three-dimensional packages that include multiple chips. Other packages have also been developed to incorporate three-dimensional aspects.

Summary of the invention

Some embodiments of the present disclosure provide a package, comprising: an integrated circuit die, including a first insulating bonding layer and a first semiconductor substrate; and an intermediate layer, including a second insulating bonding layer, a first sealing ring, and a second semiconductor substrate, wherein the second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonding, and wherein the integrated circuit die overlaps with the first sealing ring, and wherein side walls of the integrated circuit die are exposed at outer side walls of the package.

Other embodiments of the present disclosure provide a method for forming a package, the method comprising: bonding a first integrated circuit die to an interposer, wherein the interposer comprises a first sealing ring and a second sealing ring; dispensing a sealant around the first integrated circuit die; and after dispensing the sealant, performing a singulation process on the interposer in an area between the first sealing ring and the second sealing ring to form a singulated package, wherein the singulation process removes a portion of the first integrated circuit die, a first portion of the sealant on a sidewall of the first integrated circuit die, and a portion of the interposer between the first sealing ring and the second sealing ring.

Still other embodiments of the present disclosure provide a method comprising: bonding an integrated circuit die to an interposer, wherein the integrated circuit die comprises a first sealing ring and a sacrificial area between the first sealing ring and an outer side wall of the integrated circuit die; dispensing a sealant around the integrated circuit die; and performing a singulation process to form a singulated package, wherein the singulation process is performed through the interposer and the sacrificial area of the integrated circuit die, and wherein, after the singulation process, the integrated circuit die is exposed at the outer side wall of the singulated package.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

Figures 1, 2, 3, 4, 5, 6A, 6B, 7A, 7B, 7C, 7D, 8, 9, 10, 11A, 11B, 12A, 12B, 12C, 12D, 13A and 13B show different views of various intermediate stages of manufacturing a semiconductor package according to various embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or others) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

According to various embodiments, an integrated circuit package is formed by directly bonding an integrated circuit die to a wafer containing another device, such as an interposer, and a molding compound is dispensed around the integrated circuit die as a sealant. The singulation process is then performed by cutting through the interposer and the integrated circuit die. For example, sacrificial areas and interposers along the periphery of the integrated circuit die may be included in the device design so that no functional circuits are formed in these sacrificial areas. The singulation process may then be performed to cut through the sacrificial areas. In some embodiments, the sacrificial area of the interposer may be defined by one or more sealing rings, and at least one sealing ring is disposed directly below the integrated circuit die.

In this way, excess overhang of the molding compound and interposer around the periphery of the integrated circuit die is removed, advantageously reducing stress in the resulting package. For example, excess overhang of the bottom interposer may cause excessive bending due to changes in temperature conditions during operation, thereby degrading the bonding interface of the package. By reducing or eliminating excess overhang in the bottom interposer, stress in the bonded package can be relieved (e.g., reducing undesired bending). It has been observed that in packages produced by the embodiment singulation method, stress can be reduced by up to 84% under high temperature operating conditions, and stress can be reduced by up to 97% under low temperature operating conditions.

FIG. 1 is a cross-sectional view of a wafer 40 including an integrated circuit die 50. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc. or a combination thereof (e.g., a system on chip (SoC) die). The integrated circuit die 50 may be formed in a wafer 40, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies 50. Specifically, the device regions may be separated by a scribe line region 48, in which a subsequent singulation process is performed. Each of the integrated circuit dies 50 includes a semiconductor substrate 52 , an interconnect structure 54 , and bonding pads 56 disposed in an insulating bonding layer 58 .

The semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., a surface facing upward) and a non-active surface (e.g., a surface facing downward). The device is located at the active surface of the semiconductor substrate 52. The device may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. The non-active surface may be free of devices.

The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 to form one or more integrated circuits. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization patterns located in the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. The metallization pattern may include conductive vias and/or wires to interconnect the devices of the semiconductor substrate 52. The metallization pattern may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The interconnect structure 54 may also include a metal pad 54' that is connected through one or more passivation layers to the topmost metallization pattern of the interconnect structure 54. An additional insulating layer (e.g., a passivation layer) may be formed around the metal pad 54' to provide a flat surface on which to form the upper insulating bonding layer 58.

The bonding pad 56 is located at the front side of the integrated circuit die 50. The bonding pad 56 can be a conductive column, a pad, etc. for external connection. The bonding pad 56 can be formed of a metal such as copper, aluminum, etc., and the bonding pad 56 can be formed by, for example, plating, etc. In some embodiments, the bonding pad 56 can be electrically connected to the conductive component (e.g., metal pad 54') of the interconnect structure 54 through a conductive via (sometimes referred to as a bonding pad via). The integrated circuit die 50 also includes one or more sealing rings 60 located at the periphery of each integrated circuit die 50. Each sealing ring 60 can be arranged to surround the functional metallization pattern in the interconnect structure 54 of each integrated circuit die 50 and the ring of the corresponding bonding pad 56 (e.g., see Figure 6B). The sealing ring 60 can include a bonding pad portion at the same level as the metallization pattern in the interconnect structure 54 (the metallization pattern is all vertically stacked and connected together by, for example, conductive vias) and the bonding pad 56. As will be explained in more detail later, the seal ring 60 may also serve as a boundary for a sacrificial region that will be removed during the singulation process after the integrated circuit die is directly bonded to another packaging component (e.g., an interposer). In this way, the integrated circuit die 50 may not include any metallization patterns and/or bond pads 56 located outside the seal ring 60.

The bonding pad 56 can be disposed in an insulating bonding layer 58 at the front side 50F of the integrated circuit die 50. The insulating bonding layer 58 can be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, etc. The insulating bonding layer 58 can be deposited on the interconnect structure, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The bonding pad 56 can be formed in the insulating bonding layer using, for example, a damascene process, and a planarization process (e.g., chemical mechanical polishing (CMP), etc.) can be performed so that the top surfaces of the bonding pad 56 and the insulating bonding layer 58 are coplanar (within process variations) and so that the top surface of the bonding pad 56 is exposed at the front side 50F of the integrated circuit die 50. As will be described in more detail below, the planarized front side 50F of the integrated circuit die 50 will be directly bonded to another packaging component (such as an interposer).

In some embodiments, the integrated circuit die 50 is a stacked device including multiple semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including multiple memory dies, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, etc. In such an embodiment, the integrated circuit die 50 includes multiple semiconductor substrates 52 interconnected by through-substrate vias or through-silicon vias (TSVs). Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54.

2-4 are different views of intermediate steps during the singulation process of separating integrated circuit dies 50 from wafer 40. Beginning with FIG.

In some embodiments, a shallow groove 62 is formed in the scribe area 48 using a plasma cutting process. The plasma cutting process may include forming a patterned mask 55, which may be a photomask patterned by photolithography or the like. The plasma cutting process etches portions of the insulating bonding layer 58 that are exposed by a pattern (e.g., an opening) in the patterned mask 55. As shown in FIG. 2 , the shallow groove 62 extends into the insulating bonding layer 58. In some embodiments, the shallow groove 62 extends through the insulating bonding layer 58 and may further extend into the dielectric layer of the interconnect structure 54. However, because the groove 62 is relatively shallow, the shallow groove 62 does not extend into the semiconductor substrate 52. For example, the bottom surface of the groove 62 may be above the top surface of the semiconductor substrate 52. In some embodiments, the depth D1 to which the groove 62 extends may be less than or equal to 100%. The relatively shallow recess 62 does not extend into the semiconductor substrate 52, so the integrated circuit die 50 can be easily adhered to the underlying components (e.g., interposer) by the sealant, which will be explained later. In some embodiments, the plasma dicing is a dry plasma process, such as reactive ion etching (RIE) using fluorine-based plasma, argon-based plasma, oxygen-based plasma, nitrogen-based plasma, etc.

3 , an optional slotting process is performed to define trenches 64 in the scribe area 48 between adjacent integrated circuit dies 50. The slotting process may be performed through the grooves 62 so that the trenches 64 are connected to the grooves 62. The trenches 64 may extend from the grooves 62 into the semiconductor substrate 52. In some embodiments, the slotting process may be a laser slotting process, another plasma cutting process (e.g., a deep plasma cutting process), etc. The trenches 64 may be narrower than the grooves 62.

4 , a sawing process is performed to completely separate the integrated circuit dies 50 from each other and from the wafer 40. The sawing process may be performed through the recesses 62 and the trenches 64 (if present) in the scribe area 48. In some embodiments, the sawing process is a mechanical process using a saw blade that is placed in the recesses 62 and the trenches 64 to saw through the remaining semiconductor substrate 52. In other embodiments, other sawing processes may be used.

After the sawing process, each singulated integrated circuit die 50 includes an optional platform 62' (corresponding to the position of the groove 62) and an optional platform 64' (corresponding to the position of the groove 64). Due to the difference between the plasma cutting process and the sawing process, the surfaces of different areas of the integrated circuit die 50 may have different roughnesses. For example, the surface of the platform 62' formed by plasma cutting (the sidewall of the insulating bonding layer 58) may be smoother than the sidewall of the semiconductor substrate 52 formed by mechanical sawing. The platform 62' provides an artificial delamination surface that can be adhered to the underlying package component by a subsequently formed molding compound (see Figures 7B to 7C) to effectively reduce delamination defects in the bonding structure.

After singulation, each integrated circuit die 50 includes a sacrificial region 46 extending from the seal ring 60 to the outer sidewall of the integrated circuit die 50. The sacrificial region 46 does not have any functional circuits (e.g., there is no metallization pattern or bonding pad 56 located in the interconnect structure 54), and the size of the sacrificial region 46 can be defined in the design rules of the layout file corresponding to the integrated circuit die 50 so that no active circuits are provided in the sacrificial region 46. In this way, a subsequent singulation process (see Figures 11A to 12D) can be performed through the sacrificial region 46 to remove at least a portion of the sacrificial region 46. In various embodiments, the lateral dimension L1 of the sacrificial region (e.g., the lateral dimension measured from the seal ring 60 to the outer sidewall of the integrated circuit die 50) can be in the range of 3μm to 100μm. It has been observed that when the lateral dimension L1 of the sacrificial region 46 is less than 3μm, there is not enough space to perform the subsequent singulation process, and the various benefits of the singulation process described below cannot be achieved. It has been observed that when the lateral dimension L1 of the sacrificial region 46 is greater than 100 μm, the remaining space for functional circuits in the integrated circuit die 50 is unacceptably low.

Although FIGS. 2-4 illustrate a particular method of singulating integrated circuit die 50, it should be understood that other singulation processes may be used in other embodiments. For example, the plasma cutting process of FIG. 2 and/or the laser slotting process of FIG. 3 may be excluded. In such embodiments, platforms 62′ and/or 64′ may also be excluded.

5 to 13B are cross-sectional views of intermediate steps during a process of forming an integrated circuit package according to some embodiments. Details of the integrated circuit die 50 may be simplified in FIGS. 5 to 13B for ease of illustration. FIGS. 5 to 13B illustrate a particular package configuration, but it should be understood that other package configurations may also be used.

In FIGS. 5 to 10 , an integrated circuit package 100 is formed by bonding an integrated circuit die 50 to a wafer 70. The wafer 70 has packaging regions 100A, 100B, each of which includes a device, such as an interposer, formed therein. In FIGS. 11A to 12D , the packaging regions 100A, 100B are singulated to form integrated circuit packages 100, each of which includes a singulated portion of the wafer 70 (e.g., the interposer 140) and an integrated circuit die 50 bonded to the singulated portion of the wafer 70. In FIGS. 13A to 13B , the integrated circuit package 100 is then mounted to a packaging substrate 200.

Referring first to FIG. 5 , a wafer 70 is shown. Wafer 70 includes devices located in packaging regions 100A, 100B, which will be singulated in scribe regions 98 in subsequent processing to be included in integrated circuit package 100. Scribe region 98 is disposed between packaging regions 100A, 100B. The devices formed in wafer 70 may be interposers, integrated circuit dies, etc. Wafer 70 includes substrate 72, interconnect structure 74, bonding pads 76, insulating bonding layer 78, sealing ring 80 (including sealing rings 80A and 80B), and conductive vias 82.

Substrate 72 may be a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. Substrate 72 may include semiconductor materials such as silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Substrate 72 may be doped or undoped. In embodiments where a passive interposer is formed in wafer 70, substrate 72 typically does not include active devices therein, but the passive interposer may include passive devices formed in and/or on the front surface (e.g., the surface facing upward) of substrate 72. In embodiments where an active interposer (also referred to as an integrated circuit die) is formed in wafer 70, active devices such as transistors, capacitors, resistors, diodes, and the like may be formed in and/or on the front surface of substrate 72.

The interconnect structure 74 is located above the front surface of the substrate 72 and is used to electrically connect the devices (if any) of the substrate 72. The interconnect structure 74 may include one or more dielectric layers and corresponding metallization patterns located in the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. The metallization pattern may include conductive vias and/or wires to interconnect any devices together and/or to external devices. The metallization pattern may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interconnect structure 74 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

The bonding pad 76 is located at the front side 70F of the wafer 70. The bonding pad 76 can be a conductive column, a pad, etc. for external connection. The bonding pad 76 can be formed of a metal such as copper, aluminum, etc., and the bonding pad 76 can be formed by, for example, plating, etc. In some embodiments, the bonding pad 76 can be electrically connected to the conductive part of the interconnect structure 74 through a conductive via (sometimes referred to as a bonding pad via, not explicitly shown). The wafer also includes a sealing ring 80 (including sealing rings 80A and 80B) located at the periphery of each integrated circuit die 50. Each sealing ring 80 can be arranged to surround the metallization pattern in the interconnect structure 74 of each packaging area 100A, 100B and the ring of the corresponding bonding pad 76 (see, for example, FIG. 6B). The sealing ring 80 can include a bonding pad portion at the same level as the metallization pattern in the interconnect structure 74 (the metallization pattern is all vertically stacked and connected together by, for example, conductive vias) and the bonding pad 76.

As will be explained in more detail later, seal ring 80A is a functional seal ring that will remain in the singulated integrated circuit package 100 (see FIGS. 13A and 13B ) to protect the circuits in pads 76 and interconnect structures 74. Seal ring 80B (also referred to as dummy seal ring 80B or virtual seal ring 80B) surrounds seal ring 80A, and seal ring 80B can mark an area in scribe line area 98 that is removed during a subsequent singulation process (see FIGS. 11A to 12D ) after bonding the integrated circuit die to wafer 70. By removing excess portions of wafer 70 (e.g., as marked by seal rings 80A and 80B), the resulting interposer can be free of excess overhang, which advantageously reduces stress in the resulting integrated circuit package. As such, in a top view, wafer 70 can include no metallization patterns, bond pads 76, or conductive vias 82 outside the footprint of seal ring 80A. The size and location of seal ring 80 (and the resulting area removed by singulation) may be defined in design rules corresponding to a layout file for wafer 70 such that no active circuitry is disposed outside of seal ring 80A.

The bonding pad 76 can be arranged in the insulating bonding layer 78 at the front side 70F of the wafer 70. The insulating bonding layer 78 can be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, etc. The insulating bonding layer 78 can be deposited on the interconnect structure, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The material of the insulating bonding layer 78 can be the same or different from the insulating bonding layer 58. For example, in a specific embodiment, one of the insulating bonding layers 58/78 is made of silicon oxide, and the other of the insulating bonding layers 58/78 is made of silicon oxynitride. Other combinations are also possible. The bonding pad 76 can be formed in the insulating bonding layer 78 using, for example, a damascene process, and a planarization process (e.g., chemical mechanical polishing (CMP), etc.) can be performed so that the top surfaces of the bonding pad 76 and the insulating bonding layer 78 are coplanar (within process variations) and exposed at the front side 70F of the wafer 70.

Conductive via 82 extends into substrate 72 and/or interconnect structure 74. Conductive via 82 is electrically coupled to the metallization pattern of interconnect structure 74. Conductive via 82 is sometimes also referred to as TSV. As an example of forming conductive via 82, a groove can be formed in interconnect structure 74 and/or substrate 72 by, for example, etching, milling, laser technology, combinations thereof, etc. A thin dielectric material can be formed in the groove, such as by using an oxidation technique. A thin barrier layer can be conformally deposited in the opening by, for example, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer can be formed of oxides, nitrides, carbides, combinations thereof, etc. A conductive material can be deposited over the barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layer are removed from the surface of interconnect structure 74 or substrate 72 by, for example, CMP. The remaining portions of the barrier layer and the conductive material form conductive vias 82 .

In FIGS. 6A and 6B , an integrated circuit die 50 is bonded to a wafer 70. FIG. 6A shows a cross-sectional view, and FIG. 6B shows a top view of a single package area (e.g., package area 100A or 100B). The cross-sectional view of FIG. 6A is taken along line Y-Y' of FIG. 6B. In this embodiment, the integrated circuit die 50 includes a plurality of integrated circuit dies 50A, 50B placed in each of the package areas 100A, 100B. Each of the integrated circuit dies 50A, 50B may have a single function (e.g., a logic device, a memory device, etc.), or may have multiple functions (e.g., SoC). Although two integrated circuit dies 50 are shown in each package area 100A, 100B, any number of integrated circuit dies 50 may be bonded in each package area 100A, 100B. In another embodiment, a single integrated circuit die 50 is bonded in each package area 100A, 100B. The integrated circuit dies 50 in each package region 100A, 100B may be the same size (having the same footprint and height), or they may be different sizes (having different footprints and/or heights).

The integrated circuit die 50 and the wafer 70 are directly bonded in a face-to-face manner by dielectric-to-dielectric bonding and metal-to-metal bonding processes (sometimes referred to as hybrid bonding) so that the front side 50F of the integrated circuit die 50 is bonded to the front side 70F of the wafer 70. Specifically, the insulating bonding layer 58 of the integrated circuit die 50 is bonded to the insulating bonding layer 78 of the wafer 70 by dielectric-to-dielectric bonding without using any adhesive material (e.g., die attach film), and the bonding pad 56 of the integrated circuit die 50 is bonded to the bonding pad 76 of the wafer 70 by metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the integrated circuit die 50 against the wafer 70. The pre-bonding is performed at a low temperature, such as room temperature, such as at a temperature in the range of about 15°C to about 30°C. The bonding strength of the insulating bonding layers 58, 78 is then improved in a subsequent annealing step, in which the insulating bonding layers 58, 78 are annealed at a high temperature, such as at a temperature in the range of about 100°C to about 450°C. After annealing, a bond, such as a covalent bond, is formed to bond the insulating bonding layers 58, 78. The bonding pads 56, 76 are connected to each other in a one-to-one correspondence. The bonding pads 56, 76 may be in physical contact after pre-bonding, or may expand during annealing to make physical contact. In addition, during annealing, the materials (e.g., copper) of the bonding pads 56, 76 are mixed, so that a metal-to-metal bond is also formed. Therefore, the resulting bond between the integrated circuit die 50 and the wafer 70 is a hybrid bond, which includes both a dielectric-to-dielectric bond and a metal-to-metal bond.

In the illustrated embodiment where the integrated circuit die 50 includes a platform 62', a gap can be set in the peripheral area of the integrated circuit die 50 between the insulating bonding layers 58, 78. For example, the sidewalls of the insulating bonding layer 58 can be laterally offset from the outer sidewalls of the semiconductor substrate 52, which creates a gap in the bonding structure. The insulating bonding layers 58, 78 can remain non-contacting and non-bonded at the periphery of the integrated circuit die 50. These gaps allow the subsequently formed sealant to be filled between the insulating bonding layers 58, 78 to improve adhesion, reduce stress, and reduce delamination defects. In other embodiments where the platform 62' is omitted (see Figures 7D and 13B), the gap can also be omitted, and the insulating bonding layers 58, 78 can be in physical contact at the periphery of the integrated circuit die 50.

As shown, the seal ring 80A can be disposed directly below the integrated circuit die 50 in each packaging area 100A, 100B and overlap the integrated circuit die 50. For example, in the top view provided in FIG. 6B, each seal ring 80A can be disposed within the footprint of the sacrificial area 46, and the seal ring 80A can overlap each integrated circuit die 50A, 50B. In some embodiments, in the top view, the lateral distance L2 measured from the seal ring 60 to the seal ring 80A can be 0 or greater. When the lateral distance L2 is equal to 0, the seal ring 80A can at least partially overlap the seal ring 60 (see, for example, the embodiment of FIG. 7C). Although FIG. 6B shows that the lateral distance L2 between the sealing ring 80A and the sealing ring 60 of the integrated circuit die 50A is equal to the lateral distance L2 between the sealing ring 80A and the sealing ring 60 of the integrated circuit die 50B, in other embodiments, the lateral distance between the sealing ring 80A and the sealing ring 60 of the integrated circuit die 50A may be different from the lateral distance between the sealing ring 80A and the sealing ring 60 of the integrated circuit die 50B.

In addition, the seal ring 80B can be disposed outside the footprint of the integrated circuit die 50. For example, in a top view, the seal ring 80B can surround the seal ring 80A and all integrated circuit dies 50 in the package regions 100A, 100B. In a subsequent process, a singulation process can be performed between the seal rings 80A and 80B through the sacrificial region 46 of the integrated circuit die 50, and the seal ring 80B can be removed. In this way, the excess overhang of the resulting interposer can be reduced, which reduces stress in the resulting package.

In FIGS. 7A to 7D , a sealant 110 is formed on various components. The sealant 110 is formed of a molding material or a molding compound. The molding material includes a polymer material and optionally includes a filler (e.g., filler 110 ', see FIGS. 7B to 7D ). The polymer material may be an epoxy resin or the like. The filler is formed of a material that provides mechanical strength and thermal dispersion to the sealant 110, such as particles of silicon dioxide (SiO ₂ ). The molding material (including the polymer material and/or the filler) may be formed by compression molding, transfer molding, or the like. The sealant 110 may be formed over the front side 70F of the wafer 70 so that the integrated circuit die 50 is buried or covered. The sealant 110 is then cured. A planarization process may be performed to planarize the top surface of the sealant 110 and the integrated circuit die 50. The planarization process may be CMP, etch back, a combination thereof, or the like. In the illustrated embodiment, the integrated circuit die 50 is exposed by planarization of the encapsulant 110 so that the top surfaces of the integrated circuit die 50 and the encapsulant 110 are substantially flush after planarization (within process variations). Planarization may remove portions of the semiconductor substrate 52. The encapsulant 110 surrounds and protects the integrated circuit die 50.

7B to 7D illustrate detailed cross-sectional views of region 100' of FIG. 7A according to various embodiments. In each embodiment of FIG. 7B to 7D, the integrated circuit die 50 overlaps the seal ring 80A, and the seal ring 80B is disposed outside the region overlapped by the integrated circuit die 50. FIG. 7B and FIG. 7C illustrate an embodiment in which the platform 62' is included in the integrated circuit die 50. Specifically, FIG. 7B illustrates an embodiment in which the seal ring 80A is laterally offset from the seal ring 60, and FIG. 7C illustrates an embodiment in which the seal ring 60 overlaps and is aligned with the seal ring 80A. In the embodiments of FIG. 7B and FIG. 7C, the sealant 110 extends between the insulating bonding layers 58, 78 in the platform 62' along a line X-X' perpendicular to the main surface of the substrate 52, 72. In this way, the sealant 110 can be used as an adhesive to improve the adhesion between the insulating bonding layers 58, 78 and reduce delamination defects. The sealant 110 can extend laterally from the sidewalls of the insulating bonding layer 58 to the outer sidewalls of the semiconductor substrate 52. In some embodiments, a filler 110′ of sealant 110 may also be disposed between insulating bonding layers 58, 78 along line X-X′. Additionally, because the size of mesa 62′ is relatively small, voids 112 (e.g., internal seams and/or air gaps) may be formed in sealant 110 between insulating bonding layers 58, 78 along line X-X′ as part of the fill process of dispensing sealant 110 into mesa 62′. Specific to the embodiment of FIG. 7B , seal ring 80A may overlap portions of sealant 110 between insulating bonding layers 58, 78 and mesa 62′.

In the embodiments of FIGS. 7B and 7C , the size of the sealant 110 between the insulating bonding layers 58 and 78 corresponds to the size of the platform 62 ′. For example, the thickness T1 of the sealant 110 between the insulating bonding layers 58 and 78 may be equal to the depth D1 of the groove 62/platform 62 ′ (see FIG. 2 ), and the thickness T1 may be In the embodiment of the present invention, the size of the sealant 110 between the insulating bonding layers 58 and 78 can be within the range of 1 μm to 2.5 μm. In addition, the lateral dimension L3 of the sealant 110 between the insulating bonding layers 58 and 78 can be within the range of 1 μm to 150 μm. It has been observed that when the size of the sealant 110 between the insulating bonding layers 58 and 78 is within the above range, the adhesion between the integrated circuit die 50 and the wafer 70 can be improved, and stress accumulation and delamination defects can be reduced. Accordingly, a semiconductor package with reduced defects, improved reliability and improved yield can be achieved.

In some embodiments, as shown in FIG. 7D , platform 62′ is optional and platform 62′ may be omitted. In such embodiments, encapsulant 110 may not extend between insulating bonding layers 58, 78 along line X-X′. For example, at the periphery of integrated circuit die 50, insulating layer 58 may be in physical contact with insulating layer 78 without any intervening encapsulant 110. Although FIG. 7D shows an embodiment in which seal ring 80A is laterally offset from seal ring 60, seal ring 80A may also overlap seal ring 60 in a manner similar to the embodiment of FIG. 7C , but without platform 62′.

It should be understood that each of the embodiments of Figures 7B to 7D can be implemented in a single integrated circuit package. For example, multiple integrated circuit dies 50 are bonded to the wafer 70 in each packaging area 100A, 100B. Accordingly, the first integrated circuit die 50 (e.g., die 50A) can have a first configuration according to any of the embodiments of Figures 7B to 7D, and the second integrated circuit die 50 (e.g., die 50B) can have a second configuration according to any of the embodiments of Figures 7B to 7D. The second configuration of the second integrated circuit die (e.g., die 50B) can be the same or different from the first configuration of the first integrated circuit die 50 (e.g., die 50A).

In FIG8 , the intermediate structure is flipped over (not shown) to prepare for processing the back side 70B of the substrate 72. The intermediate structure can be placed on a carrier substrate 114 or other suitable support structure for subsequent processing. For example, the carrier substrate 114 can be attached to the encapsulant 110 and the integrated circuit die 50 by a release layer. The release layer can be formed of a polymer-based material, and after processing, the release layer can be removed from the structure together with the carrier substrate 114. In some embodiments, the carrier substrate 114 is a substrate such as a bulk semiconductor or a glass substrate. In some embodiments, the release layer is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating.

9, the substrate 72 is thinned to expose the conductive via 82. The exposure of the conductive via 82 can be accomplished by a thinning process, such as a grinding process, CMP, etch back, a combination thereof, etc. Then, an insulating layer 116 is formed on the back side 70B of the substrate 72, over the conductive via 82. In some embodiments, the insulating layer 116 is formed of a silicon-containing insulator, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the insulating layer 116 can be formed by a suitable deposition method, such as by spin coating, CVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), etc.

In FIG. 10 , an under bump metal (UBM) 132 is formed on the insulating layer 116 and extends through the insulating layer 116. The UBM 132 can be electrically connected to the conductive via 82. As an example of forming the UBM 132, an opening can be patterned in the insulating layer 116 to expose the conductive via 82. In some embodiments, the patterned opening can be achieved by a combination of photolithography and etching. In other embodiments, the opening in the insulating layer 116 can be achieved by, for example, laser drilling. A seed layer (not shown) is formed in the opening (such as above the exposed surface of the insulating layer 116 and the conductive via 82). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM 132. Patterning forms an opening through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating or chemical plating). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the conductive material and the seed layer forms the UBM 132.

In addition, a conductive connector 136 is formed on the UBM 132. The conductive connector 136 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 136 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 136 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be performed so that the material is formed into a desired bump shape. In another embodiment, the conductive connector 136 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal cap layer may be formed by a plating process.

10 , carrier debonding is performed to separate (debond) carrier substrate 114 from encapsulant 110 and integrated circuit die 50. In embodiments where carrier substrate 114 is attached to encapsulant 110 and integrated circuit die 50 by a release layer, debonding includes projecting light, such as laser or ultraviolet (UV), onto the release layer so that the release layer decomposes under the heat of the light and carrier substrate 114 can be removed. The structure is then flipped over and placed on tape (not shown).

Subsequently, a singulation process is performed by cutting along, for example, the scribe line region 98 between the packaging regions 100A and 100B. Figures 11A to 12D illustrate the singulation process according to various embodiments. Referring to Figures 11A and 11B, a slotting process is performed to define a groove 118 in the scribe line region 98 between the packaging regions 100A and 100B. Figure 11B shows a detailed view of the region 100' in Figure 11A. In some embodiments, the slotting process may be a laser slotting process, a plasma cutting process (e.g., a deep plasma cutting process), etc. The slotting process may be performed through the backside 70B region of the wafer 70 between the sealing rings 80A and 80B. For example, the slotting process may define a groove 118 extending through the insulating layer 116 (see Figure 11A, not shown in Figure 11B), through the substrate 72, through the interconnect structure 74, through the bonding layer 78, through the sealant 110, and into the sacrificial region 46 of the integrated circuit die 50. Specifically, the slotting process can remove portions of the insulating bonding layer 58 (if present, see FIG. 7D ), the interconnect structure 54, and the substrate 52 in the sacrificial region 46 at the periphery of the integrated circuit die 50. In some embodiments, the slotting process can remove the sealing ring 80B. In other embodiments, the slotting process can be controlled between the sealing rings 80A, 80B so that the groove 118 is disposed between the sealing rings 80A, 80B. In such an embodiment, the sealing ring 80B can remain in the wafer 70. Although FIG. 11B shows a detailed view corresponding to the embodiment of FIG. 7B , it should be understood that in other embodiments, the slotting process discussed can also be applied to the embodiments of FIG. 7C or FIG. 7D .

Then, in FIGS. 12A to 12D , a sawing process is performed to completely separate the interposers 140 from each other and from the wafer 70 to form singulated integrated circuit packages 100 . FIGS. 12B to 12D show detailed views of the region 100 ′ in FIG. 12A . FIG. 12B corresponds to the embodiment of FIG. 7B ; FIG. 12C corresponds to the embodiment of FIG. 7C ; and FIG. 12D corresponds to the embodiment of FIG. 7D , each as described above. It should be understood that each of the embodiments of FIGS. 12B to 12D can be implemented in a single integrated circuit package 100 . For example, a plurality of integrated circuit dies 50 are bonded to the interposer 140 in each integrated circuit package 100 . Accordingly, the first integrated circuit die 50 (e.g., die 50A) can have a first configuration according to any of the embodiments of FIGS. 12B to 12D , and the second integrated circuit die 50 (e.g., die 50B) can have a second configuration according to any of the embodiments of FIGS. 12B to 12D . The second configuration of the second integrated circuit die (eg, die 50B) may be the same as or different from the first configuration of the first integrated circuit die 50 (eg, die 50A).

The sawing process can be performed through the grooves 118 in the scribe area 98. In some embodiments, the sawing process is a mechanical process using a saw blade, which is placed in the grooves 118 to saw through the remaining semiconductor substrate 52 exposed by the grooves 118. The singulation process singulates the package areas 100A and 100B from each other. The resulting singulated integrated circuit package 100 comes from one of the package areas 100A and 100B. The singulation process forms an interposer 140 from the singulated portions of the wafer 70 and the insulating layer 116. The interposer 140 can be a passive interposer without active devices (e.g., transistors, diodes, etc.), or an active interposer in which active devices are disposed. Each integrated circuit package 100 includes an interposer 140. As a result of the singulation process, the integrated circuit die 50 can overhang and extend laterally beyond the outer sidewalls of the interposer 140 (see Figures 12B to 12D). In some embodiments, the outer sidewalls of the interposer 140 and the integrated circuit die 50 may be laterally co-terminal (within process variations).

Because the singulation process is performed through the integrated circuit die 50, the encapsulant 110 around the periphery of the integrated circuit die 50 can be removed. In addition, excess portions of the wafer 70 (e.g., the area directly below the encapsulant 110) can also be removed. For example, the outer sidewalls of the integrated circuit package 100 can expose the sidewalls of the integrated circuit die 50 and the sidewalls of the interposer 140. In some embodiments (see Figures 12B and 12C), the encapsulant 110 in the platform 62' can be exposed at the outer sidewalls of the integrated circuit package 100. In an embodiment in which the platform 62' is omitted (see Figure 12D), the integrated circuit package 100 may include one or more outer sidewalls that do not expose the encapsulant 110. In various embodiments, the sidewalls of the integrated circuit die 50 at the outer sidewalls of the integrated circuit package 100 may be free of any encapsulant 110 disposed thereon.

In this manner, the interposer 140 can be free of excess overhang. By reducing or eliminating excess overhang in the interposer 140, stress in the singulated integrated circuit package 100 can be relieved. For example, during operation of the integrated circuit package 100, different operating temperatures can cause undesirable bending, particularly in the overhang region of the interposer 140 (e.g., the region of the interposer 140 that extends beyond the integrated circuit die 50). By removing excess overhang in the interposer 140, the undesirable bending can be significantly reduced or even eliminated, thereby reducing stress in the integrated circuit package 100. It has been observed that in packages produced by the embodiment singulation method, stress can be reduced by up to 84% under high temperature operating conditions, and stress can be reduced by up to 97% under low temperature operating conditions.

In FIGS. 13A and 13B , the integrated circuit package 100 is then flipped over and attached to the package substrate 200 using the conductive connector 136 . FIG. 13A shows an embodiment including the platform 62 ', and FIG. 13B shows an embodiment excluding the platform 62 '. The package substrate 200 includes a substrate core 202, which can be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate core 202 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 202 is an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resins, or alternatively, other printed circuit board (PCB) materials or films.Build-up films such as Ajinomoto built-up film (ABF) or other laminates may be used for the substrate core 202 .

The substrate core 202 may include active devices and passive devices (not shown). Devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements of the design of the system. Any suitable method may be used to form the devices.

The substrate core 202 may also include metallization layers and vias (not shown) and bonding pads 204 located above the metallization layers and vias. The metallization layers may be formed above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) (wherein the vias interconnect the conductive material layers), and the metallization layers may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 202 is substantially free of active and passive devices.

The conductive connectors 136 are reflowed to attach the UBM 132 to the bonding pads 204. The conductive connectors 136 connect the integrated circuit package 100 (including the metallization pattern of the interconnect structure 74) to the package substrate 200 (including the metallization layer in the substrate core 202). Thus, the package substrate 200 is electrically connected to the integrated circuit die 50. In some embodiments, a passive device (e.g., a surface mount device (SMD), not shown) may be attached to the integrated circuit package 100 (e.g., bonded to the UBM 132) before being mounted on the package substrate 200. In such embodiments, the passive device may be bonded to the same surface of the integrated circuit package 100 as the conductive connectors 136. In some embodiments, the passive device (e.g., an SMD, not shown) may be attached to the package substrate 200, for example, to the bonding pads 204.

In some embodiments, an underfill 206 is formed between the integrated circuit package 100 and the package substrate 200 around the conductive connector 136 and the UBM 132. The underfill 206 can be formed by a capillary flow process after the integrated circuit package 100 is attached, or can be formed by a suitable deposition method before the integrated circuit package 100 is attached. The underfill 206 can be a continuous material extending from the package substrate 200 to the interposer 140 (e.g., the insulating layer 116). The underfill 206 can also extend along the sidewalls of the integrated circuit die 50 and physically contact the sidewalls of the integrated circuit die 50. In an embodiment including a platform 62' (Figure 13A), the underfill can also physically contact the sidewalls of the encapsulant 110 disposed between the insulating bonding layers 58, 78.

Optionally, a heat sink 208 is attached to the integrated circuit package 100. The heat sink 208 may be formed of a material having high thermal conductivity, such as steel, stainless steel, copper, or the like, or a combination thereof. The heat sink 208 may include a thermal cover 208A and a ring 208B, and the heat sink 208 may be attached to the integrated circuit package 100 by an adhesive or a thermal interface material (TIM). In some embodiments, in a top view, the ring 208B may surround the integrated circuit package 100. The heat sink 208 protects the integrated circuit package 100 and forms a thermal path to conduct heat from various components of the integrated circuit package 100 (e.g., the integrated circuit die 50). The heat sink 208 is in contact with the integrated circuit die 50 and the encapsulant 110.

According to various embodiments, an integrated circuit package is formed by directly bonding an integrated circuit die to a wafer containing another device (e.g., an interposer), and a molding compound is dispensed around the integrated circuit die as a sealant. Then, a singulation process is performed by cutting through the interposer and the integrated circuit die. For example, sacrificial areas along the periphery of the integrated circuit die and sealing rings of the interposer may be included in the device design so that no functional circuits are formed in these sacrificial areas. The singulation process may then be performed to cut through the sacrificial areas and between the sealing rings of the interposer. In some embodiments, the sacrificial area of the interposer may be defined by one or more sealing rings, and at least one sealing ring is disposed directly below the integrated circuit die.

In this manner, excess overhang of the molding compound and interposer around the periphery of the integrated circuit die is removed, advantageously reducing stress in the resulting package. By reducing or eliminating excess overhang in the bottom interposer, stress in the bonded package can be relieved (e.g., reducing undesirable bowing). It has been observed that in packages produced by embodiment singulation methods, stress can be reduced by up to 84% under high temperature operating conditions, and stress can be reduced by up to 97% under low temperature operating conditions.

In some embodiments, the package includes an integrated circuit die and an interposer. The integrated circuit die includes a first insulating bonding layer and a first semiconductor substrate. The interposer includes a second insulating bonding layer, a first sealing ring, and a second semiconductor substrate, wherein the second insulating bonding layer is directly bonded to the first insulating bonding layer with a dielectric-to-dielectric bond. The integrated circuit die overlaps with the first sealing ring, and wherein the sidewall of the integrated circuit die is exposed at the outer sidewall of the package. In some embodiments, the integrated circuit die also includes a second sealing ring, and wherein the first sealing ring is laterally offset from the second sealing ring. In some embodiments, the lateral distance between the first sealing ring and the outer sidewall of the package is less than the lateral distance between the second sealing ring and the outer sidewall of the package. In some embodiments, the integrated circuit die also includes a second sealing ring, and wherein the second sealing ring overlaps with the first sealing ring. In some embodiments, the package also includes a sealant located between the first insulating bonding layer and the second insulating bonding layer. In some embodiments, the sidewall of the sealant disposed between the first insulating bonding layer and the second insulating bonding layer is exposed at the outer sidewall of the package. In some embodiments, the integrated circuit die extends laterally beyond the sidewall of the interposer exposed at the outer sidewall of the package. In some embodiments, the interposer is bonded to the package substrate, wherein an underfill is disposed between the package and the package substrate, and wherein the underfill directly contacts a sidewall of the integrated circuit die.

In some embodiments, a method includes bonding a first integrated circuit die to an interposer, wherein the interposer includes a first seal ring and a second seal ring; dispensing an encapsulant around the first integrated circuit die; after dispensing the encapsulant, performing a singulation process on the interposer in an area between the first seal ring and the second seal ring to form a singulated package. The singulation process removes a portion of the first integrated circuit die, a first portion of the encapsulant on a sidewall of the first integrated circuit die, and a portion of the interposer between the first seal ring and the second seal ring. In some embodiments, the first integrated circuit die overlaps the first seal ring. In some embodiments, the method further includes bonding a second integrated circuit die to the interposer, wherein the second integrated circuit die overlaps the first seal ring, wherein dispensing the encapsulant includes dispensing a second portion of the encapsulant between the first integrated circuit die and the second integrated circuit die, and wherein after the singulation process, the second portion of the encapsulant between the first integrated circuit die and the second integrated circuit die remains. In some embodiments, the encapsulant overlaps the second seal ring. In some embodiments, the first integrated circuit die includes a third seal ring, and wherein the third seal ring defines a boundary of a sacrificial region, and wherein the portion of the first integrated circuit die removed by the singulation process is located in the sacrificial region. In some embodiments, the method further includes bonding the singulated package to a substrate; and dispensing an underfill between the singulated package and the substrate, wherein the underfill physically contacts a sidewall of the interposer and a sidewall of the first integrated circuit die. In some embodiments, the singulation process includes a slotting process that forms a groove extending through the interposer and into the semiconductor substrate of the first integrated circuit die, and a sawing process that saws through the remaining portion of the semiconductor substrate of the first integrated circuit die exposed by the groove. In some embodiments, the slotting process removes the second seal ring.

In some embodiments, a method includes bonding an integrated circuit die to an interposer, wherein the integrated circuit die includes a first sealing ring and a sacrificial area between the first sealing ring and an outer sidewall of the integrated circuit die; dispensing a sealant around the integrated circuit die; and performing a singulation process to form a singulated package. The singulation process is performed through the interposer and the sacrificial area of the integrated circuit die, and after the singulation process, the integrated circuit die is exposed at the outer sidewall of the singulated package. In some embodiments, the interposer includes a second sealing ring, and wherein the integrated circuit die overlaps the second sealing ring. In some embodiments, the first sealing ring overlaps the second sealing ring. In some embodiments, the interposer also includes a third sealing ring, and wherein the singulation process is performed in the area between the second sealing ring and the third sealing ring.

The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A package, comprising:

an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate; and

An interposer comprising a second insulating bond layer, a first seal ring, and a second semiconductor substrate, wherein the second insulating bond layer is directly bonded to the first insulating bond layer with a dielectric-to-dielectric bond, and wherein the integrated circuit die overlaps the first seal ring, and wherein a sidewall of the integrated circuit die is exposed at an outer sidewall of the package.

2. The package of claim 1, wherein the integrated circuit die further comprises a second seal ring, and wherein the first seal ring is laterally offset from the second seal ring.

3. The package of claim 2, wherein a lateral distance between the first seal ring and the outer sidewall of the package is less than a lateral distance between the second seal ring and the outer sidewall of the package.

4. The package of claim 1, wherein the integrated circuit die further comprises a second seal ring, and wherein the second seal ring overlaps the first seal ring.

5. The package of claim 1, further comprising a sealant between the first and second insulating bond layers.

6. The package of claim 5, wherein a sidewall of the sealant disposed between the first and second insulating bonding layers is exposed at the outer sidewall of the package.

7. The package of claim 1, wherein the integrated circuit die extends laterally beyond a sidewall of the interposer exposed at the outer sidewall of the package.

8. The package of claim 1, wherein the interposer is bonded to a package substrate, wherein an underfill is disposed between the package and the package substrate, and wherein the underfill directly contacts the sidewalls of the integrated circuit die.

9. A method of forming a package, comprising:

bonding the first integrated circuit die to an interposer, wherein the interposer includes a first seal ring and a second seal ring;

Dispensing an encapsulant around the first integrated circuit die; and

After dispensing the encapsulant, a singulation process is performed on the interposer in a region between the first and second seal rings to form singulated packages, wherein the singulation process removes portions of the first integrated circuit die, first portions of the encapsulant on sidewalls of the first integrated circuit die, and portions of the interposer between the first and second seal rings.

10. A method, comprising:

bonding an integrated circuit die to an interposer, wherein the integrated circuit die includes a first seal ring and a sacrificial region between the first seal ring and an outer sidewall of the integrated circuit die;

dispensing an encapsulant around the integrated circuit die; and

A singulation process is performed to form singulated packages, wherein the singulation process is performed through the interposer and the sacrificial areas of the integrated circuit die, and wherein after the singulation process, the integrated circuit die is exposed at an outer sidewall of the singulated packages.