CN118782119B - Memory and operation method thereof and storage system - Google Patents

Abstract

The application provides a memory and an operation method of the memory, wherein the operation method comprises the steps of resetting a calibrated memory unit in a memory array by a first current; and performing weak reset operation on at least one adjacent memory cell adjacent to the nominal memory cell in the memory array with a second current, the second current being less than the first current. The operation method and the memory can perform weak reset operation according to the weak reset operation requirement. Through the weak reset operation method and the memory, the thermal interference to the adjacent memory cells during the reset operation can be relieved, and the weak reset operation can be performed according to the requirement, so that the operation efficiency of the memory can be further improved besides the thermal interference prevention effect.

Description

Memory, operation method thereof and memory system

Technical Field

The present application relates generally to the field of electronic devices, and more particularly to a memory and a method of operating the same, and a memory system.

Background

The phase change memory (PHASE CHANGE Random Access Memory, PCM) is widely focused on as a candidate of the next generation nonvolatile semiconductor memory due to the advantages of high-speed reading, high erasable times, non-volatility, small element size, low power consumption, strong shock resistance, radiation resistance, and the like, particularly 3D PCM.

However, the write disturb is always a major problem of the 3D PCM, and especially when performing a write operation of writing 0 into a target memory cell, the heat disturb is often caused to an adjacent memory cell due to the high melting point temperature, and the problem of the confusion of the stored data is caused. While there are many remedies for this problem in the industry, there is still no good solution.

Disclosure of Invention

The application aims to provide a memory, an operation method thereof and a memory system, and aims to solve the problem caused by thermal interference.

In a first aspect, the present application provides a method of operating a memory, the method comprising:

Performing a reset operation on a calibrated memory cell in the memory array with a first current, and

And performing weak reset operation on at least one adjacent memory cell adjacent to the calibrated memory cell in the memory array by using a second current, wherein the second current is smaller than the first current.

In some embodiments, the calibration memory cell connects an mth word line and an nth bit line in the memory array, the adjacent memory cell is connected to one of the mth-1 to m+1 word lines, and one of the nth-1 to n+1 bit lines, the first current passes through the nth bit line, and the second current passes through one of the nth-1 to n+1 bit lines.

In some embodiments, the method further comprises a weak reset operation requirement determination, wherein the weak reset operation is performed only when the weak reset operation is required.

In some embodiments, the weak reset operation requirement determination includes a neighboring cell data determination, configured to determine whether data stored in the neighboring cell is reset data, if so, perform the weak reset operation after performing the reset operation, if not, not perform the weak reset operation, and the neighboring cell data determination step may be performed before or after performing the reset operation.

In some embodiments, the weak reset operation requirement determination includes a weak reset trigger determination, configured to determine, before performing the reset operation, whether the calibration memory cell is located in a reset interference possible area, if so, perform the adjacent memory cell data determination before or after performing the reset operation, and if not, not perform the adjacent memory cell data determination and the weak reset operation.

In some embodiments, the step of determining whether the dummy memory cell is located in a reset disturbance capable region includes determining whether the dummy memory cell is located in a region within a drive bias influence distance, in a data error capable region, or in a top stack or a bottom stack of the memory array.

In some embodiments, the weak reset operation requirement determination includes a calibration memory cell operation determination configured to determine whether the calibration memory cell is to be subjected to a reset operation, if so, performing the weak reset operation after the reset operation, and if not, not performing the weak reset operation.

In some embodiments, the reset operation includes applying a first voltage to an mth word line, applying a second voltage to an nth bit line, and the weak reset operation includes applying the first voltage to one of the m-1 to m+1 th word lines to which the adjacent memory cell is connected, and applying the second voltage to one of the n-1 to n+1 th bit lines to which the adjacent memory cell is connected.

In a second aspect, the present application provides a memory comprising:

A memory array comprising a calibration memory cell and at least one adjacent memory cell adjacent to the calibration memory cell, and

And performing a weak reset operation on the at least one adjacent memory cell with a second current, the second current being less than the first current.

In some embodiments, the calibration memory cell connects an mth word line and an nth bit line in the memory array, the adjacent memory cell is connected to one of the mth-1 to m+1 word lines, and one of the nth-1 to n+1 bit lines, the first current passes through the nth bit line, and the second current passes through one of the nth-1 to n+1 bit lines.

In some embodiments, the memory further includes a first data determining module, configured to perform data determination on an adjacent memory cell, and determine whether the data stored in the adjacent memory cell is reset data, if so, send a first weak reset execution signal to enable the peripheral circuit to perform the weak reset operation after performing the reset operation, and if not, not send the first weak reset execution signal to enable the peripheral circuit not to perform the weak reset operation.

In some embodiments, the memory further includes a weak reset trigger module configured to determine whether the calibration memory cell is located in a reset disturbance possible area, if so, send a weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination or the weak reset operation, and if not, not send the weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination and the weak reset operation.

In some embodiments, the memory further includes a second data determining module configured to determine whether the calibration memory cell is to be reset, if so, send a second weak reset execution signal to enable the peripheral circuit to perform the weak reset operation, and if not, send no second weak reset execution signal to enable the peripheral circuit not to perform the weak reset operation.

In some embodiments, the reset operation of the peripheral circuit further comprises applying a first voltage to an mth word line, applying a second voltage to an nth bit line, and the weak reset operation further comprises applying the first voltage to one of the m-1 to m+1 word lines to which the adjacent memory cell is connected, and applying the second voltage to one of the n-1 to n+1 bit lines to which the adjacent memory cell is connected.

In a third aspect, the present application provides a storage system, which includes the memory described above, and a controller electrically connected to the memory, for controlling the memory, where the first data determination module, the second data determination module, and the weak reset trigger module are respectively and optionally disposed in the peripheral circuit of the memory, or in the controller.

According to the memory, the operation method and the memory system provided by the application, the thermal interference to the adjacent memory units during the reset operation can be relieved, and the weak reset operation can be carried out according to the requirement, so that the operation efficiency of the memory can be further improved besides the thermal interference prevention effect.

Drawings

The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a functional block diagram of a memory provided in accordance with some embodiments of the present application;

FIG. 2 is a schematic diagram of a memory array circuit of a memory provided in accordance with some embodiments of the application;

FIG. 3 is a schematic diagram illustrating the structure and operation of a phase change memory cell according to some embodiments of the present application;

FIG. 4 is a schematic diagram illustrating a reset operation of a phase change memory cell according to some embodiments of the present application;

FIG. 5 is a schematic diagram illustrating the consistency of a phase change memory cell according to some embodiments of the present application after a weak reset operation;

FIGS. 6a and 6b are schematic diagrams illustrating operations of a calibration memory cell and an adjacent memory cell according to some embodiments of the present application;

FIG. 7 is a schematic diagram of the operational steps provided by some embodiments of the present application.

FIG. 8 is a schematic diagram of another operational step provided by some embodiments of the present application.

Fig. 9 is a functional schematic block diagram of a memory provided by some embodiments of the application.

FIG. 10 is a functional schematic block diagram of a memory system provided by some embodiments of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present application.

It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar fashion.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layers may extend over the entire underlying or overlying structure, or may have a range less than the range of the underlying or overlying structure. Further, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layers may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

It should be noted that, the illustrations provided in the embodiments of the application are merely schematic illustrations of the basic concepts of the application, and only the components related to the application are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The directions are expressed herein in terms of Cartesian coordinates, with reference to the substrate, a first direction being a direction perpendicular to the substrate, expressed in terms of "Z", a second direction parallel to the substrate, expressed in terms of "X", and a third direction parallel to the substrate and perpendicular to X, expressed in terms of "Y".

Referring first to fig. 1, fig. 1 is a functional schematic block diagram of a memory according to some embodiments of the present application. The memory 200 generally includes a memory array 10 and peripheral circuitry 20 connected to control the memory array 10.

As shown in fig. 1, the peripheral circuit 20 is connected to the memory array 10, and the peripheral circuit 20 generally includes at least a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a bit line voltage generator 271, a bit line clamp 272, a reference current generator 261, a sense amplifying current comparator 262, and a logic control module 230 connected to the above devices for receiving operation instructions and controlling the above devices.

The row decoder 240 receives a row address signal from a bus (not shown), and decodes the row address signal to select an address word line.

The word line driver 212 is connected to a plurality of word lines WL <0:m >, a word line voltage generator 211, and a row decoder 240. The word line driver 212 receives a row address selection signal and a word line driving voltage, and outputs the word line driving voltage to at least one row of memory cells connected to at least one word line WL < m > of the plurality of word lines WL <0:m > according to the row address selection signal.

The bit line driver 251, the bit line clamp 272, the bit line voltage generator 271, and the column decoder 250 belong to a column driving circuit and are connected as shown in fig. 1. The bit line voltage generator 271 and the column decoder 250 are connected to the logic control module 230 to receive the control of the logic control module 230.

The column decoder 250 receives the column address signal and decodes the column address signal to select the address bit line to which the operation target memory cell is connected. The bit line voltage generator 271 generates a clamp voltage required for each selected bit line. The bit line clamp 272 is connected to the bit line voltage generator 271, receives the clamp voltage, and outputs the set clamp voltage to each corresponding selected bit line.

The bit line driver 251 is connected to a plurality of bit lines, bit line clamps 272, and column decoder 250. The bit line driver 251 receives a bit line voltage and a column address selection signal, and outputs a set clamp bit line voltage to at least one column of memory cells connected to at least one bit line BL < n > of the plurality of bit lines BL <0:n > according to the column address selection signal.

The peripheral circuit 20 also includes a sense amplifier current comparator 262, a reference current generator 261, a data latch (not shown), and the like. Sense amp current comparator 262 is coupled to reference current generator 261 and to a plurality of bit lines BL <0:n > and to data latch 223. The sense amplifier current comparator 262 is configured to compare the read current with the reference current generated by the reference current generator 261, determine the data stored in the selected memory cell, store the data in the data latch 280, and output the data together with the data read by other bit lines to the data bus via the i/o interface 290 for output.

Based on the structural design of the peripheral circuit 20 of the memory described above, operations on the memory may include an erase operation, a read operation, and a program operation.

Referring to fig. 2, fig. 2 is a circuit diagram illustrating an example of a memory array 10 as a memory according to some embodiments of the present application. The memory array 10 includes a plurality of memory cells 11 arranged in an array. The memory cells arranged in the array are arranged in a plurality of rows and a plurality of columns. Each row of memory cells comprises a plurality of memory cells 11 arranged in a row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged in a column direction (i.e., second direction Y). For example, fig. 2 only illustrates three rows and three columns of memory cells each, and in practice the memory will include rows and columns of memory cells depending on its storage capacity. In addition, the memory cell illustrated in fig. 2 is a phase change memory cell 11, and the phase change memory cell 11 includes a phase change memory cell (PCM storage cell) (for distinguishing from the cell, a part of the phase change memory structure is referred to herein as a cell) 111 and a threshold change switch ((Ovonic Threshold Switch, OTS) 112. In the new generation of phase change memory cells, only the selector memory (selector only memory, SOM) is also one of the phase change memories because a chalcogenide is also used.

It should be understood that the memory cells in the memory array may be various kinds of memory cells, such as floating gate (ONO) memory cells, resistive memory cells (RRAM), phase change memory cells (PCM/PCRAM/SOM), etc., and the present application is not limited thereto, but is particularly applicable to phase change memory cells, and thus the phase change memory cells PCM will be exemplified below, but it should be understood that the present application is not limited thereto.

Referring to fig. 3, fig. 3 (a) is a schematic diagram of a memory cell according to some embodiments of the present application, and fig. 3 (b) is a schematic diagram of a reset operation (reset) and a set operation (set) of a memory cell according to some embodiments of the present application.

As shown in fig. 3 (a), some embodiments of the present application provide a schematic structure of a phase change memory cell. Taking fig. 3 (a) as an example, some embodiments of the present application provide a phase change memory cell including a top electrode 111a and a bottom electrode 111b sequentially disposed in a longitudinal direction perpendicular to the bottom electrode, a dielectric layer 111c, a heater 111d disposed in the dielectric layer, and a phase change material layer 111e.

The phase change material layer 111e includes one or more phase change materials such as germanium-antimony-tellurium (Ge-Sb-Te, GST) based materials, an example of which may be Ge2Sb2Te5. The relatively large number of phase change materials currently used by various institutions are chalcogenides (represented by intel) and germanium, antimony, tellurium-containing composite materials (GST), such as Ge2Sb2Te5. Phase change materials can have a large resistivity contrast between different phases (e.g., crystalline and amorphous). For example, a phase change material may exhibit a relatively low resistivity in the crystalline phase, but a relatively high resistivity in the amorphous phase, and the resistivity of the phase change material in the amorphous phase may be hundreds to thousands of times higher than the resistivity in the crystalline phase. The phase change material may be switched between different phase states when heated to enable writing of information (data), including set and reset in this embodiment, the heater 111d may be used to heat the phase change material layer 111e to change the phase state (phase) of the phase change material layer 111 e.

The heater 111d may be made of a material having an appropriate resistance, such as a metal material, to generate enough joule heat to heat the phase change material layer 111 e. For example, the heater 111d may be made of inconel.

The material of the dielectric layer 111c may be silicon dioxide or silicon nitride. The heater 111d is disposed in a via hole formed in the dielectric layer 111c, and the dielectric layer 111c surrounds the heater 111d to prevent heat transfer between different cells in the phase change memory to avoid thermal interference.

The top electrode 111a and the bottom electrode 111b are disposed opposite to each other, and the positions of the top electrode and the bottom electrode can be interchanged, and the top electrode and the bottom electrode overlap with each other in cooperation with an outer bit line and a word line (not numbered), thereby forming a 3D phase change memory.

Fig. 3 (b) shows the operation principle and operation schematic diagram of the phase change memory. The basic structure of the phase change memory (PHASE CHANGE Random Access Memory, abbreviated as PCRAM) is shown in fig. 3 (a), and the basic storage principle of the phase change memory is that voltage or current pulse signals with different widths and heights are applied to the phase change memory cells, so that the phase change material is subjected to physical phase change, i.e., reversible phase change is performed between crystalline state (low resistance state) and amorphous state (high resistance state), so as to implement operations of writing ("1") and erasing ("0") of information, or write information, including writing 1 (set) or 0 (reset). The interconversion process involves both amorphous to amorphous transformation, referred to as the amorphization process, and crystalline to amorphous transformation, referred to as the crystallization process. The non-destructive reading process then enables accurate reading of the information stored in the device cell by measuring and comparing the resistance difference between the two physical phases. The difference in resistivity of the phase change material between crystalline and amorphous states differs by several orders of magnitude so that it has a high noise margin sufficient to distinguish between the "0" and "1" states.

As shown in fig. 3 (b), in the reset operation, since a large temperature rise is required in a short time, thermal interference is easily caused to adjacent memory cells, thereby affecting the accuracy of data stored in the adjacent memory cells.

Fig. 4 shows a specific bias condition of the memory cell 11 shown in fig. 2 when performing a reset operation, wherein the bias (bias) is meant to include the application of voltage and current. Referring to fig. 2 together, for example, when the calibration memory cell 11s shown in fig. 2 is to be reset, a positive voltage is applied to the word line WLn, a negative voltage is applied to the bit line BLn, as shown in fig. 4 (a), and a reset current Ireset is input to the bit line BLn, as shown in fig. 4 (b), to cause the reset pulse shown in fig. 3.

However, during the course of the present application, it was found that in actual operation, because of the intrinsic threshold characteristics of OTS (threshold switch Ovonic Threshold Switch), a surge current (inrush current) is generated as shown in fig. 4 (c), which in particular causes thermal interference to adjacent memory cells.

In a further development, as shown in fig. 5, fig. 5 is a schematic diagram illustrating the consistency of the phase change memory cell according to some embodiments of the present application after a weak reset operation. If a low reset current, e.g., 30-60uA, is applied to adjacent cells, i.e., a weak reset operation, good convergence (data consistency with increasing operation times) can be achieved, and the reset cells with poor convergence due to thermal disturbance can be repaired.

Thus, a method of operating a memory according to some embodiments of the present application includes:

Performing a reset operation on a calibrated memory cell in the memory array with a first current, and

And performing weak reset operation on at least one adjacent memory cell adjacent to the calibrated memory cell in the memory array by using a second current, wherein the second current is smaller than the first current.

Specifically, as shown in FIG. 2, the nominal memory cell connects the mth word line WLn and the nth bit line BLn in the memory array, the adjacent memory cell is connected to one of the mth-1 to m+1 word lines WLn-1/WLn/WLn+1, and one of the n-1 to n+1 bit lines BLn-1/BLn/BLn+1, the first current is passed through the nth bit line, the second current is passed through one of the n-1 to n+1 bit lines, that is, the first current is a reset current Ireset, which is applied to the nominal memory cell 11s connected to the word line WLn, and the second current is a weak reset current, which is applied to the adjacent memory cell 11s adjacent to the nominal memory cell.

It is further described that, as shown in fig. 2, the adjacent memory cells include at least two adjacent memory cells 11a located on (connected to) the same word line WLn but different bit lines BLn-1/bln+1, two adjacent memory cells 11b located on the same bit line BLn but different word lines WLn-1/wln+1, and four adjacent memory cells 11c located on different word lines WLn-1/wln+1 and different bit lines BLn-1/bln+1.

Thus, at least one adjacent memory cell of the pair of memory arrays adjacent to the nominal memory cell means any one of at least eight memory cells 11a, 11b, 11 c. In contrast, the application of the second current or weak reset current to the adjacent memory cells represents the application of the second current to one of the bit lines BLn-1/BLn/bln+1 to which the eight adjacent memory cells are connected.

That is, the reset operation includes applying a first voltage to an mth word line, applying a second voltage to an nth bit line, and the weak reset operation includes applying the first voltage to one word line WLn-1/WLn/wln+1 of the mth to m+1 word lines to which the adjacent memory cell is connected, and applying the second voltage to one bit line BLn-1/BLn/bln+1 of the n-1 to n+1 bit lines to which the adjacent memory cell is connected.

It is understood that although eight adjacent memory cells are exemplified herein, it is understood that the adjacent memory cells may be more peripheral adjacent memory cells, such as adjacent memory cells connected to word lines WLn-2, wln+2, or bit lines BLn-2, bln+2.

Fig. 6a and 6b illustrate bias conditions when weak reset operations are performed on adjacent memory cells 11a and 11b, respectively. The adjacent memory cell 11c operates in the same manner, and only the word lines and bit lines are arranged differently when read and weak reset are performed, so that it is not exemplified here for the sake of reduced space.

As shown in fig. 6a, after the first period t 1-t 2 performs the reset operation on the calibration memory cell 11s, between the second period t 2-t 3, the data stored in the adjacent memory cell 11a is judged first, and if the stored data is reset (reset) data, that is, 0, the weak reset operation is performed between the third period t 3-t 4, that is, as described above, a positive voltage is applied to the word line WLn connected to the adjacent memory cell 11a, a negative voltage is applied to the bit line bln+1 or BLn-1, and a weak reset current Ilowreset, that is, the second current described above is input to the bit line bln+1 or BLn-1, and the weak reset current is smaller than the reset current.

As shown in fig. 6b, after the first period t 1-t 2 resets the calibration memory cell 11s, the data stored in the adjacent memory cell 11b is first determined between the second period t 2-t 3, and if the stored data is reset (reset) data, that is, 0, the weak reset operation is performed between the third period t 3-t 4, that is, as described above, a positive voltage is applied to the word line wln+1/WLn-1 connected to the adjacent memory cell 11b, a negative voltage is applied to the bit line BLn, and a weak reset current Ilowreset, that is, the aforementioned second current is input to the bit line BLn, and the weak reset current is smaller than the reset current.

It should be noted that, in some embodiments, the weak reset operation may be directly performed on the adjacent memory cell without interpreting the stored data of the adjacent memory cell 11 a. In still other embodiments, the data stored in the adjacent memory cells may be interpreted before the reset operation of the calibration memory cell, so as to determine whether the weak reset operation is required. Therefore, the order of the interpretation of the stored data of the adjacent memory cells is not limited, and the weak reset operation may be performed even without the interpretation, as long as it is known.

In some embodiments, the weak reset operation is performed according to the requirement, because in the study of the present application, it is found that if the data stored in the adjacent memory cells 11a, 11b, 11c is the set data representing 1, the probability of being disturbed by the reset operation of the calibrated memory cell is smaller, so in order to save the operation time, in some embodiments, the weak reset operation requirement interpretation mechanism is added.

Therefore, the operation method according to some embodiments of the present application further includes a weak reset operation requirement determining mechanism, where the weak reset operation requirement determining mechanism may include adjacent memory cell data determining, that is, determining whether the data stored in the adjacent memory cell is reset data (i.e., data written in a reset operation), if yes, the weak reset operation is performed after the reset operation is performed, if not, the weak reset operation is not performed, and the adjacent memory cell data determining step may be performed before or after the reset operation is performed.

In addition, the weak reset operation requirement determining mechanism may include a calibration storage unit operation determination for determining whether an operation to be performed by the calibration storage unit is a reset operation, and if the operation to the calibration storage unit is not the reset operation, the thermal interference to the adjacent storage unit is not so serious, that is, the weak reset operation to the adjacent storage unit is not required. Based on such a technical idea, the weak reset operation requirement judgment of the storage operation method according to some embodiments of the present application further includes a calibration storage unit operation judgment for judging whether the calibration storage unit is to be subjected to a reset operation, if so, the weak reset operation is performed after the reset operation, and if not, the weak reset operation is not performed.

Also based on the technical idea of the present disclosure, in some embodiments, the weak reset operation requirement determining mechanism of the storage operation method according to some embodiments of the present disclosure further includes a weak reset trigger (trigger) determining, configured to determine, before performing the reset operation, whether the calibrated storage unit is located in a reset disturbance possible area, if yes, perform the adjacent storage unit data determination before or after performing the reset operation, and if not, not perform the adjacent storage unit data determination and the weak reset operation. It will be appreciated that this weak reset trigger determination may also be used when it is determined whether the calibration memory unit is to perform a reset operation before it is further determined whether a weak reset operation is to be performed.

In some embodiments, the determining whether the dummy memory cell is located in a reset disturbance capable region includes determining whether the dummy memory cell is located in a region within a driving bias influence distance, in a data error capable region, in a top stack or a bottom stack of the memory array, or the like. It should be understood that these judgment matters are merely examples, and the actual requirements may be selected according to various design conditions, and thus the technical idea of the present application is not limited thereto.

The region that is within the driving bias influence distance refers to the different distances between each memory cell and the word line driver (e.g., word line driver 212 of fig. 1) and the bit line driver (e.g., bit line driver 251 of fig. 1). For example, in the entire memory array, for example, four quadrants may be divided, the bias voltage applied to the region closest to the word line driver and the bit line driver may be stronger, and as the distance increases, the bias voltage applied may be weaker. Therefore, the probability that the calibration memory cells located in the closer area will generate thermal interference when the reset operation is performed is relatively high, and the probability that the calibration memory cells located in the farther area will generate thermal interference when the reset operation is performed is relatively low. Therefore, in some embodiments, in order to reduce the consideration of the operation time of the reset operation, the weak reset operation may not be performed for an area where the probability of generating thermal disturbance is not large. However, it is understood that such determination may not be made without affecting the technical idea of the present application.

The data error possible area may be a preset area, and the setting of the area may be performed in an external controller controlling the memory or may be set in a register of the memory itself, for example. It will be appreciated that during the test phase, the probability of error for memory cells in some addresses or regions will be higher due to manufacturing process errors, and that operation of memory cells in these regions will be more desirable.

The determination of whether to locate the top stack or the bottom stack of the memory array is based on the same principle that there is a greater probability of errors in the data being stored in these areas, and therefore more rigorous protection is provided especially in these areas.

From the foregoing, it can be appreciated that in the operating method according to some embodiments of the present application, the operating method further includes a weak reset operation requirement determination, where the weak reset operation requirement determination may include performing a calibration memory cell operation determination after the weak reset trigger determination and the adjacent memory cell data determination if the adjacent memory cell data determination is performed before the reset operation, for determining whether the calibration memory cell is to be subjected to the reset operation, and performing the weak reset operation after the reset operation if the calibration memory cell is not to be subjected to the reset operation, and not performing the weak reset operation if the calibration memory cell is not to be subjected to the reset operation. In summary, the time points of these determinations may be arbitrarily arranged without absolute order, and these determinations are not all required, and only at least one of them may be selected to make a determination as to whether or not to perform a weak reset.

Specifically, as shown in fig. 7 and 8, fig. 7 and 8 respectively show operation steps with weak reset operation requirement determination according to some embodiments of the present application. As previously described, it will be appreciated that the weak reset operation requirement determination may be at any suitable point prior to performing the weak reset operation, and thus the embodiments shown in fig. 7 and 8 are merely exemplary of some embodiments.

As shown in fig. 7, fig. 7 illustrates a weak reset operation need judgment sequence. First, in step S11, it is determined whether there is a weak reset trigger set to perform the weak reset function, that is, whether the addressed calibration memory cell is located in the specific area described above or has a flag to perform the weak reset operation. If there is no (N), the process proceeds to step S13a, and it is determined whether the calibration storage unit is to be reset, if yes, the process proceeds to step S14a, and if no (N), the process is certainly ended.

If yes, the step S11 goes to step S12 to determine whether the neighboring memory cells store the reset data (i.e. the data obtained by the reset operation). The determination may be performed by reading the data of the adjacent memory cells, or may be obtained by reading the data buffered in the buffer, and any other manner of obtaining the data is possible, so long as the data can be obtained without limitation.

If the result of step S12 is yes (Y), step S13 is further proceeded to determine whether to perform the reset operation on the calibration memory cell (i.e. the calibration memory cell operation determination). If the result of step S12 is that there is no (N), the process proceeds to step S13a and below described above.

In step S13, if there is no (N) reset operation to be performed on the calibration memory unit 11S, the procedure is ended, and if there is (Y) reset operation to be performed on the calibration memory unit 11S, then in step S14 the calibration memory unit 11S is reset, then in step S15 the weak reset operation is performed on the adjacent memory units, and then the procedure is ended.

In this embodiment, various weak reset operation need judging steps are performed before, so that after the reset operation is performed on the calibration memory cell, the weak reset operation is performed on the adjacent memory cell.

Fig. 8 shows another example of the weak reset operation requirement judgment sequence. First, in step S21, it is determined whether there is a weak reset trigger set to perform a weak reset function, that is, whether the addressed calibration memory cell is located in the specific area described above or has a flag to perform a weak reset operation. If there is no (N), the process proceeds to step S22a, and it is determined whether the calibration storage unit is to be reset, if yes, the process proceeds to step S23a, and if no (N), the process is certainly ended.

If yes, the step S21 goes to step S22 to determine whether to perform the reset operation on the calibration memory cell. If the result of step S22 is no (N), the operation procedure may be ended. If yes, the step S22 proceeds to step S23 to execute the reset operation on the calibration memory cell.

After the execution of step S23, step S24 is performed to determine whether the adjacent storage unit is reset data.

In step S24, if yes (Y), the process proceeds to step S25 to perform a weak reset operation on the adjacent memory cells, and then ends. If the result is not (N), the process is directly finished.

In this embodiment shown in fig. 8, the step of determining the adjacent memory cells in the weak reset operation requirement determination is set back, that is, after the calibration memory cells are subjected to the reset operation.

The above-described fig. 7 and 8 are merely examples, and as described above, the order of the various determinations may be arbitrarily arranged as long as the determination is performed before the weak reset operation is actually performed, and the determination of the various required weak reset operations is not all required, or only at least one of them may be selected for the determination.

By the weak reset operation method, the thermal interference to the adjacent memory cells during the reset operation can be relieved, and the weak reset operation can be performed according to the requirement, so that the operation efficiency of the memory can be further improved besides the thermal interference prevention effect.

In accordance with the foregoing manner of operation, some embodiments of the present application also provide a memory as described below.

As shown in fig. 9, and referring to fig. 2, a memory 300 provided according to some embodiments of the present application includes:

a memory array 10 comprising the calibration memory cells 11s described above and at least one adjacent memory cell adjacent to the calibration memory cells 11s, and

Peripheral circuitry 30 configured to perform a reset operation on the nominal memory cells at a first current;

and performing weak reset operation on the at least one adjacent memory cell with a second current, wherein the second current is smaller than the first current.

Specific details of the operation have been set forth in the previous description of fig. 2 and in connection with fig. 6a and 6b and will not be repeated here.

In some embodiments, as shown in fig. 2 and fig. 6a and fig. 6b, the calibration memory cell 11s connects the mb-th word line and the n-th bit line in the memory array, the adjacent memory cells 11a/11b/11c are connected to one of the m-1 to m+1-th word lines, and one of the n-1 to n+1-th bit lines, the first current passes through the n-th bit line, and the second current passes through one of the n-1 to n+1-th bit lines.

In some embodiments, as shown in fig. 9, the memory 300 further includes a weak reset operation requirement determination module 31, and the weak reset operation requirement determination module 31 may include a first data determination module 31a, a second data determination module 31b, and a weak reset trigger module 31c.

The first data judging module 31a is configured to perform data judgment of adjacent memory cells, and is configured to judge whether the data stored in the adjacent memory cells is reset data, if so, send a first weak reset execution signal to enable the peripheral circuit to perform the weak reset operation after performing the reset operation, and if not, send no first weak reset execution signal to enable the peripheral circuit not to perform the weak reset operation.

In particular, such a mechanism is described in the adjacent memory cell data judgment step described above. Referring to fig. 1, in some embodiments, the first data determining module 31a may be read by a sense amplifier comparator or may be obtained according to data in a buffer (not shown) for inputting data, so the first data determining module 31a is described above instead of the sense amplifier comparator or the buffer.

The weak reset trigger module 31c is configured to determine whether the calibration memory cell is located in a possible reset interference area, if yes, send a weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination or the weak reset operation, and if not, not send the weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination and the weak reset operation.

In some embodiments, the weak reset trigger module 31c determines whether to send the weak reset trigger signal or the weak reset cancel signal according to whether the calibration memory cell is located in the driving bias influence range, the data error possible range, or the top stack layer or the bottom stack layer of the memory array.

Specifically, the function performed by this weak reset trigger module 31c is the same as the weak reset trigger judgment operation described above, and therefore, description will not be repeated. It will be appreciated that the weak reset trigger module 31c may be provided in the memory 300 itself, including registers and buffers, and preset flags, etc., or may be provided in an external controller for controlling the memory, and may send the flags to the logic control module 230 shown in fig. 1 to control the above-mentioned operations.

The second data determining module 31b is configured to perform the operation determination of the calibration memory cell, that is, determine whether the calibration memory cell 11s is to be subjected to the reset operation, if so, send a second weak reset execution signal to enable the peripheral circuit to perform the weak reset operation, and if not, send no second weak reset execution signal to enable the peripheral circuit not to perform the weak reset operation.

Specifically, the actions performed by the second data determination module 31b described herein correspond to the calibration storage unit operation determination steps described above. In some embodiments, as described above, for the operation determination of the calibration storage unit, the data to be stored in the calibration storage unit may be retrieved from the buffer according to the address to determine the operation to be performed by the calibration storage unit, and thus the description will not be repeated here.

The weak reset operation requirement determination module 31 is a corresponding device for performing the weak reset operation requirement determination operation, and the specific embodiments of the first data determination module 31a, the second data determination module 31b, and the weak reset trigger module 31c included in the weak reset operation requirement determination module 31 may be performed by the logic control module 230 shown in fig. 1 and the flag bit or the read data of the register and the like described above are not limited and are not repeated herein. As described above, these determination modules may be provided by selecting at least one of them, and it is not always necessary to provide all of them, and fig. 9 shows all three modules for convenience of illustration. With the memory shown in fig. 9, in addition to the thermal interference to the adjacent memory cells during the reset operation can be alleviated, and the weak reset operation can be performed as required, so that the operation efficiency of the memory can be further improved in addition to the heat interference prevention effect.

According to some embodiments of the present application, as shown in FIG. 10, there is further provided a storage system 400, the storage system 400 including the memory 300 described previously, and

A controller 40 electrically connected to the memory 300 for controlling the memory 300, and the first data determination module 31a, the second data determination module 31b, and the weak reset trigger module 31c shown in fig. 9 may be optionally provided in the peripheral circuit 30 of the memory, or in the controller 40, respectively. These modules may be placed in the memory 300 or the controller 40, as described above, because they may be obtained in various ways, as long as they are based on the technical ideas of the weak reset operation and the weak reset requirement determination disclosed in the present application.

In some embodiments, the storage system may be implemented as a multimedia card such as universal flash memory storage (UFS) devices, solid State Drives (SSDs), MMC, eMMC, RS-MMC and micro-MMC forms, secure digital cards in SD, mini SD and micro SD forms, personal Computer Memory Card International Association (PCMCIA) card type storage devices, peripheral Component Interconnect (PCI) type storage devices, PCI-express (PCI-E) type storage devices, compact Flash (CF) cards, smart media cards or memory sticks, and the like.

The foregoing description of the embodiments is only for the purpose of aiding in the understanding of the technical solutions of the present application and the core ideas thereof, and it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalents may be substituted for some of the technical features thereof, and these modifications or substitutions do not depart from the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (11)

1. A method of operating a memory, the method comprising:

Performing a reset operation on a calibrated memory cell in the memory array with a first current, and

And when the data stored in the adjacent memory cells of the calibration memory cell are reset data, selectively performing weak reset operation on the adjacent memory cells with a second current, wherein the second current is smaller than the first current.

2. The method of claim 1, further comprising determining a weak reset operation requirement for determining whether the weak reset operation is required.

3. The method according to claim 2, wherein the weak reset operation requirement determination includes a neighboring cell data determination for determining whether data stored in the neighboring cell is reset data, if so, the weak reset operation is performed after the reset operation is performed, if not, the weak reset operation is not performed, and the neighboring cell data determination step may be performed before or after the reset operation is performed.

4. The method according to claim 2, wherein the weak reset operation demand determination includes a weak reset trigger determination for determining whether the calibration memory cell is located in a reset possible area before the reset operation is performed, if so, performing the adjacent memory cell data determination before or after the reset operation is performed, and if not, not performing the adjacent memory cell data determination and the weak reset operation.

5. The method of claim 4, wherein determining whether the memory cell is in a reset disturbance capable region comprises determining whether the calibration memory cell is in a region within a drive bias influence distance, in a data error capable region, or in a top stack or a bottom stack of the memory array.

6. The method according to claim 2, wherein the weak reset operation requirement determination includes a calibration memory cell operation determination for determining whether the calibration memory cell is to be subjected to a reset operation, if so, the weak reset operation is performed after the reset operation, and if not, the weak reset operation is not performed.

7. A memory, the memory comprising:

A memory array comprising a calibration memory cell and at least one adjacent memory cell adjacent to the calibration memory cell, and

And selectively performing a weak reset operation on adjacent memory cells of the nominal memory cell with a second current when the data stored in the adjacent memory cells are reset data, the second current being less than the first current.

8. The memory of claim 7 further comprising a first data determination module configured to determine whether data stored in the adjacent memory cells is reset data, if so, send a first weak reset execution signal to cause the peripheral circuit to perform the weak reset operation after performing the reset operation, and if not, not send the first weak reset execution signal to cause the peripheral circuit not to perform the weak reset operation.

9. The memory of claim 8 further comprising a weak reset trigger module configured to determine whether the calibration memory cell is in a reset disturbance possible region, and if so, send a weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination or the weak reset operation, and if not, not send the weak reset trigger signal to enable the peripheral circuit to perform the adjacent memory cell data determination and the weak reset operation.

10. The memory of claim 7 further comprising a second data determination module for determining whether the nominal memory cell is to be reset, if so, sending a second weak reset execution signal to cause the peripheral circuit to perform the weak reset operation, and if not, not sending the second weak reset execution signal to cause the peripheral circuit not to perform the weak reset operation.

11. A storage system, comprising:

the memory according to claim 7 to 10, and

And the controller is electrically connected with the memory and used for controlling the memory.