CN118764023B - A TTL level conversion circuit - Google Patents
A TTL level conversion circuit Download PDFInfo
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- CN118764023B CN118764023B CN202411248884.2A CN202411248884A CN118764023B CN 118764023 B CN118764023 B CN 118764023B CN 202411248884 A CN202411248884 A CN 202411248884A CN 118764023 B CN118764023 B CN 118764023B
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- 230000005669 field effect Effects 0.000 claims abstract description 17
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 8
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention discloses a TTL level conversion circuit, which belongs to the technical field of semiconductor integrated circuits, wherein a level conversion module adopts a plurality of D tubes connected in series to shift an input level into a first target level, the D tubes are gallium arsenide depletion type field effect transistors, an inverter module comprises a first-stage inverter and a second-stage inverter which are electrically connected in sequence, each of the first-stage inverter and the second-stage inverter comprises an inversion logic functional unit, a power supply branch and a load unit, the inversion logic functional unit is electrically connected with the power supply branch and the load unit power supply branch respectively, and the field effect transistors in the inversion logic functional unit, the power supply branch and the load unit are D tubes. The method has the advantages that the level conversion circuit meeting the requirements is designed on the premise of not using the enhancement type field effect transistor based on the depletion type field effect transistor and the resistor, the simplification and the miniaturization of the monolithic microwave integrated circuit are promoted, and the process applicability is greatly improved.
Description
Technical Field
The invention relates to a TTL level conversion circuit, which belongs to the technical field of semiconductor integrated circuits.
Background
In order to control the on/off of the control type monolithic microwave integrated circuits such as attenuators, phase shifters, switching chips, etc., digital drivers are often integrated on-chip or externally added to the control type monolithic microwave integrated circuits, and a digital driver Transistor-Transistor Logic (TTL) circuit is responsible for outputting the common +5V/0V voltage to the on/off voltage required by a switch tube. The ED mode of gallium arsenide pHEMT is typically used to design TTL drive circuits, pHEMT tubes have greater output resistance, higher transconductance, higher current handling capability, and lower noise than conventional HEMT tubes.
Most of known switch tubes for designing attenuators, phase shifters and switches adopt depletion type field effect tubes, the opening voltage range of the switch tube is determined to be-0.7V-1V and the closing voltage is determined to be-5V-1V according to a PDK manual provided by a manufacturer and an actual direct current scanning result, and therefore the high and low levels output by a TTL level conversion circuit are within the range, so that the switch tube can be driven to be opened and closed.
Traditional TTL level conversion circuits are designed by ED mode, D pipe plays a role in load, and E pipe (enhanced field effect transistor) plays a key logic role. The device mainly comprises a level conversion module and an inverter module, wherein the conventional inverter module is shown in fig. 1, and the source electrode of an E tube is directly connected with-5V power supply. However, in the case of gallium arsenide process libraries provided by various manufacturers, not all gallium arsenide libraries contain both E-tubes and D-tubes, and therefore, there are certain design limitations.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the prior art and provide a TTL level conversion circuit.
In order to solve the technical problems, the invention is realized by adopting the following technical scheme.
The invention discloses a TTL level conversion circuit, which comprises a level conversion module and an inverter module;
the level conversion module adopts a plurality of D tubes connected in series to shift the input level into a first target level, and the D tubes are gallium arsenide depletion type field effect tubes;
The inverter module comprises a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on inverting logic, and the second-stage inverter converts the input second target level into a third target level based on inverting logic;
The first-stage inverter and the second-stage inverter comprise an inversion logic functional unit, a power supply branch and a load unit, wherein the inversion logic functional unit is respectively and electrically connected with the power supply branch and the load unit power supply branch, and field effect transistors in the inversion logic functional unit, the power supply branch and the load unit are D tubes;
the level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter.
Further, the input levels are 0V and 5V, the first target level corresponding to the input level is negative voltage level and 0V, the second target level corresponding to the first target level is-0.7V-1V level and-5V-1V level after the first inversion by the first-stage inverter, and the third target level corresponding to the second target level is-5V-1V level and-0.7V-1V level after the second inversion by the second-stage inverter. The two-stage inverter acts as an inverter and improves the load carrying capability by stabilizing the output voltage waveform.
Further, the source electrode and the drain electrode of each D tube in the plurality of D tubes connected in series are connected, the grid electrode of the latter D tube is connected with the source electrode and the drain electrode of the former D tube, the grid electrode of the first D tube is connected with the input level, and the source electrode and the drain electrode of the last D tube are connected with the inverter module as a first node a. Compared with the prior art, the diode is formed by using the D-tube with the source electrode and the drain electrode connected, unidirectional conductivity is realized by controlling voltage through the grid electrode, and the applicability of the process is expanded.
Further, the level conversion module further includes a resistor R 1, one end of the resistor R 1 is connected to the first node a, and the other end of the resistor R 1 is connected to the inverter module as the second node b. Compared with the prior art, the large resistor R 1 reduces the power consumption of the input control voltage V in.
Further, the power supply branch of the first-stage inverter comprises a sixth D tube and a second resistor R 2, the second node b is connected with the drain electrode of the sixth D tube, the source electrode of the sixth D tube is connected with one end of the second resistor R 2, and the other end of the second resistor R 2 is respectively connected with-5V power supply and the grid electrode of the sixth D tube. Compared with the prior art, the connection method of the sixth D tube and the second resistor R 2 improves the resistance value of the power supply branch, so that the power consumption of-5V power supply is reduced.
Further, the inverting logic functional unit of the first-stage inverter comprises a third resistor R 3 and a plurality of seventh D tubes which are sequentially connected, and the load unit of the first-stage inverter comprises an eighth D tube and a fourth resistor R 4;
The source electrode of the former seventh D tube is connected with the drain electrode of the latter seventh D tube, the drain electrode of the first seventh D tube is used as a third node c to be respectively connected with one end of a fourth resistor R 4, the grid electrode of an eighth D tube and a second target level output end V out1, the source electrode of the last seventh D tube is used as a fourth node D to be connected with one end of a third resistor R 3, the other end of the third resistor R 3 is connected with-5V for supplying power, the grid electrodes of all seventh D tubes are connected with a second node b, the other end of the fourth resistor R 4 is connected with the source electrode of the eighth D tube, and the drain electrode of the eighth D tube is grounded.
In the inverter circuit module, a seventh D tube is used as logic, and the source electrode of the seventh D tube is connected in series with a third resistor R 3 and is connected in parallel with-5V to supply power, so that the voltage division of the source electrode resistor is realized. By controlling the cut-off resistance of the first resistor R 1 and the sixth D tube in the power supply branch, the cut-off resistance of the eighth D tube and the resistance of the fourth resistor R 4 in the load unit, the size of the seventh D tube of the inverter logic tube and the resistance of the third resistor R 3 can be switched on when the inverter inputs high level, and the inverter is switched off when the inverter inputs low level, so that the inversion function is completed.
Further, a fifth resistor R 5 is further disposed between the first-stage inverter and the second-stage inverter, one end of the fifth resistor R 5 is connected to the third node c, and the other end of the fifth resistor R 5 is connected to the second-stage inverter as a fifth node e. Compared with the prior art, the large resistor R 5 reduces the power consumption of the input control voltage V in.
Further, the power supply branch of the second-stage inverter comprises a ninth D tube and a sixth resistor R 6, a fifth node e is connected with the drain electrode of the ninth D tube, the source electrode of the ninth D tube is connected with one end of the sixth resistor R 6, and the other end of the sixth resistor R 6 is respectively connected with-5V power supply and the grid electrode of the ninth D tube. Compared with the prior art, the connection method of the ninth D tube and the second resistor R 2 improves the resistance value of the power supply branch, so that the power consumption of-5V power supply is reduced.
Further, the inverting logic functional unit of the second-stage inverter comprises a seventh resistor R 7 and a plurality of tenth D pipes which are sequentially connected, wherein the load unit of the second-stage inverter comprises an eleventh D pipe and an eighth resistor R 8;
The source electrode of the former tenth D tube is connected with the drain electrode of the latter tenth D tube, the drain electrode of the first tenth D tube is respectively connected with one end of an eighth resistor R 8, the grid electrode of the eleventh D tube and a third target level output end V out2, the source electrode of the last tenth D tube is used as a sixth node f to be connected with one end of a seventh resistor R 7, the other end of the seventh resistor R 7 is connected with-5V for supplying power, the grid electrodes of all tenth D tubes are connected with a fifth node e, the other end of the eighth resistor R 8 is connected with the source electrode of the eleventh D tube, and the drain electrode of the eleventh D tube is grounded.
In the inverter circuit module, a tenth D tube is logically acted, and the source electrode of the tenth D tube is connected in series with a seventh resistor R 7 to supply power for-5V, so that the voltage division of the source electrode resistor is realized. The size of the tenth D tube of the inverting logic tube and the resistance value of the seventh resistor R 7 can ensure that the inverter is conducted when the inverter inputs high level and is cut off when the inverter inputs low level, so that the inverting function is completed.
The invention has the beneficial effects that:
the circuit is based on the depletion type field effect transistor and the resistor, and the level conversion circuit meeting the requirements is designed on the premise of not using the enhancement type field effect transistor, so that the simplification and miniaturization of the monolithic microwave integrated circuit are promoted, and the process applicability is greatly improved.
Drawings
FIG. 1 is a block diagram of an inverter of a conventional TTL driving circuit;
FIG. 2 is a general architecture diagram of the present invention;
FIG. 3 is a circuit diagram of the present invention;
FIG. 4 is a graph of transient simulation results for an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
Embodiment 1, as shown in fig. 2, the present embodiment describes a TTL level conversion circuit, which includes a level conversion module and an inverter module;
the level conversion module adopts a plurality of D tubes connected in series to shift the input level into a first target level, and the D tubes are gallium arsenide depletion type field effect tubes;
The inverter module comprises a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on inverting logic, and the second-stage inverter converts the input second target level into a third target level based on inverting logic;
The first-stage inverter and the second-stage inverter comprise an inversion logic functional unit, a power supply branch and a load unit, wherein the inversion logic functional unit is respectively and electrically connected with the power supply branch and the load unit power supply branch, and field effect transistors in the inversion logic functional unit, the power supply branch and the load unit are D tubes;
the level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter.
The input level is 0V and 5V, the first target level corresponding to the input level is negative voltage level and 0V, the second target level corresponding to the first target level is-0.7V-1V level and-5V-1V level after the first inversion through the first-stage inverter, and the third target level corresponding to the second target level is-5V-1V level and-0.7V-1V level after the second inversion through the second-stage inverter.
The source electrode and the drain electrode of each D pipe in the plurality of D pipes connected in series are connected, the grid electrode of the latter D pipe is connected with the source electrode and the drain electrode of the former D pipe, the grid electrode of the first D pipe is connected with the input level, and the source electrode and the drain electrode of the last D pipe are connected with the inverter module as a first node a.
The level conversion module further comprises a resistor R 1, one end of the resistor R 1 is connected with the first node a, and the other end of the resistor R 1 is used as a second node b to be connected with the inverter module.
The power supply branch of the first-stage inverter comprises a sixth D tube and a second resistor R 2, the second node b is connected with the drain electrode of the sixth D tube, the source electrode of the sixth D tube is connected with one end of the second resistor R 2, and the other end of the second resistor R 2 is respectively connected with-5V power supply and the grid electrode of the sixth D tube.
The inverting logic functional unit of the first-stage inverter comprises a third resistor R 3 and a plurality of seventh D tubes which are sequentially connected, wherein the load unit of the first-stage inverter comprises an eighth D tube and a fourth resistor R 4;
The source electrode of the former seventh D tube is connected with the drain electrode of the latter seventh D tube, the drain electrode of the first seventh D tube is respectively connected with one end of a resistor R 4, the grid electrode of an eighth D tube and a second target level output end V out1 as a third node c, the source electrode of the last seventh D tube is connected with one end of a third resistor R 3 as a fourth node D, the other end of the third resistor R 3 is connected with-5V for supplying power, the grid electrodes of all seventh D tubes are connected with a second node b, the other end of the fourth resistor R 4 is connected with the source electrode of the eighth D tube, and the drain electrode of the eighth D tube is grounded.
A fifth resistor R 5 is further arranged between the first-stage inverter and the second-stage inverter, one end of the fifth resistor R 5 is connected with the third node c, and the other end of the fifth resistor R 5 is used as a fifth node e to be connected with the second-stage inverter.
The inverting logic functional unit of the second-stage inverter comprises a seventh resistor R 7 and a plurality of tenth D pipes which are sequentially connected, wherein the load unit of the second-stage inverter comprises an eleventh D pipe and an eighth resistor R 8;
The source electrode of the former tenth D tube is connected with the drain electrode of the latter tenth D tube, the drain electrode of the first tenth D tube is respectively connected with one end of a resistor R 8, the grid electrode of the eleventh D tube and a third target level output end V out2, the source electrode of the last tenth D tube is used as a sixth node f to be connected with one end of a seventh resistor R 7, the other end of the seventh resistor R 7 is connected with-5V for supplying power, the grid electrodes of all tenth D tubes are connected with a fifth node e, the other end of the eighth resistor R 8 is connected with the source electrode of the eleventh D tube, and the drain electrode of the eleventh D tube is grounded.
The power supply branch of the second-stage inverter comprises a ninth D tube and a sixth resistor R 6, a fifth node e is connected with the drain electrode of the ninth D tube, the source electrode of the ninth D tube is connected with one end of the sixth resistor R 6, and the other end of the sixth resistor R 6 is respectively connected with-5V power supply and the grid electrode of the ninth D tube.
Embodiment 2, as shown in the present embodiment, introduces a TTL level conversion circuit, especially in the inverter module, where the level shift module shifts the input 0V and 5V to a certain negative voltage level and a level of about 0V. The negative pressure level and the level about 0V output by the level shift module are output by the first-stage inverter with the V out1 as-0.7V-1V level and-5V-1V level, -0.7V-1V level and-5V-1V level through the second-stage inverter with the V out2 as-5V-1V and-0.7V-1V level. The invention is composed of gallium arsenide depletion type field effect transistor and resistor.
The first D tube T 1, the second D tube T 2, the third D tube T 3, the fourth D tube T 4 and the fifth D tube T 5 of the level shift module are respectively connected in source-drain mode, the source electrode or the drain electrode of the fifth D tube T 5 is connected with one end of a first resistor, the other end of the first resistor is a second node b, the second node b is connected with the drain electrode of the sixth D tube T 6, the sixth D tube T 6 and the second resistor are connected in series to form a large resistor, and the other end of the second resistor is connected with-5V power supply.
The second node b is the input end of the inverter module, the second node b is connected with the drain electrode of the sixth D tube, the other end of the sixth D tube is connected with-5V power supply, the second node b is connected with the grid electrode of the seventh D tube, the source electrode of the seventh D tube is connected with a third resistor, the other end of the third resistor is connected with-5V power supply, the drain electrode of the seventh D tube is a third node c, and the third node c leads out outputThe drain electrode of the seventh D tube is connected with a fourth resistor, the other end of the fourth resistor is connected with the source electrode of the eighth D tube, the drain electrode of the eighth D tube is grounded, and the source electrode of the eighth D tube and the fourth resistor are connected in series to form a large resistor.
In the first-stage inverter, a seventh D-tube plays a key logic role, and compared with an E-tube, the D-tube is already conducted when V gs = 0, so that a third resistor is connected in series with the drain electrode of the seventh D-tube, and by setting a proper third resistor value, the seventh D-tube can complete the functions of on and off when a high level and a low level are input.
The second-stage inverter is characterized in that V out1 is used as an input end of the second-stage inverter, the input end of the second-stage inverter is connected with one end of a fifth resistor, the other end of the fifth resistor is a fifth node e, the fifth node e is connected with a drain electrode of a ninth D tube, a source electrode of the ninth D tube is connected with a sixth resistor, a grid electrode of the ninth D tube is connected with the drain electrode to form a large resistor, the large resistor is connected in series with the sixth resistor, the other end of the sixth resistor is connected with a power supply of-5V, the fifth node e is connected with a tenth D tube, the source electrode of the tenth D tube is connected with a seventh resistor, the other end of the seventh resistor is connected with a power supply of-5V, the drain electrode of the tenth D tube is led out to be an output V out2, the drain electrode of the tenth D tube is connected with an eighth resistor, the other end of the eighth resistor is connected with an eleventh D tube, the drain electrode of the eleventh D tube is grounded, and the grid electrode of the eleventh D tube is connected with the source electrode to form the large resistor, and the large resistor is connected in series with the eighth resistor.
In the second inverter, the tenth D-tube has a key logic function, and the D-tube is turned on when V gs = 0 compared with the E-tube, so that the drain electrode of the tenth D-tube is connected in series with a seventh resistor, and by setting a suitable seventh resistance value, the tenth D-tube can complete the functions of turning on and off when a high level and a low level are input.
Embodiment 3 of the invention describes a TTL level shift circuit, as shown in FIG. 3, comprising a first D-tube T 1, a second D-tube T 2, a third D-tube T 3, a fourth D-tube T 4, the fifth D-tube T 5 is connected with source and drain to form a first diode, a second diode, a third diode, a fourth diode and a fifth diode. The final stage of the fifth diode is connected with a first resistor R 1, the other end of the first resistor R 1 is a second node b, the second node b is connected with the drain electrode of a sixth D tube T 6 and is connected with a second resistor R 2 in series to form a large resistor, the other end of the second resistor R 2 is connected with a V EE for supplying power, and V EE = -5V. When the sizes of the first D-tube T 1, the second D-tube T 2, the third D-tube T 3, the fourth D-tube T 4, and the fifth D-tube T 5 are different, the corresponding forward conduction voltage drops may be different, so that the sizes and the numbers of the field effect transistors are selected according to the specific situation.
The first-stage inverter comprises a second node b serving as an input end of an inverter circuit, wherein the second node b is connected with a sixth D tube T 6, the other end of the sixth D tube T 6 is connected with a V EE for power supply, the second node is connected with a grid electrode of a seventh D tube T 7, a source electrode of the seventh D tube T 7 is connected with a third resistor R 3, the other end of the third resistor R 3 is connected with a V EE for power supply, a drain electrode of the seventh D tube T 7 is a third node c, an output V out1 is led out from the third node c, a drain electrode of the seventh D tube T 7 is connected with a fourth resistor R 4, the other end of the fourth resistor R 4 is connected with a source electrode of an eighth D tube T 8, and a drain electrode of the eighth D tube T 8 is grounded, and the source electrode of the eighth D tube T 8 is connected with the fourth resistor R 4 in series to form a large resistor. The seventh D-tube T 7, which has been turned on when V gs =0, is compared with the E-tube, and therefore, the drain of the seventh D-tube T 7 is connected in series with the third resistor R 3, and by setting a suitable third resistance value, the seventh D-tube T 7 can perform the functions of turning on and off when a high level and a low level are input.
The second-stage inverter is characterized in that V out1 serves as an input end of the second-stage inverter, the input end of the second-stage inverter is connected with a fifth resistor R 5, the other end of the fifth resistor R 5 is a fifth node e, the fifth node e is connected with a drain electrode of a ninth D tube T 9, a source electrode of the ninth D tube T 9 is connected with a sixth resistor R 6, a grid electrode of the ninth D tube T 9 is connected with the drain electrode to form a large resistor, the second-stage inverter is connected with a sixth resistor R 6 in series, the other end of the sixth resistor R 6 is connected with a V EE for supplying power, the fifth node is connected with a tenth D tube T 10, a source electrode of the tenth D tube T 10 is connected with a seventh resistor R 7, the other end of the seventh resistor R 7 is connected with a V EE for supplying power, a drain electrode of the tenth D tube T 10 is led out to be an output V out2, a drain electrode of the tenth D tube T 10 is connected with an eighth resistor R 8, the other end of the eighth resistor R 8 is connected with an eleventh D tube T 11, a drain electrode of the eleventh D tube T 11 is grounded, and the grid electrode of the eighth D tube T 11 is connected with the source electrode to form a large resistor, and is connected with the eighth resistor R 8 in series. The tenth D tube T 10, which has been turned on when V gs =0, is compared with the E tube, and thus, the seventh resistor R 7 is connected in series to the drain of the tenth D tube T 10, and by setting a suitable seventh resistance value, the tenth D tube T 10 can perform the functions of turning on and off when the high and low levels are input.
TTL level translation circuit principle:
When a +5v high level is input, under the condition that the voltage difference between the two ends of the first D tube T 1, the second D tube T 2, the third D tube T 3, the fourth D tube T 4 and the fifth D tube T 5 is enough, five diodes are conducted, the voltage drop of each diode is about 0.98V, the level V a at the first node a is 5-0.98×5=0.1V, the sixth D tube T 6 and the second resistor R 2 are equivalent to a large resistor close to the cut-off state, and the resistor cannot be infinitely large, so that the existence of small current is allowed in a circuit in practical application.
In the first inverter, a first resistor R 1, a sixth D-tube T 6, On the branch lines of the second resistors R 2 and V EE, the voltage V b of the second node b is (V EE-Va)×(RT6/( R1+ RT6) obtained by a resistor voltage division formula, and is obtained in an eighth D tube T 8, A fourth resistor R 4, a seventh D tube T 7, The voltage V d at the fourth point d is 5 x (R 3/( RT8+ R3) according to the resistance voltage division formula on the third resistor R 3 and the-5V branch, the first resistor R 1 is controlled by the control resistor, Cut-off voltage R T6 of sixth D-tube T 6, cut-off voltage R T8 of eighth D-tube T 8, The size of the third resistor R 3 ensures (V b-Vd)＞VTH, the seventh D tube T 7 is conducted, and V out1=Vd is approximately equal to-3.4V;
Similarly, the voltage V e at the fifth node e of the second inverter is (V EE- Vout1)×(RT9/(R5+ RT9)), the voltage V f at the sixth node f is 5× (R 7/( RT11+ R7), and the voltage V e-Vf)＞VTH, the tenth D-tube T 10 is turned off, and V out2 ≡0.4V is ensured by controlling the magnitudes of the fifth resistor R 5, the turn-off voltage R T9 of the ninth D-tube T 9, the turn-off voltage R T11 of the eleventh D-tube T 11, and the seventh resistor R 7.
When a low level of 0V is input, the level V a at the first node a is 0-0.98X5 (R 7/( RT11+ R7)) and V b≈Va, the voltage V d at the fourth point D is 5 (R 3/( RT8+ R3)), the voltage V b-Vd is ensured to be smaller than V TH, the seventh D tube T 7 is cut off, V out1=Vc (V) is approximately-0.4V, the voltage V e at the fifth node e is (V EE- Vout1)×(RT9/(R5+ RT9)), the voltage V f at the sixth node f is 5 (R 7/( RT11+ R7)), the voltage V e-Vf is ensured to be smaller than V TH, the tenth D tube T 10 is conducted, and V out2=Vf (V) is approximately-3.4V.
In order to reduce the dc power consumption, the dimensions of the first resistor R 1, the second resistor R 2, the third resistor R 3, the fourth resistor R 4, the fifth resistor R 5, the sixth resistor R 6, the seventh resistor R 7, and the eighth resistor R 8, which are at least kiloohm-level large resistors, need to be determined according to the actual conditions of the circuit, and the dimensions of the first D-tube T 1, the second D-tube T 2, the third D-tube T 3, the fourth D-tube T 4, the fifth D-tube T 5, the sixth D-tube T 6, the seventh D-tube T 7, and the eighth D-tube T 8 are required.
Finally, the conversion of the input 5V/0V into the complementary high-low level output V out1 V/-0.4V, V out2 of-0.4V/-3.4V, the switching time of 17ns and the maximum power consumption of-5V/0.42 mu A are realized based on the depletion type field effect transistor and the resistor only, and the maximum power consumption is shown in figure 4. The generated complementary level outputs V out1 and V out2 are sufficient for driving the switch tube in the control type microwave integrated circuit to be turned on and off, thereby promoting the simplification and miniaturization of the monolithic microwave integrated circuit and greatly improving the process applicability.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (6)
1. The TTL level conversion circuit is characterized by comprising a level conversion module and an inverter module;
the level conversion module adopts a plurality of D tubes connected in series to shift the input level into a first target level, and the D tubes are gallium arsenide depletion type field effect tubes;
The inverter module comprises a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on inverting logic, and the second-stage inverter converts the input second target level into a third target level based on inverting logic;
The first-stage inverter and the second-stage inverter comprise an inversion logic functional unit, a power supply branch and a load unit, wherein the inversion logic functional unit is respectively and electrically connected with the power supply branch and the load unit power supply branch, and field effect transistors in the inversion logic functional unit, the power supply branch and the load unit are D tubes;
The level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter;
The grid electrode of the latter D tube is connected with the source electrode or the drain electrode of the former D tube, the grid electrode of the first D tube is connected with the input level, and the source electrode or the drain electrode of the last D tube is connected with the inverter module as a first node a;
The level conversion module further comprises a resistor R 1, one end of the resistor R 1 is connected with the first node a, and the other end of the resistor R 1 is used as a second node b to be connected with the inverter module;
The power supply branch of the first-stage inverter comprises a sixth D tube and a second resistor R 2, the second node b is connected with the drain electrode of the sixth D tube, the source electrode of the sixth D tube is connected with one end of the second resistor R 2, and the other end of the second resistor R 2 is respectively connected with-5V power supply and the grid electrode of the sixth D tube.
2. The TTL level shift circuit of claim 1, wherein the input levels are 0V and 5V, the first target level corresponding to the input level is a negative voltage level and 0V, the second target level corresponding to the first target level is a-0.7v to 1V level and a-5V to 1V level after the first inversion by the first inverter, and the third target level corresponding to the second target level is a-5V to 1V level and a-0.7v to 1V level after the second inversion by the second inverter.
3. The TTL level conversion circuit of claim 1, wherein the inverting logic functional unit of the first stage inverter comprises a third resistor R 3 and a plurality of seventh D tubes connected in sequence, the load unit of the first stage inverter comprises an eighth D tube and a fourth resistor R 4;
The source electrode of the former seventh D tube is connected with the drain electrode of the latter seventh D tube, the drain electrode of the first seventh D tube is respectively connected with one end of a resistor R 4, the grid electrode of an eighth D tube and a second target level output end V out1 as a third node c, the source electrode of the last seventh D tube is connected with one end of a third resistor R 3 as a fourth node D, the other end of the third resistor R 3 is connected with-5V for supplying power, the grid electrodes of all seventh D tubes are connected with a second node b, the other end of the fourth resistor R 4 is connected with the source electrode of the eighth D tube, and the drain electrode of the eighth D tube is grounded.
4. The TTL level shift circuit of claim 3, wherein a fifth resistor R 5 is further disposed between the first stage inverter and the second stage inverter, one end of the fifth resistor R 5 is connected to the third node c, and the other end of the fifth resistor R 5 is connected to the second stage inverter as a fifth node e.
5. The TTL level conversion circuit of claim 4 wherein said inverting logic functional unit of said second stage inverter comprises a seventh resistor R 7 and a plurality of tenth D tubes connected in sequence, said load unit of said second stage inverter comprises an eleventh D tube and an eighth resistor R 8;
The source electrode of the former tenth D tube is connected with the drain electrode of the latter tenth D tube, the drain electrode of the first tenth D tube is respectively connected with one end of a resistor R 8, the grid electrode of the eleventh D tube and a third target level output end V out2, the source electrode of the last tenth D tube is used as a sixth node f to be connected with one end of a seventh resistor R 7, the other end of the seventh resistor R 7 is connected with-5V for supplying power, the grid electrodes of all tenth D tubes are connected with a fifth node e, the other end of the eighth resistor R 8 is connected with the source electrode of the eleventh D tube, and the drain electrode of the eleventh D tube is grounded.
6. The TTL level conversion circuit of claim 5 wherein the power supply branch of the second stage inverter includes a ninth D-tube and a sixth resistor R 6, a fifth node e is connected to the drain of the ninth D-tube, the source of the ninth D-tube is connected to one end of the sixth resistor R 6, and the other end of the sixth resistor R 6 is connected to-5V power supply and the gate of the ninth D-tube, respectively.
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| US4568844A (en) * | 1983-02-17 | 1986-02-04 | At&T Bell Laboratories | Field effect transistor inverter-level shifter circuitry |
| US4798978A (en) * | 1987-04-30 | 1989-01-17 | Gain Electronics Corporation | GAAS FET logic having increased noise margin |
| JPH0263319A (en) * | 1988-08-30 | 1990-03-02 | Fujitsu Ltd | input buffer |
| JPH089738B2 (en) * | 1991-04-05 | 1996-01-31 | 川崎製鉄株式会社 | Buckling occurrence prediction device |
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