CN118759925A - Domain controller standby control method, control device, storage medium and vehicle - Google Patents

Abstract

The present invention discloses a control method, a control device, a storage medium and a vehicle for a domain controller standby. The method includes: periodically detecting whether the vehicle controller sends a vehicle sleep signal; generating a first control instruction, a second control instruction and a third control instruction when the vehicle sleep signal is received; controlling the system-level chip in the domain controller to suspend program execution based on the first control instruction and storing the execution result of the system-level chip at the current moment into a dynamic random access memory; controlling the data selector in the domain controller to switch the reset mode of the dynamic random access memory from the initial mode to the target mode based on the second control instruction; and controlling the power management circuit to perform a power-off action on the system-level chip based on the third control instruction. The present invention solves the technical problem of high power consumption when the domain controller is in sleep mode.

Description

Domain controller standby control method, control device, storage medium and vehicle

Technical Field

The present invention relates to the technical field of domain controller control, and in particular to a domain controller standby control method, a control device, a storage medium and a vehicle.

Background Art

With the development of the central domain integrated architecture, in order to solve the problems of increasing number of ECUs in traditional architecture, increasing weight of vehicle wiring harnesses, and the inability of communication bandwidth between controllers to meet the needs of massive data communication, the automotive electronic and electrical architecture has gradually developed towards centralization, mainly including vehicle controller (VDC), regional controller (PDC), intelligent driving domain controller (HAD), and intelligent cockpit domain controller (CSC). Each domain is managed by a main control unit and communicates through the domain bus, realizing centralized management within the domain and coordination between domains. In such an architecture, the functions of multiple ECUs are integrated into a central control unit, the power consumption of the controller increases sharply, and the problems of endurance and heat dissipation caused by power consumption become more and more serious, and the power consumption of the chip accounts for a large proportion. Therefore, the low-power design of high-power chips in the domain controller has become a top priority. At present, domain controllers are connected to the vehicle network management, and the vehicle sends sleep wake-up signals. Most of the current domain controller sleep wake-up designs adopt the suspend to RAM (STR) suspend mode. When the system-level chip SOC enters STR, the continuous power supply (Always on: AON) domain of the SOC chip and the MCU chip must continue to maintain power supply to maintain the RESET pin of the external DDR chip and the monitoring of the MCU to ensure that the DDR is in self-refresh mode. Therefore, the DCDC and LDO of the previous stage must be connected to normal power, which introduces unnecessary power consumption and affects the vehicle's endurance.

To address the above-mentioned problems, no effective solution has been proposed yet.

Summary of the invention

The embodiments of the present invention provide a control method, a control device, a storage medium and a vehicle for a domain controller standby, so as to at least solve the technical problem of high power consumption when the domain controller is in sleep mode.

According to one aspect of an embodiment of the present invention, a control method for domain controller standby is provided, the method comprising periodically detecting whether a vehicle controller sends a vehicle sleep signal; generating a first control instruction, a second control instruction and a third control instruction when the vehicle sleep signal is received; controlling a system-level chip in the domain controller to suspend program execution based on the first control instruction and storing the execution result of the system-level chip at the current moment into a dynamic random access memory; controlling a data selector in the domain controller to switch a reset mode of the dynamic random access memory from an initial mode to a target mode based on the second control instruction, wherein in the initial mode, the reset signal of the dynamic random access memory is controlled by the system-level chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by a microcontroller unit in the domain controller; and controlling a power management circuit to power off the system-level chip based on the third control instruction.

Optionally, after controlling the power management circuit to execute a power-off process on the system-on-chip based on the third control instruction, the method further includes: storing standby information of the system-on-chip into the micro control unit, where the standby information includes a standby mode.

Optionally, after controlling the power management circuit to execute the power-off process on the system-level chip based on the third control instruction, the method also includes: periodically detecting whether the vehicle controller sends a vehicle wake-up signal; generating a fourth control instruction and a fifth control instruction when the vehicle wake-up signal is obtained; controlling the power management circuit to execute the power-on process on the system-level chip based on the fourth control instruction; and controlling the data selector to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction.

Optionally, after obtaining the vehicle wake-up signal, the method includes: obtaining from the micro control unit whether a power-off process before the wake-up process is legal; if so, generating a fifth control instruction.

Optionally, after controlling the data selector to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction, the method includes: controlling the system-level chip to read the execution result and the to-be-executed program information in the dynamic random access memory from the dynamic random access memory.

Optionally, after controlling the system-level chip to read the execution result and the information of the program to be executed in the dynamic random access memory from the dynamic random access memory, the method includes: controlling the power management circuit to execute a power-on process for the remaining devices in the domain controller.

According to another aspect of an embodiment of the present invention, a control device for a domain controller standby is also provided, comprising: an acquisition module, used to periodically detect whether the vehicle controller sends a vehicle sleep signal; a generation module, used to generate a first control instruction, a second control instruction and a third control instruction when the vehicle sleep signal is received; a first control module, used to control the system-level chip in the domain controller to suspend program execution based on the first control instruction and store the execution result of the system-level chip at the current moment into a dynamic random access memory; a second control module, used to control the data selector in the domain controller to switch the reset mode of the dynamic random access memory from an initial mode to a target mode based on the second control instruction, wherein in the initial mode, the reset signal of the dynamic random access memory is controlled by the system-level chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by a microcontroller unit in the domain controller; and a third control module, used to control the power management circuit to perform a power-off action on the system-level chip based on the third control instruction.

According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the above method when running.

According to yet another aspect of an embodiment of the present invention, a processor is provided, and the processor is used to run a program, wherein the program is configured to execute the above method when running.

According to another aspect of an embodiment of the present invention, a vehicle is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the method through the computer program.

In an embodiment of the present invention, when a vehicle sleep signal is received, a first control instruction, a second control instruction and a third control instruction are generated. The reset mode of the dynamic random access memory is switched from the initial mode to the target mode by controlling the data selector in the domain controller based on the second control instruction, and the power management circuit is controlled based on the third control instruction to power off the system-level chip. The purpose of completely hibernating the system-level chip by switching the reset signal control right of the dynamic random access memory is achieved, thereby achieving the technical effect of reducing power consumption without affecting the system's rapid startup again, and further solving the technical problem of high power consumption when the domain controller is in hibernation.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

1 is a hardware structure block diagram of a computer terminal according to a method for controlling standby of a domain controller according to an optional embodiment of the present invention;

FIG2 is a flow chart of a method for controlling standby of a domain controller according to an optional embodiment of the present invention;

3 is a structural diagram of a control system for a domain controller standby according to an optional embodiment of the present invention;

FIG. 4 is a flow chart of a method for controlling standby of a domain controller according to an optional embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

The vehicle's domain controller is a critical integrated system in modern cars, responsible for managing and coordinating the functions of different electronic control units (ECUs) in the vehicle. These controllers achieve centralized control of multiple key vehicle systems such as powertrain, chassis, body electronics, and infotainment through highly complex software and hardware architectures. Through domain controllers, vehicles can achieve more advanced automation functions, enhanced safety, and better energy efficiency.

MCU: The microcontroller unit (MCU) in the vehicle's domain controller field is a core component in the automotive electronic system, responsible for processing and controlling multiple key functions of the vehicle.

With the development of automotive electronics and intelligence, the traditional distributed ECU (electronic control unit) architecture has gradually shifted to a domain-centralized architecture. The domain controller (DCU) uses high-performance multi-core CPU/GPU chips to centrally control each domain. The domain controller uses the MCU to achieve centralized control and complex calculations of specific vehicle functional domains (such as power domain, chassis domain, cockpit domain, autonomous driving domain, and body domain). The MCU in the domain controller of modern vehicles needs to have high-performance processing capabilities to support advanced functions such as autonomous driving algorithms, sensor data processing, and vehicle communications. The MCU in the domain controller usually needs to have high-speed external communication interfaces, such as CAN FD and Ethernet, to support data exchange inside and outside the vehicle.

Soc: System-on-chip (SoC) is a key component in automotive electronic systems. It integrates multiple functional modules and provides a strong hardware foundation for the intelligence and networking of vehicles. SoC integrates multiple processors such as CPU, GPU, DSP, NPU, as well as memory, input/output ports and other peripherals on a single chip to achieve high integration.

SoC usually contains a high-performance CPU core. In the vehicle domain controller, SoC can process data from different sensors and actuators to achieve centralized control of multiple functional domains such as power, chassis, body, cockpit and autonomous driving. SoC has high-speed communication interfaces such as Ethernet and CAN FD to meet the high bandwidth requirements of the vehicle's internal network and external communication.

According to an embodiment of the present invention, an embodiment of a method for controlling standby of a domain controller is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

The method embodiment provided in the embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 shows a hardware structure block diagram of a computer terminal (or mobile device) for realizing the control of the standby of a domain controller. As shown in Figure 1, the computer terminal 10 (or mobile device 10) may include one or more (102a, 102b, ..., 102n are used in the figure to show) processors (the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission module 106 for communication functions. In addition, it may also include: a display, an input/output interface (I/O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and/or a camera. It can be understood by those skilled in the art that the structure shown in Figure 1 is only for illustration and does not limit the structure of the above-mentioned electronic device. For example, the computer terminal 10 may also include more or fewer components than those shown in Figure 1, or have a configuration different from that shown in Figure 1.

It should be noted that the one or more processors and/or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 10 (or mobile device). As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

The memory 104 can be used to store software programs and modules of application software, such as the program instructions/data storage device corresponding to the control of the domain controller standby in the embodiment of the present invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, realizing the control of the domain controller standby mentioned above. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

In the above operating environment, the present application provides a control of the domain controller standby as shown in Figure 2. Figure 2 is a flow chart of the control of the domain controller standby according to an embodiment of the present invention.

Methods include:

Step S1, periodically detecting whether the vehicle controller sends a vehicle sleep signal;

Step S2, when receiving the vehicle sleep signal, generating a first control instruction, a second control instruction and a third control instruction;

Step S3, based on the first control instruction, controlling the system-on-chip in the domain controller to suspend program execution and storing the execution result of the system-on-chip at the current moment into the dynamic random access memory;

Step S4, based on the second control instruction, controlling the data strobe in the domain controller to switch the reset mode of the dynamic random access memory from the initial mode to the target mode, wherein in the initial mode, the reset signal of the dynamic random access memory is controlled by the system-level chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by the microcontroller unit in the domain controller;

Step S5: controlling the power management circuit to power off the system-on-chip based on the third control instruction.

In an embodiment of the present invention, when a vehicle sleep signal is received, a first control instruction, a second control instruction and a third control instruction are generated. The reset mode of the dynamic random access memory is switched from the initial mode to the target mode by controlling the data selector in the domain controller based on the second control instruction, and the power management circuit is controlled based on the third control instruction to power off the system-level chip. The purpose of completely hibernating the system-level chip by switching the reset signal control right of the dynamic random access memory is achieved, thereby achieving the technical effect of reducing power consumption without affecting the system's rapid startup again, and further solving the technical problem of high power consumption when the domain controller is in hibernation.

The present application provides a low-power design solution for a domain controller, and proposes a solution using digital selection to switch DDR reset control rights for the existing single sleep and wake-up solution on the market; this solution can achieve a lower power consumption system design without affecting the fast startup of the system, and provides a unified solution for different domain controllers.

Specifically, when the system is in hibernation, only the MCU normal power domain needs to be powered, and the power of the SOC and other irrelevant peripherals can be completely turned off to keep the system power consumption lower. When the SOC enters hibernation, an innovative method is proposed to completely hibernate the SOC by controlling the data selector through the MCU to switch the control of the DRAM reset pin to reduce power consumption; compared with the existing method, this method has lower power consumption and does not affect the rapid startup of the system.

The solution of digitally switching DDR control rights fills the gap in the domain controller's inability to design lower power consumption, and there is no need to require the SOC to have STR function. This hardware design solution simplifies the selection and design difficulty of the SOC on the controller side and reduces the sleep power consumption of the entire vehicle.

Optionally, after controlling the power management circuit to execute a power-off process on the system-on-chip based on the third control instruction, the method further includes: storing standby information of the system-on-chip into the micro control unit, where the standby information includes a standby mode.

Optionally, after controlling the power management circuit to execute the power-off process on the system-level chip based on the third control instruction, the method also includes: periodically detecting whether the vehicle controller sends a vehicle wake-up signal; generating a fourth control instruction and a fifth control instruction when the vehicle wake-up signal is obtained; controlling the power management circuit to execute the power-on process on the system-level chip based on the fourth control instruction; and controlling the data selector to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction.

Optionally, after obtaining the vehicle wake-up signal, the method includes: obtaining from the micro control unit whether a power-off process before the wake-up process is legal; if so, generating a fifth control instruction.

Optionally, after controlling the data selector to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction, the method includes: controlling the system-level chip to read the execution result and the to-be-executed program information in the dynamic random access memory from the dynamic random access memory.

Optionally, after controlling the system-level chip to read the execution result and the information of the program to be executed in the dynamic random access memory from the dynamic random access memory, the method includes: controlling the power management circuit to execute a power-on process for the remaining devices in the domain controller.

As shown in Figure 3, the control of the domain controller standby provided in this application mainly includes MCU, PMIC, data selector, SOC and DDR. When the system is working normally, MCU controls PMIC to power SOC and DDR through GPIO. At this time, MCU controls the data selector to select the RESET signal of DDR to be controlled by SOC. MCU continuously monitors the SOC heartbeat signal through GPIO interconnected with SOC to ensure the normal operation of the system.

Combined with Figure 4, the process of system sleep wake-up process is as follows:

1. When the system is powered on for the first time, after the MCU detects that the whole machine has no faults, it will enable the power management IC (PMIC) to power the SOC, so that it enters the BOOT boot process. According to the initial settings of the chip, the SOC boots the program in the external storage into the DDR to complete the boot. At this point, the SOC starts to work normally.

2. When the MCU or SOC detects the vehicle sleep signal, they will first communicate through the SPI interface to inform each other, the system enters the sleep process, the SOC suspends program execution, stores the current result in DDR and then notifies the MCU. At this time, the MCU controls the digital selection to switch to the reset signal of the MCU control DDR, and keeps it at a high level. Then the MCU controls the PMIC to control the power-off timing of the SOC, and stores the standby mode status of the SOC in the MCU for query when waking up. Finally, the MCU notifies the whole machine to keep only the normal power, and the rest of the power is powered off to maintain low power consumption.

3. When the MCU receives the vehicle wake-up signal, it first controls the PMIC to power on. After the SOC reads the MCU status and confirms that the last power-off was normal sleep, it sends a "switch" command to the MCU. The MCU controls the data selector to complete the switching of the DDR reset signal, and the SOC reads the DDR data to complete the wake-up.

4. MCU controls other power supplies of the whole machine to power on, and the whole board works normally.

Although this solution completely cuts off the power supply of the SOC during hibernation, it does not take too much time to complete the configuration of basic information such as system parameter configuration, file path, registry, device driver and environment variables like the system cold start. This is because the data from the last hibernation is stored in DDR, and the CPU core can directly boot the program at the current location, which avoids the time wasted by restarting the operating system and reduces the overall power consumption during hibernation. When the system is in hibernation, it only needs to keep the MCU powered in the normal power domain, and the power supply of the SOC and irrelevant peripherals can be completely turned off to keep the system power consumption lower, and the control of the DRAM reset pin is switched through the MCU control data selector.

It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described order of actions, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

According to an embodiment of the present invention, a control device for a domain controller standby is also provided, comprising: an acquisition module, used to periodically detect whether the vehicle controller sends a vehicle sleep signal; a generation module, used to generate a first control instruction, a second control instruction and a third control instruction when the vehicle sleep signal is received; a first control module, used to control the system-level chip in the domain controller to suspend program execution based on the first control instruction and store the execution result of the system-level chip at the current moment into a dynamic random access memory; a second control module, used to control the data selector in the domain controller to switch the reset mode of the dynamic random access memory from an initial mode to a target mode based on the second control instruction, wherein in the initial mode, the reset signal of the dynamic random access memory is controlled by the system-level chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by a microcontroller unit in the domain controller; and a third control module, used to control the power management circuit to perform a power-off action on the system-level chip based on the third control instruction.

In an embodiment of the present invention, when a vehicle sleep signal is received, a first control instruction, a second control instruction and a third control instruction are generated. The reset mode of the dynamic random access memory is switched from the initial mode to the target mode by controlling the data selector in the domain controller based on the second control instruction, and the power management circuit is controlled based on the third control instruction to power off the system-level chip. The purpose of completely hibernating the system-level chip by switching the reset signal control right of the dynamic random access memory is achieved, thereby achieving the technical effect of reducing power consumption without affecting the system's rapid startup again, and further solving the technical problem of high power consumption when the domain controller is in hibernation.

According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the above method when running.

According to yet another aspect of an embodiment of the present invention, a processor is provided, and the processor is used to run a program, wherein the program is configured to execute the above method when running.

According to another aspect of an embodiment of the present invention, a vehicle is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the method through the computer program.

The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims (10)

1. A method for controlling standby of a domain controller, the method comprising:

periodically detecting whether the whole vehicle controller sends out a whole vehicle dormancy signal;

Generating a first control instruction, a second control instruction and a third control instruction under the condition that the whole vehicle dormancy signal is received;

controlling a system-in-chip in the domain controller to suspend program execution based on the first control instruction and storing an execution result of the system-in-chip at the current moment into a dynamic random access memory;

Controlling a data gate in the domain controller to switch a reset mode of the dynamic random access memory from an initial mode to a target mode based on the second control instruction, wherein in the initial mode, a reset signal of the dynamic random access memory is controlled by the system-in-chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by a micro control unit in the domain controller;

and controlling a power management circuit to execute power-down operation on the system-in-chip based on the third control instruction.

2. The method of claim 1, wherein after controlling a power management circuit to perform a down current pass on the system on chip based on the third control instruction, the method further comprises:

and storing standby information of the system-in-chip into the micro control unit, wherein the standby information comprises a standby mode.

3. The method of claim 1, wherein after controlling a power management circuit to perform a down current pass on the system on chip based on the third control instruction, the method further comprises:

Periodically detecting whether the whole vehicle controller sends out a whole vehicle wake-up signal;

Generating a fourth control instruction and a fifth control instruction under the condition that the whole vehicle wake-up signal is obtained;

controlling the power management circuit to execute a current-up process on the system-on-chip based on the fourth control instruction;

And controlling the data gate to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction.

4. A method according to claim 3, characterized in that after obtaining the wake-up signal of the whole vehicle, the method comprises:

Acquiring whether a previous power-off process of the wake-up process is legal or not from the micro control unit;

And if so, generating the fifth control instruction.

5. A method according to claim 3, wherein after controlling the data strobe to switch the reset mode of the dynamic random access memory from the target mode to the initial mode based on the fifth control instruction, the method comprises:

and controlling the system-in-chip to read the execution result and the information of the program to be executed in the dynamic random access memory from the dynamic random access memory.

6. The method according to claim 5, wherein after controlling the system on chip to read the execution result and program information to be executed in the dynamic random access memory from the dynamic random access memory, the method comprises:

And controlling a power management circuit to execute a power-up current process on other devices in the domain controller.

7. A control apparatus for standby of a domain controller, comprising:

the acquisition module is used for periodically detecting whether the whole vehicle controller sends out a whole vehicle dormancy signal;

the generation module is used for generating a first control instruction, a second control instruction and a third control instruction under the condition that the whole vehicle dormancy signal is received;

The first control module is used for controlling a system-level chip in the domain controller to suspend program execution based on the first control instruction and storing an execution result of the system-level chip at the current moment into a dynamic random access memory;

The second control module is used for controlling the data strobe in the domain controller to switch the reset mode of the dynamic random access memory from an initial mode to a target mode based on the second control instruction, wherein in the initial mode, the reset signal of the dynamic random access memory is controlled by the system-in-chip, and in the target mode, the reset signal of the dynamic random access memory is controlled by the micro control unit in the domain controller;

and the third control module is used for controlling the power supply management circuit to execute the power-down operation on the system-in-chip based on the third control instruction.

8. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored program, wherein the program when run controls a device in which the computer readable storage medium is located to perform the method according to any one of claims 1 to 6.

9. A processor, characterized in that the processor is adapted to run a program, wherein the program is arranged to execute the method of any of the claims 1 to 6 at run-time.

10. A vehicle comprising a memory and a processor, wherein the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of claims 1 to 6.