CN118759498A - A fast TDC measurement system and method based on differential carry chain - Google Patents

Abstract

The present invention discloses a fast TDC measurement system and method based on a differential carry chain, which belongs to the field of laser radar flight time measurement technology, including a coarse counting unit, a fine counting unit, a counting calibration unit and a data combination, a storage and transmission unit; the fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit and a Fast double-edge counting unit; the ring oscillator is composed of a carry chain, a NOT gate and an AND gate. The present invention adopts the above-mentioned fast TDC measurement system and method based on a differential carry chain, which can effectively reduce the number of oscillations of the ring oscillator, improve the measurement accuracy of the fine counting unit and effectively shorten the conversion time.

Description

A fast TDC measurement system and method based on differential carry chain

Technical Field

The present invention relates to the technical field of laser radar flight time measurement, and in particular to a fast TDC measurement system and method based on a differential carry chain.

Background Art

In the prior art, high-precision time measurement is of great significance in the field of laser radar, which can sense the azimuth and distance by measuring the round-trip time of laser pulses. Commonly used time measurement methods include ASIC-TDC design method and FPGA-TDC design method. The ASIC-TDC method has a slow interface reading speed and a long development cycle during the design process, while the FPGA-based design method has low cost, more resources can be deployed, and the time to complete a measurement is relatively short, and the measurable laser point frequency is relatively high.

Common methods used in FPGA-based design methods include the fast carry chain method, which uses a tapped delay line to obtain sub-nanosecond resolution. By determining the high and low level jump positions of the thermometer code, the corresponding measurement time can be solved according to the delay time of a single carry chain. However, this method is restricted by the basic delay time of the internal delay structure, especially the minimum delay unit, and is affected by the uneven distribution of delays. The measurement error is relatively large and the required logic resources are relatively large.

In order to further improve the resolution and accuracy of the TDC implemented in the FPGA, a vernier delay line or a vernier ring oscillator can be used to implement a TDC with sub-gate resolution. The resolution of the above method is determined by the difference in delay time between the two delay units, and is not limited by the internal delay structure. However, this method has the main problems of a short measurable time range, a large number of oscillations leading to reduced accuracy, and a relatively long TDC conversion time.

Summary of the invention

The object of the present invention is to provide a fast TDC measurement system and method based on a differential carry chain, which can reduce the number of oscillations of a ring oscillator and improve the measurement accuracy and conversion time of fine counting units.

To achieve the above object, the present invention provides a fast TDC measurement system based on a differential carry chain, comprising a coarse counting unit, a fine counting unit, a counting calibration unit and a data combination, storage and transmission unit;

The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit and a Fast double-edge counting unit; the ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, a NOT gate and an AND gate; the input end of the AND gate of the slow loop part is connected to the input and output ends of the pulse shaping unit and the reverse input end of the oscillation signal of the slow loop part, and the input end of the AND gate of the fast loop part is connected to the input and output ends of the clock synchronization unit and the reverse input end of the oscillation signal of the fast loop part.

Preferably, the coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter, the low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter.

Preferably, the pulse shaping unit is composed of a single-level D flip-flop, the clock input terminal of the D flip-flop is connected to the echo start or stop pulse signal, the data input terminal is connected to the high level, and the data clear terminal clrn is connected to the reverse output terminal real_locked of the double-edge phase detector.

Preferably, the clock synchronization unit is a three-bit shift register structure, including a first-level D flip-flop, a second-level D flip-flop and a third-level D flip-flop; wherein, the clock input terminal of the first-level D flip-flop is connected to the echo start or stop pulse signal, the data input terminal is connected to the high level, and the data clear terminal clrn is connected to the reverse output terminal real_locked of the double-edge phase detector; the clock input terminal of the second-level D flip-flop is connected to the system clock signal, and the data input terminal is connected to the data output terminal of the first-level D flip-flop; the clock input terminal of the third-level D flip-flop is connected to the system clock signal, and the data input terminal is connected to the data output terminal of the second-level D flip-flop.

Preferably, the fast loop part and the slow loop part are composed of structural carry chains with different delay times, and the period of the slow loop part is greater than the period of the fast loop part.

Preferably, the double edge phase detector is composed of a rising edge-rising edge coincidence detection part and a rising edge-falling edge coincidence detection part;

The rising edge-rising edge coincidence detection part is composed of two stages of D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first stage D flip-flop, and the data input and clock input of the second stage D flip-flop. The first stage D flip-flop and the second stage D flip-flop are output through the AND gate after passing through the delay unit.

The rising edge-falling edge coincidence detection part is also composed of two stages of D flip-flops. The outputs of the fast loop part and the slow loop part are the reverse clock input and data input of the first stage D flip-flop, and the data input and reverse clock input of the second stage D flip-flop. The first stage D flip-flop and the second stage D flip-flop are output through the AND gate after passing through the delay unit.

The output ends of the AND gate of the rising edge-rising edge coincidence detection part and the AND gate of the rising edge-falling edge coincidence detection part are output through the OR gate.

Preferably, the feedback count latch is composed of a D flip-flop, the data input terminal is connected to a high level, and the clock input terminal is connected to the output terminal of the double-edge phase detector; the reverse output of the feedback count latch is connected to the pulse shaping unit and the clock synchronization unit.

Preferably, the structures of the Slow double-edge counting unit and the Fast double-edge counting unit are the same as the coarse counting unit.

A fast TDC measurement method based on a differential carry chain comprises the following steps:

S1, the echo start pulse signal is first converted into a single-edge signal by the pulse shaping unit, driving the slow loop oscillation loop to oscillate, and the Slow double-edge counting unit starts to count the rising and falling edges of the slow loop. After that, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, driving the fast loop oscillation loop to oscillate, and the Fast double-edge counting unit starts to count the rising and falling edges of the fast loop.

S2, the clock synchronization signal of the echo start pulse signal is detected, and the coarse counting unit starts counting the rising edge of the system clock;

S3, the double-edge phase detector detects the rising edge-rising edge or rising edge-falling edge coincidence moment of the fast loop part and the slow loop part, and outputs a high level to the feedback count latch; the feedback count latch outputs the first rising edge of the extracted multi-edge signal;

S4, when the Slow double-edge counting unit and the Fast double-edge counting unit detect the rising edge of the latch signal, they stop counting; when the pulse shaping unit and the clock synchronization unit detect the reverse output of the latch signal, they trigger the data clearing terminal clrn of the D flip-flop, pull down the output level, and wait for the next measurement input;

S5, after the counting data is calibrated, it enters the data combination, storage and transmission unit, outputs the Start part fine counting unit measurement completion flag signal, all counting units enter the zero state, and wait for the next Stop part fine counting unit to measure;

S6, the echo stop pulse signal is the same as the echo start pulse signal, and steps S1-S5 are repeated;

S7, the clock synchronization signal of the echo stop pulse signal is detected, and the coarse counting unit stops counting;

S8. Combine the measurement result of a coarse counting unit and the measurement results of the Start and Stop fine counting units to complete a time measurement. The result expression is:

T _coarse = N _coarse T _{sys_clk}

T＝T _coarse +T _{start_fine} -T _{stop_fine}

Wherein, T _{sys_clk} , T _{slow_ro} and T _{fast_ro} represent the oscillation cycle time of the system clock, the slow loop part and the fast loop part respectively; T is the flight time of the overall measurement, representing the measurement result of data combination, storage and transmission, T _coarse is the main part time of the wide range time measured by the coarse counting unit, T _{start_fine} and T _{stop_fine} represent the start fine time and stop fine time of the remaining edge part of the measurement time respectively; N _coarse represents the count value of the coarse counting unit, N _{slow_start} and N _{fast_start} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo start pulse signal respectively, and N _{slow_stop} and N _{fast_stop} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo stop pulse signal respectively;

S9, repeat steps S1-S8 to measure the flight time in a continuous cycle.

Therefore, the beneficial effects of the fast TDC measurement system and method based on the differential carry chain of the present invention are as follows:

(1) Compared with the traditional differential structure using a single D flip-flop to enable counting, the present invention can increase the measurement range of fine counting units that can be measured, and can handle the measurement range exceeding an integer number of oscillation clock cycles.

(2) The resolution of the differential carry chain structure is improved to 51 ps compared to the dedicated carry chain method.

(3) The oscillation frequency of the ring oscillator can be significantly reduced, and the measurement accuracy of the fine counting unit can be improved to 48ps.

(4) The maximum codes of the double-edge detection counting results output by the fast loop part and the slow loop part are 86 and 88 respectively, and the maximum measurement time of the fine counting unit is half a cycle of the slow loop part. Compared with the differential carry chain method with the same resolution using a common phase detector structure, the maximum relative conversion time is reduced by 50%. And as the loop oscillation frequency decreases, the actual conversion time will be further reduced.

The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of a fast TDC measurement system based on a differential carry chain according to the present invention;

2 is a circuit diagram of a clock synchronization unit and a pulse shaping unit of a fast TDC measurement system based on a differential carry chain according to the present invention;

3 is a circuit diagram of a double-edge phase detector structure of a fast TDC measurement system based on a differential carry chain according to the present invention;

FIG4 is a schematic diagram of a double-edge phase detection process;

FIG5 is a diagram of a fine counting unit code density test;

FIG6 is a differential nonlinearity diagram;

FIG7 is a graph of integral nonlinearity;

FIG8 is a graph showing time measurement accuracy.

DETAILED DESCRIPTION

The technical solution of the present invention is further described below through the accompanying drawings and embodiments.

Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Embodiment 1

As shown in FIG1 , the present invention provides a fast TDC measurement system based on a differential carry chain, including a coarse counting unit, a fine counting unit, a counting calibration unit and a data combination, storage and transmission unit;

The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit and a Fast double-edge counting unit.

Among them, the coarse counting unit is used to measure the main part of the wide range of time. The coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter. The low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter. The counting result of the coarse counting unit is the sum of the two parts, and the result is expressed as:

N＝ _NH ＜＜2+ _NL

The fine counting unit is used to measure the remaining edge portion, which constitutes the fine time measurement portion of the time measurement result.

The pulse shaping unit converts the input echo start or stop pulse signal into a start single edge signal, which is used to start the slow loop part to generate oscillation.

The clock synchronization unit is used to obtain a single edge signal for the fine counting unit to stop counting, and is also used as a start measurement signal or a stop measurement signal for the coarse counting unit.

As shown in FIG2(a), a general clock synchronization unit and a pulse shaping unit use M delay buffers to make the phase difference between the start signal and the stop signal less than 180°, which is used to offset the delay time introduced by the two D flip-flops. The present invention designs a new pulse shaping unit and a clock synchronization unit based on FIG2(a). The clock synchronization unit used is a three-bit shift register structure, and the input is a high-frequency clock signal and an echo start or stop pulse signal. The clock input end of the first-stage D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to the high level, and the data clear end clrn is connected to the reverse output end real_locked of the double-edge phase detector. The clock input end of the second-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the first-stage D flip-flop. The clock input end of the third-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the second-stage D flip-flop.

The pulse shaping unit consists of a D flip-flop and a delay unit. The clock input of the D flip-flop is connected to the echo start or stop pulse signal, and the data input is connected to a high level to convert the pulse signal into a single-edge signal that can form an oscillating output. The data clear terminal clrn is connected to the reverse output terminal real_locked of the double-edge phase detector.

The advantage of structure (b) of the present invention over structure (a) is that there is no need to repeatedly adjust the delay level to determine the specific size of M, and there is no need to consider the excess delay time caused by N triggers, which facilitates overall system adjustment.

The ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, a NOT gate and an AND gate. The input end of the AND gate of the slow loop part is connected to the input and output end of the pulse shaping unit and the reverse input end of the oscillation signal of the slow loop part, and the input end of the AND gate of the fast loop part is connected to the input and output end of the clock synchronization unit and the reverse input end of the oscillation signal of the fast loop part. The fast loop part and the slow loop part are composed of a carry chain with different delay times, and the period of the slow loop part is greater than the period of the fast loop part.

The double edge phase detector is used to output the phase synchronization signal of the fast loop part and the slow loop part. The double edge phase detector needs to detect the coincidence moment of the rising edge of the fast loop part and the slow loop part, and also needs to detect the coincidence moment of the rising edge of the fast loop part and the falling edge of the slow loop part.

Assume that the initial phase difference between the fast loop and the slow loop is and The frequencies of the slow loop and the fast loop are _fs and _fk respectively. _2ncπ corresponds to the time difference of the slow clock _{ncTs .} By the double-edge phase detector, when the rising edge of the fast clock and the slow clock are aligned, the fast clock _nk counts as:

Assume that the initial phase difference between the fast loop and the slow loop is and Then the fast clock n _k count is:

For an uncompensated ring oscillator, the rms error σ increases in proportion to the square root of the total number of oscillations n.

In the above formula, σ is the root mean square error of the system measurement, ΔT represents the time interval to be measured, res is the system resolution, and T _ro is the oscillation period of the oscillator. It can be seen from the above formula that shortening the time interval to be measured will reduce the root mean square error of the system measurement.

According to the characteristics of the double-edge phase detector, the maximum counting result of the fast loop part is:

It can be seen from the above formula that the double-edge phase detector can reduce the number of oscillations of n to half of the original, which not only effectively reduces the root mean square error, but also reduces the overall measurement time.

The double edge phase detector consists of a rising edge-rising edge coincidence detection part and a rising edge-falling edge coincidence detection part, specifically:

The rising edge-rising edge coincidence detection part is composed of two stages of D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first stage D flip-flop, and the data input and clock input of the second stage D flip-flop. The first stage D flip-flop and the second stage D flip-flop are output through the AND gate after passing through the delay unit. When the rising edges of the fast loop part and the slow loop part coincide, the AND gate output is high, indicating that the phase difference between the fast loop part and the slow loop part is 0° after phase shifting.

The rising edge-falling edge coincidence detection part is also composed of two-stage D flip-flops. The output of the fast loop part and the slow loop part is the reverse clock input and data input of the first-stage D flip-flop, and the data input and reverse clock input of the second-stage D flip-flop. The first-stage D flip-flop and the second-stage D flip-flop are output through the AND gate after passing through the delay unit. When the rising edge of the fast loop part and the falling edge of the slow loop part coincide, the AND gate output is high, indicating that the phase difference between the fast loop and the slow loop is 180° after phase shifting.

The outputs of the AND gate of the rising-rising edge coincidence detection part and the AND gate of the rising-falling edge coincidence detection part are output through the OR gate. When the OR gate output is high, it means that the phase detection is completed, and the phase difference between the fast loop part and the slow loop part is 0° or 180°.

The Slow double edge counting unit and the Fast double edge counting unit have the same structure as the coarse counting unit, and are used to count the number of double edges in the slow loop part and the fast loop part respectively. Their structures are divided into rising edge counter and falling edge counter. Both the rising edge counter and the falling edge counter are double cascade structures, and the sum of the two is the output of the double edge counting result.

The feedback count latch is used to output the counting stop signal of the Slow double edge counting unit and the Fast double edge counting unit. The feedback count latch is composed of a single D flip-flop, the data input terminal is high level, and the clock input signal is connected to the output of the double edge phase detector. Since the output of the double edge phase detector may be a multi-pulse signal, after passing through the feedback count latch, only the first rising edge of the output of the double edge phase detector is extracted as the final latch signal. At the same time, the reverse output of the feedback count latch is connected to the pulse shaping unit and the clock synchronization unit. Once it enters the latch state, the ring oscillation is stopped immediately.

The counting calibration unit is used for calibrating the data of the fine counting unit and the coarse counting unit, and the data combination, storage and transmission unit is used for outputting the overall time measurement result.

As shown in FIG3 , DFF1 and DFF2 are used to detect that the slow loop part and the fast loop part are located at a 0° synchronous position, and DFF3 and DFF4 are used to detect that the slow loop part and the fast loop part are located at a 180° synchronous position.

The clock input of DFF1 is the oscillation output of the fast loop part, and the data input is the oscillation output of the slow loop part. The clock input of DFF2 is the oscillation output of the slow loop part, and the data input is the oscillation output of the fast loop part. As shown in Figure 4(1), let the initial phase of the fast loop part and the slow loop part be and The phase detection results are shown in Table 1 below:

Table 1 Phase detection results of Q1 and Q2

Q1 Q2 Phase Relationship 1 0 Ahead of the times 1 1 Phase is at 0° synchronous 0 1 behind

When the outputs of Q1 and Q2 are ANDed through the AND gate, the output is 1, indicating that phase synchronization is achieved at point A. At this time, the count latch result output is 1, and the count results of the fast loop part and the slow loop part are latched.

The clock input of DFF3 is the reverse oscillation output of the fast loop part, and the data input is the oscillation output of the slow loop part. The clock input of DFF4 is the reverse oscillation output of the slow loop part, and the data input is the oscillation output of the fast loop part. As shown in Figure 4(2), let the initial phase of the fast loop part and the slow loop part be and The phase detection results are shown in Table 2 below: Table 2 Phase detection results of Q3 and Q4

Q3 Q4 Phase Relationship 1 0 Ahead of the times 1 1 Phase is 180° synchronous 0 1 behind

When the outputs of Q3 and Q4 are ANDed through the AND gate, the output is 1, indicating that phase synchronization is achieved at point B. At this time, the count latch result output is 1, and the count results of the fast loop part and the slow loop part are latched.

As shown in FIG3 , the delay units τ ₁ and τ ₂ in the double-edge phase detector are used to adjust the phase detection output and shape the AND gate output pulse.

As shown in Figure 4, the double-edge phase detector outputs the phase position through an OR gate. First, the output phase is at the 0° synchronous position; when When the output phase is 180° synchronous, the time interval to be measured can be controlled within half a cycle.

The input of the feedback count latch is the output of the double-edge phase detector. Since the double-edge phase detector may have multiple phase synchronization positions, it is necessary to use the feedback count latch to output only the first rising edge position as the final phase detection result. When the data combination is completed and the transmission unit timing result is stored, the feedback count latch is reset.

The present invention also provides a fast TDC measurement method based on a differential carry chain, comprising the following steps:

S1, the echo start pulse signal is first converted into a single-edge signal by the pulse shaping unit, driving the slow loop oscillation loop to oscillate, and the Slow double-edge counting unit starts to count the rising and falling edges of the slow loop. After that, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, driving the fast loop oscillation loop to oscillate, and the Fast double-edge counting unit starts to count the rising and falling edges of the fast loop.

S2, the clock synchronization signal of the echo start pulse signal is detected, and the coarse counting unit starts counting the rising edge of the system clock;

S3, the double-edge phase detector detects the rising edge-rising edge or rising edge-falling edge coincidence moment of the fast loop part and the slow loop part, and outputs a high level to the feedback count latch; the feedback count latch outputs the first rising edge of the extracted multi-edge signal;

S4, when the Slow double-edge counting unit and the Fast double-edge counting unit detect the rising edge of the latch signal, they stop counting; when the pulse shaping unit and the clock synchronization unit detect the reverse output of the latch signal, they trigger the data clearing terminal clrn of the D flip-flop, pull down the output level, and wait for the next measurement input;

S5, after the counting data is calibrated, it enters the data combination, storage and transmission unit, outputs the Start part fine counting unit measurement completion flag signal, all counting units enter the zero state, and wait for the next Stop part fine counting unit to measure;

S6, the echo stop pulse signal is the same as the echo start pulse signal, and steps S1-S5 are repeated;

S7, the clock synchronization signal of the echo stop pulse signal is detected, and the coarse counting unit stops counting;

S8. Combine the measurement result of a coarse counting unit and the measurement results of the Start and Stop fine counting units to complete a time measurement. The result expression is:

T _coarse = N _coarse T _{sys_clk}

T＝T _coarse +T _{start_fine} -T _{stop_fine}

Wherein, T _{sys_clk} , T _{slow_ro} and T _{fast_ro} represent the oscillation cycle time of the system clock, the slow loop part and the fast loop part respectively; T is the flight time of the overall measurement, representing the measurement result of data combination, storage and transmission, T _coarse is the main part time of the wide range time measured by the coarse counting unit, T _{start_fine} and T _{stop_fine} represent the start fine time and stop fine time of the remaining edge part of the measurement time respectively; N _coarse represents the count value of the coarse counting unit, N _{slow_start} and N _{fast_start} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo start pulse signal respectively, and N _{slow_stop} and N _{fast_stop} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo stop pulse signal respectively;

S9, repeat steps S1-S8 to measure the flight time in a continuous cycle.

In this embodiment, the present invention is implemented in Altera FPGA, and the design tools are Quartus II 15.0 version and Modelsim 10.7 version. The Quartus software provided by Altera includes LogicLock logic locking function design, TIMEQuest timing analysis tool, and can use Assignment editor to perform location constraints on related structures, and the specific layout content can be viewed in Chip Planner. Similarly, the relevant principles of this solution can also be implemented through other models of FPGA design such as Xilinx.

The specific implementation steps are as follows:

(1) In order to obtain two oscillation loops with similar frequencies, the differences in carry chain structure characteristics are utilized or different delay chain structure series are constructed to obtain stable oscillation loops with similar frequencies.

(2) Build a specific TDC design according to the structure shown, and use tools such as ChipPlanner to design a specific circuit.

(3) Use a signal generator or the internal phase-locked loop of the FPGA to generate a stable square wave signal, input it to the stop/start port, and connect it to an oscilloscope to test and observe whether a stable oscillation loop is formed. Determine the oscillation frequencies of the fast loop and the slow loop as _fs and _fk , and obtain the oscillation period of the slow loop as _Ts .

(4) A large number of random pulse signals are used to simulate the starting signal, and the number of samples is set to 200,000 times. The distribution of the counting results of the fine counting units in the fast loop is shown in FIG5 .

(5)

(6) The resolution of the fast loop is calculated by the formula as 2218 (half cycle of the slow loop)/43 (distribution level) = 51.6ps. In fact, the statistical result shows that the rising edge of the fast loop coincides with the rising edge or falling edge of the slow loop, so the statistical count of the fast loop presents the characteristics of odd number distribution. To facilitate time calibration, the count of the fast loop is compressed to _N'k , and the relationship between the compressed count value and the original count value _Nk satisfies

(7) The differential nonlinearity and integral nonlinearity of the fast loop part are shown in Figures 6 and 7. The experimental results show that the time stamp results measured by the ring carry chain TDC circuit based on the fine delay phase shift structure of the present invention are both within the range of (-0.5LSB, 0.5LSB). Compared with the tapped TDC circuit, the DNL and INL results obtained by the present invention are relatively low. Since the oscillation number range of the TDC of this structure is 86, it is 43 after compression.

(8) Constructing a lookup table structure. Similarly, the fast loop part of the stop part is obtained by the same method as above, and a lookup table structure is also established for the stop part to calibrate each level of fine counting unit.

(9) Independently establish a multi-stage carry chain structure and adjust the number of carry chain stages to use as a precision measurement delay line, and obtain delay times of 5 ns and 10 ns for this test.

(10) As shown in Figure 8, the average time of the time delay at about 5ns is 5.14ns, and the variance is 48.2ps. The average time of the time delay at 10ns is 10.36ns, and the variance is 49.6ps. The result obtained by using the double-edge phase detector structure is 48ps. The RMS accuracy of the phase detector structure is about 70ps when the phase detector structure is changed to only use a single-edge phase detector. In comparison, the improvement effect of the double-edge phase detector structure is significantly improved.

(11) The ring carry chain TDC circuit based on fine delay phase shift measurement proposed in the present invention can reduce the maximum number of oscillation cycles and the count value of the fine counting unit by half, thereby significantly reducing the RMS error and improving the resolution. It can be seen from the experimental results that this circuit structure improves the accuracy from 70ps to 48ps, and has good integral nonlinearity and differential nonlinearity. The present invention can be widely used in high-precision time interval measurement and related fields.

Therefore, the present invention adopts the above-mentioned fast TDC measurement system and method based on differential carry chain, which can effectively reduce the number of oscillations of the ring oscillator and improve the measurement accuracy and conversion time of the fine counting unit.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims (9)

1. A fast TDC measurement system based on differential carry chain, characterized by: comprising a coarse counting unit, a fine counting unit, a counting calibration unit and a data combination, storage and transmission unit; The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit and a Fast double-edge counting unit; the ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, a NOT gate and an AND gate; the input end of the AND gate of the slow loop part is connected to the input and output ends of the pulse shaping unit and the reverse input end of the oscillation signal of the slow loop part, and the input end of the AND gate of the fast loop part is connected to the input and output ends of the clock synchronization unit and the reverse input end of the oscillation signal of the fast loop part. 2. A fast TDC measurement system based on differential carry chain according to claim 1, characterized in that: the coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter, the low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter. 3. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: the pulse shaping unit is composed of a single-level D flip-flop, the clock input end of the D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to the high level, and the data clear end clrn is connected to the reverse output end real_locked of the double-edge phase detector. 4. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: the clock synchronization unit is a three-bit shift register structure, including a first-stage D flip-flop, a second-stage D flip-flop and a third-stage D flip-flop; wherein the clock input end of the first-stage D flip-flop is connected to an echo start or stop pulse signal, the data input end is connected to a high level, and the data clear end clrn is connected to the reverse output end real_locked of the double-edge phase detector; the clock input end of the second-stage D flip-flop is connected to a system clock signal, and the data input end is connected to a data output end of the first-stage D flip-flop; the clock input end of the third-stage D flip-flop is connected to a system clock signal, and the data input end is connected to a data output end of the second-stage D flip-flop. 5. A fast TDC measurement system based on differential carry chain according to claim 1, characterized in that: the fast loop part and the slow loop part are composed of structural carry chains with different delay times, and the period of the slow loop part is greater than the period of the fast loop part. 6. A fast TDC measurement system based on differential carry chain according to claim 1, characterized in that: the double edge phase detector is composed of a rising edge-rising edge coincidence detection part and a rising edge-falling edge coincidence detection part; The rising edge-rising edge coincidence detection part is composed of two stages of D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first stage D flip-flop, and the data input and clock input of the second stage D flip-flop. The first stage D flip-flop and the second stage D flip-flop are output through the AND gate after passing through the delay unit. The rising edge-falling edge coincidence detection part is also composed of two stages of D flip-flops. The outputs of the fast loop part and the slow loop part are the reverse clock input and data input of the first stage D flip-flop, and the data input and reverse clock input of the second stage D flip-flop. The first stage D flip-flop and the second stage D flip-flop are output through the AND gate after passing through the delay unit. The output ends of the AND gate of the rising edge-rising edge coincidence detection part and the AND gate of the rising edge-falling edge coincidence detection part are output through the OR gate. 7. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: the feedback count latch is composed of a D flip-flop, the data input terminal is connected to a high level, and the clock input terminal is connected to the output terminal of the double-edge phase detector; the reverse output of the feedback count latch is connected to the pulse shaping unit and the clock synchronization unit. 8 . The fast TDC measurement system based on differential carry chain according to claim 1 , wherein the structure of the Slow double edge counting unit and the Fast double edge counting unit is the same as that of the coarse counting unit. 9. A fast TDC measurement method based on differential carry chain, characterized by comprising the following steps: S1, the echo start pulse signal is first converted into a single-edge signal by the pulse shaping unit, driving the slow loop oscillation loop to oscillate, and the Slow double-edge counting unit starts to count the rising and falling edges of the slow loop. After that, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, driving the fast loop oscillation loop to oscillate, and the Fast double-edge counting unit starts to count the rising and falling edges of the fast loop. S2, the clock synchronization signal of the echo start pulse signal is detected, and the coarse counting unit starts counting the rising edge of the system clock; S3, the double-edge phase detector detects the rising edge-rising edge or rising edge-falling edge coincidence moment of the fast loop part and the slow loop part, and outputs a high level to the feedback count latch; the feedback count latch outputs the first rising edge of the extracted multi-edge signal; S4, when the Slow double-edge counting unit and the Fast double-edge counting unit detect the rising edge of the latch signal, they stop counting; when the pulse shaping unit and the clock synchronization unit detect the reverse output of the latch signal, they trigger the data clearing terminal clrn of the D flip-flop, pull down the output level, and wait for the next measurement input; S5, after the counting data is calibrated, it enters the data combination, storage and transmission unit, outputs the Start part fine counting unit measurement completion flag signal, all counting units enter the zero state, and wait for the next Stop part fine counting unit to measure; S6, the echo stop pulse signal is the same as the echo start pulse signal, and steps S1-S5 are repeated; S7, the clock synchronization signal of the echo stop pulse signal is detected, and the coarse counting unit stops counting; S8. Combine the measurement result of a coarse counting unit and the measurement results of the Start and Stop fine counting units to complete a time measurement. The result expression is: T _coarse = N _coarse T _{sys_clk} T＝T _coarse +T _{start_fine} -T _{stop_fine} Wherein, T _{sys_clk} , T _{slow_ro} and T _{fast_ro} represent the oscillation cycle time of the system clock, the slow loop part and the fast loop part respectively; T is the flight time of the overall measurement, representing the measurement result of data combination, storage and transmission, T _coarse is the main part time of the wide range time measured by the coarse counting unit, T _{start_fine} and T _{stop_fine} represent the start fine time and stop fine time of the remaining edge part of the measurement time respectively; N _coarse represents the count value of the coarse counting unit, N _{slow_start} and N _{fast_start} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo start pulse signal respectively, and N _{slow_stop} and N _{fast_stop} represent the double edge count values of the double edges of the slow loop part and the fast loop part of the echo stop pulse signal respectively; S9, repeat steps S1-S8 to measure the flight time in a continuous cycle.