CN118740096B - A surface acoustic wave wafer-level structure and manufacturing method thereof, and electronic equipment - Google Patents
A surface acoustic wave wafer-level structure and manufacturing method thereof, and electronic equipment Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 claims abstract description 34
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- 239000010409 thin film Substances 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02543—Characteristics of substrate, e.g. cutting angles
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02637—Details concerning reflective or coupling arrays
- H03H9/02653—Grooves or arrays buried in the substrate
- H03H9/02661—Grooves or arrays buried in the substrate being located inside the interdigital transducers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/125—Driving means, e.g. electrodes, coils
- H03H9/145—Driving means, e.g. electrodes, coils for networks using surface acoustic waves
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- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
本申请公开了一种声表面波晶圆级结构及其制作方法、电子设备，涉及半导体技术领域，该声表面波晶圆级结构中引入封装盖板作为WLP的键合部分，通过对封装盖板做处理形成多个凸起柱，以此来形成跟衬底之间键合的目的。基于封装盖板和干膜的特性可知，封装盖板的凸起柱相比较由干膜形成的支撑坝而言，凸起柱的强度比支撑坝更强，在版图布局的过程中，凸起柱只需要在芯片四周以及有焊盘连接需求的地方存在，相比较双层干膜封装技术中的支撑坝，则无需考虑支撑问题。也就是说本技术方案在可靠性以及支撑性等方面相比较双层干膜封装技术有巨大的提升。
The present application discloses a surface acoustic wave wafer-level structure and a manufacturing method thereof, and an electronic device, and relates to the field of semiconductor technology. A packaging cover is introduced into the surface acoustic wave wafer-level structure as the bonding part of the WLP, and a plurality of raised columns are formed by processing the packaging cover to achieve the purpose of bonding with the substrate. Based on the characteristics of the packaging cover and the dry film, it can be known that the raised columns of the packaging cover are stronger than the support dam formed by the dry film. In the process of layout, the raised columns only need to exist around the chip and where there is a need for pad connection. Compared with the support dam in the double-layer dry film packaging technology, there is no need to consider the support problem. In other words, this technical solution has a huge improvement in reliability and support compared to the double-layer dry film packaging technology.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a surface acoustic wave wafer-level structure, a manufacturing method thereof and electronic equipment.
Background
The SAW (Surface Acoustic Wave ) resonator is a short term of surface acoustic wave resonator, is a special filter device made by utilizing the piezoelectric effect and the physical characteristics of surface acoustic wave propagation, and is widely applied to various fields, such as the radio frequency field. Wherein a surface acoustic wave is an elastic wave in which energy is concentrated near a surface. Where the filter is designed to use resonators as the basic unit, a corresponding topology can be constructed and the signal of the specified frequency component amplified.
In general, the surface acoustic wave filter is obtained by performing wafer level packaging of the surface acoustic wave filter on the manufactured surface acoustic wave resonator. In the related art, in the method for manufacturing the wafer level package of the surface acoustic wave filter, a first dry film layer is attached to the upper surface of the surface acoustic wave resonator, and a supporting dam is formed by etching the first dry film layer. And then attaching a second layer of dry film on the supporting dam to form a cavity of the surface acoustic wave filter.
But based on the characteristic of the dry film, the strength of the supporting dam manufactured by the first layer dry film is lower, the second layer dry film cannot be effectively supported, the second layer dry film has the bad condition of film collapse, and the packaging effect of the surface acoustic wave wafer level structure is further affected.
Disclosure of Invention
In view of the above problems, the present application provides a surface acoustic wave wafer level structure, a method for manufacturing the same, and an electronic device, so as to achieve the purpose of improving the reliability of the surface acoustic wave wafer level structure. The specific scheme is as follows:
The first aspect of the present application provides a surface acoustic wave wafer level structure comprising:
The packaging cover plate is provided with a plurality of protruding columns, and the substrate and the packaging cover plate are connected in a packaging mode through the protruding columns;
The piezoelectric thin film layer is positioned between the substrate and the packaging cover plate, is positioned on the substrate, and is positioned on one side of the piezoelectric thin film layer away from the substrate.
In one possible implementation, the package cover is a Si cover.
In one possible implementation, the saw wafer level structure further includes:
At least one dielectric layer between the piezoelectric film layer and the substrate.
In one possible implementation, the saw wafer level structure further includes:
a bonding layer located at least between the raised pillars and the substrate;
the bonding layer comprises a first bonding layer arranged adjacent to the substrate and a second bonding layer arranged adjacent to the protruding columns.
In one possible implementation, the materials of the first bonding layer and the second bonding layer are metallic materials.
In one possible implementation, the material of the first bonding layer and the second bonding layer is a gold material.
In one possible implementation, the first bonding layer is in contact with the interdigital electrode.
In one possible implementation, the substrate has a through hole that extends through the substrate;
the surface acoustic wave wafer level structure further comprises an external lead structure, wherein the external lead structure is connected with the first bonding layer through the through hole.
The second aspect of the present application provides a method for manufacturing a surface acoustic wave wafer level structure, the method for manufacturing a surface acoustic wave wafer level structure comprising:
providing a substrate, wherein a piezoelectric film layer and at least one dielectric layer positioned between the piezoelectric film layer and the substrate are arranged on the substrate;
forming interdigital electrodes on one side of the piezoelectric film layer, which is away from the substrate;
providing a packaging cover plate;
processing the packaging cover plate to form a plurality of protruding columns;
and packaging and connecting the substrate and the packaging cover plate through the plurality of protruding columns.
A third aspect of the present application provides an electronic device comprising a saw wafer level structure as described in any one of the preceding claims.
By means of the technical scheme, the surface acoustic wave wafer level structure, the manufacturing method thereof and the electronic equipment provided by the application have the advantages that the packaging cover plate is introduced to serve as a bonding part of WLP (WAFER LEVEL PACKAGE, wafer level packaging), and a plurality of protruding columns are formed by processing the packaging cover plate, so that the purpose of bonding with a substrate is achieved. Based on the characteristics of the packaging cover plate and the dry film, compared with a supporting dam formed by the dry film, the strength of the protruding column of the packaging cover plate is stronger than that of the supporting dam, and in the process of layout, the protruding column only needs to exist around a chip and in a place with a bonding pad connection requirement. That is to say, the technical scheme has great improvement in the aspects of reliability, supportability and the like compared with the double-layer dry film packaging technology.
Drawings
The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale.
Fig. 1 is a schematic structural diagram of a surface acoustic wave wafer level structure according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of an interdigital electrode according to an embodiment of the present invention;
Fig. 3 is a schematic flow chart of a method for manufacturing a surface acoustic wave wafer level structure according to an embodiment of the present invention;
Fig. 4 to 16 are schematic views of a portion of the saw wafer level structure shown in fig. 3 corresponding to the method for manufacturing the saw wafer level structure.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application.
Embodiments of the present application are described below with reference to the accompanying drawings. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.
In combination with the description of the background technology, the surface acoustic wave resonator and the filter are acoustic devices widely applied to the radio frequency field, integrate low insertion loss and good inhibition performance, have smaller volume, are used for filtering interference of different-frequency signals, attenuate partial frequency components, only enable specified frequency components, and are the technical basis for applying a wireless spectrum as a non-renewable scarce resource. The specific principle can be simply understood as that based on the piezoelectric characteristics of piezoelectric materials, the input and output transducer devices such as interdigital transducers are utilized to convert electric signals into mechanical energy, and the mechanical energy is converted into electric signals after being processed, so that the effects of amplifying required signals, filtering out impurity signals and improving signal quality are achieved, and the piezoelectric transducer is widely applied to various wireless communication equipment.
Currently, filters are largely classified into SAW filters and BAW (Bulk Acoustic Wave ) filters, in which a surface acoustic wave is an elastic wave that is generated and propagates on the surface of a piezoelectric substrate having piezoelectric characteristics, and whose amplitude rapidly decreases with increasing depth into the piezoelectric substrate. For the SAW filter, the manufacturing cost is much lower than that of the BAW filter, and the SAW filter is applied to a low frequency band, has low insertion loss, good inhibition and temperature sensitivity.
Meanwhile, it should be noted that, the SAW filter has a corresponding limitation in that it is susceptible to temperature change, when the temperature increases, the rigidity of the base material tends to decrease, and the sound velocity also decreases, which is also known as a defect that the SAW filter has a temperature drift, i.e. the frequency drift with the operating temperature, so that, based on the conventional SAW filter, a TC-SAW filter, i.e. a temperature compensation type SAW filter, is correspondingly generated, and the compensation of the temperature drift characteristic is realized mainly by using the temperature elastic characteristic of the temperature compensation layer (e.g. SiO 2 layer) opposite to the piezoelectric film layer.
Further, SAW filters are also designed for products such as TF-SAW filters (thin film surface acoustic wave filters), and the filters are often designed using resonators as basic units, so that the signals of specified frequency components can be amplified and formed in a corresponding topology.
Based on the TC-SAW resonator or the common SAW resonator or the TF-SAW resonator, the manufactured SAW resonator is packaged at the wafer level, so that the SAW filter is obtained. In the related art, in the method for manufacturing the wafer level package of the surface acoustic wave filter, a first dry film layer is attached to the upper surface of the surface acoustic wave resonator, and a supporting dam is formed by etching the first dry film layer. And then attaching a second layer of dry film on the supporting dam to form a cavity of the surface acoustic wave filter.
But based on the characteristic of the dry film, the strength of the supporting dam manufactured by the first layer dry film is lower, the second layer dry film cannot be effectively supported, the second layer dry film has the bad condition of film collapse, and the packaging effect of the surface acoustic wave wafer level structure is further affected.
The embodiment of the invention provides a surface acoustic wave Wafer level structure, a manufacturing method thereof and electronic equipment, which are mainly divided into two parts in terms of structure, namely DEVICE WAFER and Cap Wafer. The DEVICE WAFER part where the surface acoustic wave device is located is a main working area of the filter, and mainly comprises a substrate, a piezoelectric film layer, interdigital electrodes and the like, and the Cap Wafer is a structural part which is reversely buckled on DEVICE WAFER and used as a Wafer level package.
That is, in the present invention, the bonding with the substrate is performed by introducing a package cover as a bonding portion of WLP (WAFER LEVEL PACKAGE ) and forming a plurality of bump pillars by processing the package cover. At the same time, jin Jinjian can be introduced to bond the upper and lower wafers. Based on the characteristics of the packaging cover plate and the dry film, compared with a supporting dam formed by the dry film, the strength of the protruding column of the packaging cover plate is stronger than that of the supporting dam, and in the process of layout, the protruding column only needs to exist around a chip and in a place with a bonding pad connection requirement. That is to say, the technical scheme has great improvement in the aspects of reliability, supportability and the like compared with the double-layer dry film packaging technology.
It should be noted that the SAW wafer level structure provided in the embodiment of the present invention includes, but is not limited to, a wafer level structure of a common SAW resonator, a wafer level structure of a TC-SAW resonator, or a wafer level structure of a TF-SAW resonator, that is, the technical solution provided in the embodiment of the present invention may be applied to a common SAW resonator, a TC-SAW resonator, or a TF-SAW resonator, and in the embodiment of the present invention, only application to a TF-SAW resonator is described as an example.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a surface acoustic wave wafer level structure according to an embodiment of the present invention, where the surface acoustic wave wafer level structure according to the embodiment of the present invention includes:
the packaging cover plate 11 is provided with a plurality of protruding columns 13, and the substrate 11 and the packaging cover plate 12 are connected in a packaging mode through the plurality of protruding columns 13.
A piezoelectric film layer 14 located between the substrate 11 and the package cover 12 and on the substrate 11, and an interdigital electrode 15 located on a side of the piezoelectric film layer 14 facing away from the substrate 11.
Specifically, in the embodiment of the present invention, the package cover 12 may be a Si cover, that is, the package cover 12 may be processed from a Si wafer, referring to fig. 2, fig. 2 is a schematic structural diagram of an interdigital electrode provided in the embodiment of the present invention, where the interdigital electrode 15 includes a bus bar and an electrode finger bar, the bus bar includes a first bus bar 151 and a second bus bar 152 disposed opposite to each other in a first direction X, the electrode finger bar includes a first electrode finger 153 disposed on the first bus bar 151 and a second electrode finger 154 disposed on the second bus bar 152, the length extension directions of the first bus bar 151 and the second bus bar 152 are the same, and both extend along a second direction Y, and the first direction X and the second direction Y are parallel to a plane on which the substrate 11 is located, and the first direction X and the second direction Y intersect.
The length extending directions of the first electrode finger 153 and the second electrode finger 154 are parallel to the first direction X, the first electrode finger 153 on the first bus bar 151 is arranged at intervals in the second direction Y, the second electrode finger 154 on the second bus bar 152 is arranged at intervals in the second direction Y, the first electrode finger 153 on the first bus bar 151 and the second electrode finger 154 on the second bus bar 152 are sequentially arranged in a crossing manner in the second direction Y, and intervals are arranged between the first electrode finger 153 and the second bus bar 152 on the first bus bar 151, and intervals are arranged between the second electrode finger 154 and the first bus bar 151 on the second bus bar 152, and at this time, the bus bars and the electrode finger are distributed in a similar finger crossing manner to form a so-called interdigital electrode 15. When the first bus bar 151 and the first electrode finger 153 thereon are used as the transmitting end, the second bus bar 152 and the second electrode finger 154 thereon are used as the receiving end, whereas when the first bus bar 151 and the first electrode finger 153 thereon are used as the receiving end, the second bus bar 152 and the second electrode finger 154 thereon are used as the transmitting end. The transmitting end part is used for converting the electric signal into sound waves, the sound waves mainly propagate on the surface of the piezoelectric film layer, and the receiving end part is used for converting the received sound waves into electric signals to be output, so that filtering is realized.
The SAW Wafer level structure is mainly divided into two parts in terms of structure, namely DEVICE WAFER and Cap Wafer. The DEVICE WAFER part where the surface acoustic wave device is located is a main working area of the filter, and mainly comprises a substrate, a piezoelectric film layer, interdigital electrodes and the like, and the Cap Wafer is a structural part which is reversely buckled on DEVICE WAFER and used as a Wafer level package.
That is, in the embodiment of the present invention, the package cover 12 is introduced as a bonding portion of WLP (WAFER LEVEL PACKAGE ), and a plurality of bump pillars 13 (when the package cover is a Si cover, the bump pillars 13 are bump silicon pillars) are formed by processing the package cover 12, so that the purpose of bonding with the substrate 11 is achieved. Based on the characteristics of the package cover plate 12 and the dry film, compared with the supporting dam formed by the dry film, the strength of the protruding column 13 of the package cover plate 12 is stronger than that of the supporting dam, and in the process of layout, the protruding column 13 only needs to exist around the chip and at the place with the bonding pad connection requirement, and compared with the supporting dam in the double-layer dry film package technology, the supporting problem is not needed to be considered. That is to say, the technical scheme has great improvement in the aspects of reliability, supportability and the like compared with the double-layer dry film packaging technology.
Further, based on the dual-layer dry film packaging technology, the width of the supporting dam is generally increased to improve the strength of the supporting dam, which obviously is also unfavorable for the miniaturization design of the chip. The raised post 13 in the embodiment of the application has no problem of supporting strength, which can directly indicate that the technical scheme has great improvement in the aspect of chip miniaturization design compared with the double-layer dry film packaging technology.
In an alternative embodiment of the present invention, as shown in fig. 1, the saw wafer level structure provided in the embodiment of the present invention further includes:
at least one dielectric layer is located between the piezoelectric thin film layer 14 and the substrate 11.
Specifically, in the embodiment of the present invention, the dielectric layer between the piezoelectric film layer 14 and the substrate 11 may be any number of dielectric layers including an insertion layer, a protection layer, a regulation layer, a temperature compensation layer, a speed change layer, and the like, so as to form a Stack layer (Stack) structure, thereby achieving various different technical effects. The number and function of the dielectric layers in the embodiment of the present invention are not limited, but only two dielectric layers (i.e., the first dielectric layer 16 and the second dielectric layer 17) are provided between the piezoelectric thin film layer 14 and the substrate 11.
In an alternative embodiment of the present invention, as shown in fig. 1, the saw wafer level structure provided in the embodiment of the present invention further includes:
And a bonding layer located at least between the bump pillar 13 and the substrate 11.
The bonding layers include a first bonding layer 18 disposed adjacent the substrate 11 and a second bonding layer 19 disposed adjacent the raised stud 13.
Specifically, in the embodiment of the present invention, the materials of the first bonding layer 18 and the second bonding layer 19 are metal materials. The exemplary materials of the first bonding layer 18 and the second bonding layer 19 are gold materials, that is, in the embodiment of the present invention, the package cover 12 is introduced as a bonding portion of WLP (WAFER LEVEL PACKAGE ), and the package cover 12 is processed to form a plurality of bump pillars 13 (when the package cover is a Si cover, the bump pillars 13 are bump silicon pillars), so as to form a bond with the substrate 11. Based on the characteristics of the package cover plate 12 and the dry film, the strength of the protruding columns 13 of the package cover plate 12 is stronger than that of the supporting dam formed by the dry film, and a Jin Jinjian bonding process is further introduced as a bonding process of the upper wafer and the lower wafer in the embodiment of the invention, so that the bonding strength is further improved, and in the layout process, the protruding columns 13 only need to exist around the chip and in the places with the bonding pad connection requirements, and compared with the supporting dam in the double-layer dry film package technology, the supporting problem is not needed to be considered.
In general, the technical scheme has great improvement in the aspects of reliability, supportability and the like compared with the double-layer dry film packaging technology.
Further, as shown in fig. 1, the bonding surface of each protruding pillar 13 further has a plurality of independent small protrusions, and after bonding, a similar snap-in manner can be formed, so as to enlarge the contact surface between the first bonding layer 18 and the second bonding layer 19 as much as possible, thereby further improving the bonding effect.
In an alternative embodiment of the present invention, as shown in fig. 1, the first bonding layer 18 is in contact with the interdigital electrode 15, and the substrate 11 has a through hole 20, and the through hole 20 penetrates the substrate 11.
The saw wafer level structure further includes an external lead structure 21, where the external lead structure 21 is connected to the first bonding layer 18 through the through hole 20.
Specifically, in the embodiment of the present invention, when the first bonding layer 18 is made of a metal material, it may also be in contact with and connected to the interdigital electrode 15, and the connection between the external component or the external circuit and the saw wafer level structure is achieved by implementing the connection between the external lead structure 21 and the through hole 20 on the substrate 11, so as to achieve the required function.
For example, copper pillars or solder balls may be disposed on the external lead structure 21 to connect external components, which is not limited in the embodiment of the present invention.
Based on the foregoing embodiments of the present invention, in another embodiment of the present invention, a method for manufacturing a surface acoustic wave wafer level structure is further provided, and referring to fig. 3, fig. 3 is a schematic flow chart of a method for manufacturing a surface acoustic wave wafer level structure according to an embodiment of the present invention, where the method for manufacturing a surface acoustic wave wafer level structure according to an embodiment of the present invention includes:
S101, as shown in FIG. 4, a substrate 11 is provided, and a piezoelectric film layer 14 and at least one dielectric layer between the piezoelectric film layer 14 and the substrate 11 are disposed on the substrate 11.
Specifically, in this step, two dielectric layers (i.e., the first dielectric layer 16 and the second dielectric layer 17) are provided between the piezoelectric thin film layer 14 and the substrate 11. It should be noted that the structure shown in fig. 4 may be understood as a structure of the incoming wafer.
And S102, forming interdigital electrodes 15 on the side of the piezoelectric film layer 14, which is away from the substrate 11, as shown in fig. 5-9.
Specifically, in this step, the piezoelectric thin film layer 14 is thinned to a desired thickness as shown in fig. 5, the piezoelectric thin film layer 14 and the dielectric layer between the piezoelectric thin film layer 14 and the substrate 11 are patterned as shown in fig. 6, and the interdigital electrode 15 is formed on the side of the piezoelectric thin film layer 14 facing away from the substrate 11 as shown in fig. 7.
For example, as shown in fig. 8, after forming the interdigital electrode 15, a passivation layer 22 may be further formed on a side of the interdigital electrode 15 facing away from the substrate 11, so as to implement passivation protection for the interdigital electrode 15.
Illustratively, as shown in fig. 9, after the passivation layer 22 is formed, the first bonding layer 18 is formed, and a material of the first bonding layer 18 is illustrated as a gold material, and the first bonding layer 18 is in contact with the interdigital electrode 15.
S103, as shown in FIG. 10, a package cover 12 is provided.
And S104, as shown in fig. 11-13, the packaging cover plate 12 is processed to form a plurality of protruding columns 13.
Specifically, in this step, the bonding portion is patterned by performing a patterning process on one side surface of the package cover 12 as shown in fig. 11, a second bonding layer 19 is formed on the side having the bonding portion patterned as shown in fig. 12, the material of the second bonding layer 19 is illustrated as a gold material, and a plurality of bump pillars 13 are simultaneously formed by performing a patterning process on the second bonding layer 19 as shown in fig. 13.
S105, as shown in fig. 14 and 1, the substrate 11 and the package cover 12 are connected through the plurality of protruding columns 13.
Specifically, in this embodiment, as shown in fig. 14, the bonding surface of each protruding pillar 13 further has a plurality of independent small protrusions, and after bonding, a similar snap-in manner can be formed to increase the contact surface between the first bonding layer 18 and the second bonding layer 19 as much as possible, thereby further improving the bonding effect.
For example, as shown in fig. 15, after bonding is completed, the substrate 11 may be further subjected to polishing treatment to reduce the thickness to a target thickness, which is not limited in the embodiment of the present invention and may be according to practical situations.
Illustratively, as shown in fig. 16, after the thinning process of the substrate 11, the substrate 11 may be further subjected to an etching process, that is, TSV (Through Silicon Via, deep silicon hole) etching, to form a through-hole 20 penetrating through the substrate 11.
Illustratively, as shown in fig. 1, an external lead structure 21 is formed, and the external lead structure 21 is connected to the first bonding layer 18 through the via hole 20.
In fig. 1,6, 7, 8, 9, 14, 15 and 16, the sidewalls of the piezoelectric thin film layer 14, the first dielectric layer 16 and the second dielectric layer 17 may be sloped sidewalls, for example, the dimensions of the piezoelectric thin film layer 14, the first dielectric layer 16 and the second dielectric layer 17 may gradually decrease in the direction in which the substrate 11 is directed toward the package cover 12.
Based on the above embodiment of the present invention, in another embodiment of the present invention, there is further provided an electronic device including the saw wafer level structure described in the above embodiment.
The foregoing describes the structure of a surface acoustic wave wafer and the method for manufacturing the same, and the electronic device, and the specific examples are provided herein to illustrate the principles and embodiments of the present invention, and the above examples are provided to assist in understanding the method and core ideas of the present invention, and meanwhile, the present invention should not be construed as being limited to the embodiments and application scope of the present invention, since the ideas of the present invention will be changed by those skilled in the art.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include, or is intended to include, elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A surface acoustic wave wafer level structure, the surface acoustic wave wafer level structure comprising:
The packaging cover plate is provided with a plurality of protruding columns, and the substrate and the packaging cover plate are connected in a packaging mode through the protruding columns;
the piezoelectric thin film layer is positioned between the substrate and the packaging cover plate and is positioned on the substrate, and the interdigital electrode is positioned on one side of the piezoelectric thin film layer away from the substrate;
the surface acoustic wave wafer level structure further comprises:
At least one dielectric layer between the piezoelectric thin film layer and the substrate;
the surface acoustic wave wafer level structure further comprises:
a bonding layer located at least between the raised pillars and the substrate;
The bonding layer comprises a first bonding layer arranged adjacent to the substrate and a second bonding layer arranged adjacent to the convex column;
the first bonding layer is in contact connection with the interdigital electrode.
2. The saw wafer level structure of claim 1, wherein said package cover is a Si cover.
3. The saw wafer level structure of claim 1, wherein a material of said first bonding layer and said second bonding layer is a metallic material.
4. The saw wafer level structure of claim 3, wherein a material of said first bonding layer and said second bonding layer is a gold material.
5. The saw wafer level structure of claim 3, wherein said substrate has a through hole therethrough;
the surface acoustic wave wafer level structure further comprises an external lead structure, wherein the external lead structure is connected with the first bonding layer through the through hole.
6. A method for manufacturing a surface acoustic wave wafer level structure, characterized in that the method for manufacturing a surface acoustic wave wafer level structure is used for manufacturing the surface acoustic wave wafer level structure according to any one of claims 1 to 5, and the method for manufacturing a surface acoustic wave wafer level structure comprises the steps of:
providing a substrate, wherein a piezoelectric film layer and at least one dielectric layer positioned between the piezoelectric film layer and the substrate are arranged on the substrate;
forming interdigital electrodes on one side of the piezoelectric film layer, which is away from the substrate;
providing a packaging cover plate;
processing the packaging cover plate to form a plurality of protruding columns;
and packaging and connecting the substrate and the packaging cover plate through the plurality of protruding columns.
7. An electronic device comprising the saw wafer level structure of any one of claims 1-5.
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| CN111121843A (en) * | 2019-12-18 | 2020-05-08 | 上海交通大学 | Integrated packaging structure and packaging method of a surface acoustic wave sensor |
| CN111510099A (en) * | 2020-04-24 | 2020-08-07 | 杭州见闻录科技有限公司 | Film bulk acoustic wave filter and wafer level packaging method thereof |
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| CN111654262B (en) * | 2020-06-19 | 2023-09-08 | 北京航天微电科技有限公司 | Wafer level packaging method and wafer level packaging structure of SAW filter chip |
| CN111786647B (en) * | 2020-08-07 | 2021-06-15 | 展讯通信（上海）有限公司 | Wafer-level surface acoustic wave filter and packaging method |
| KR20220092039A (en) * | 2020-12-24 | 2022-07-01 | 한양대학교 에리카산학협력단 | Surface Acoustic Devices For Front End Module And Its Manufacturing Method |
| CN113054942A (en) * | 2021-03-11 | 2021-06-29 | 展讯通信（上海）有限公司 | Surface acoustic wave filter and packaging method |
| WO2023208208A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensor based on wafer-level package, and manufacturing method therefor |
| CN118282345A (en) * | 2024-03-28 | 2024-07-02 | 浙江星曜半导体有限公司 | Packaging structure and packaging method of film surface acoustic wave resonator and radio frequency chip |
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| CN111121843A (en) * | 2019-12-18 | 2020-05-08 | 上海交通大学 | Integrated packaging structure and packaging method of a surface acoustic wave sensor |
| CN111510099A (en) * | 2020-04-24 | 2020-08-07 | 杭州见闻录科技有限公司 | Film bulk acoustic wave filter and wafer level packaging method thereof |
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