CN118738084A - A semiconductor component - Google Patents

Abstract

The present invention belongs to the field of semiconductor technology. The pn junction MOSFET based on the solution of the present invention improves the structure of the traditional pn junction MOSFET. In the field effect tube of the present invention, the electron conduction channel between the drain and the source only passes through the n-type conduction region of the semiconductor layer, and no longer passes through the p-type conduction region of the semiconductor layer. Through this change in detail, the bottleneck of the width of the electron conduction channel between the drain and the source is eliminated, the width of the electron conduction channel is widened, and thus the flow capacity of the electron conduction channel between the drain and the source is improved, which helps to further reduce the device loss and further miniaturize the device size.

Description

A semiconductor component

Technical Field

The present invention belongs to the field of semiconductor technology, and in particular, relates to a semiconductor element.

Background Art

In a traditional pn junction field effect transistor, taking an enhancement type pn junction MOSFET as an example, in order to realize a normally-off function, a portion of a p-type conductive region in a semiconductor layer of the traditional pn junction MOSFET is always in direct contact with a gate insulating film. When the gate-source voltage V _GS = 0 and the drain-source voltage V _DS = 0, the pn junction between the drain and the source itself will form a space charge region; when the gate-source voltage V _GS = 0 and the drain-source voltage V _DS > 0, the pn junction between the drain and the source is reverse biased, the formed space charge region widens, and a complete electron conduction channel is not formed between the drain and the source. At this time, no current flows between the drain and the source; when the gate-source voltage V _GS > 0, the electrons in the area adjacent to the gate insulating film in the semiconductor layer will be attracted and the holes will be repelled. An electron gathering area will be formed in an area of a certain thickness adjacent to the gate insulating film in the semiconductor layer. As the gate-source voltage V _GS continues to increase to V _GS(th) (the gate voltage when the electron conduction channel is just formed), a complete electron conduction channel is formed between the drain electrode and the source electrode. At this time, when the drain-source voltage V _DS applied between the drain and the source is > 0, a certain current will flow between the drain and the source.

However, in the on state of the conventional pn junction MOSFET, the electron conduction channel between the drain and the source must pass through both the n-type conduction region and the p-type conduction region of the semiconductor layer. Among them, the electron conduction channel in the region adjacent to the gate insulating film in the semiconductor layer can be divided into the following three parts (these three parts of the electron channel are as noted in Figure 2): the electron conduction channel of the first part is located in the n-type conduction region of the semiconductor layer. For the convenience of description, the electron conduction channel width of the first part is marked as _Wn ; the electron conduction channel of the second part is located in the p-type conduction region of the semiconductor layer. For the convenience of description, the electron conduction channel width of the second part is marked as _Wp ; the electron conduction channel of the third part is located in the pn junction space charge region of the semiconductor layer. For the convenience of description, the electron conduction channel width of the third part is marked as _Wpn ; I found through TCAD modeling and simulation that, under the condition of setting the corresponding electron concentration boundary, the electron conduction channel widths of these three parts have the following relationship: _Wp ＜ _Wpn ＜ _Wn , the width of _Wp is relatively narrow, and _Wp is less than Wp. 1/2 of the value of _n , according to conductivity σ=nqu (n is the electron carrier concentration, q is the electron charge, and u is the electron mobility), current density J=σE (E is the electric field strength), current I=JS (S is the flow area), since Wp width is the narrowest, the flow area of the electron conduction channel corresponding to this area is the smallest, making the flow capacity of the electron conduction channel in the p-type conductive region of the semiconductor layer relatively the smallest, which becomes the bottleneck of the flow capacity in the entire electron conduction channel. This bottleneck hinders the further improvement of the flow capacity of the traditional pn junction MOSFET.

Summary of the invention

In view of this, the present invention aims at the problems existing in the traditional pn junction field effect tube, improves and optimizes its structure, and proposes a pn junction field effect tube with greater current flow capacity than the traditional pn junction field effect tube.

In order to achieve the above object, the present invention provides a pn junction field effect transistor having:

A semiconductor layer comprising at least an n-type conductive region and a p-type conductive region;

Electrodes, including a drain electrode, a source electrode, and a gate electrode, wherein the source electrode is connected to the p-type conductive region;

a gate insulating film, which is interposed between the gate electrode and the semiconductor layer;

The p-type conductive region is not in contact with the gate insulating film, and a conductive region is provided between the p-type conductive region and the gate insulating film. The conductive region is composed of a semiconductor whose conductivity type is different from the p-type conductivity or is composed of a conductor. Under the action of the gate electrode bias, the conductive region increases the electron concentration in the conductive channel formed between the drain electrode and the source electrode.

Preferably, the semiconductor having a conductivity type different from the p-type conductivity is an n-type doped conductivity semiconductor, an unintentionally doped intrinsic state semiconductor, or an intentionally doped high resistance state semiconductor.

Preferably, the width of the conductive region is in the range of 3 nm to 300 nm.

Preferably, the width of the conductive region is in the range of 3 nm to 100 nm.

Preferably, the pn junction field effect transistor is a horizontal MOSFET or a vertical MOSFET.

Preferably, the vertical MOSFET is a vertical planar gate MOSFET, a vertical trench gate MOSFET, a vertical shielded gate MOSFET or a vertical super junction MOSFET.

Preferably, the semiconductor layer is composed of a simple semiconductor, a compound semiconductor or an oxide semiconductor.

The present invention further provides a semiconductor element, wherein the semiconductor element is an insulated gate bipolar transistor, and the insulated gate bipolar transistor comprises:

A semiconductor layer comprising at least an n-type conductive region and a p-type conductive region;

Electrodes, including an emitter, a collector, and a gate electrode;

a gate insulating film, which is interposed between the gate electrode and the semiconductor layer;

A p-type conductive region of the semiconductor layer connected to the emitter is not in contact with the gate insulating film, and a conductive region is provided between the p-type conductive region of the semiconductor layer connected to the emitter and the gate insulating film. The conductive region is composed of a semiconductor whose conductivity type is different from the p-type conductivity or is composed of a conductor. Under the action of the gate electrode bias, the electron concentration of the conductive channel formed between the emitter and the collector is increased in the conductive region.

Preferably, the semiconductor having a conductivity type different from the p-type conductivity is an n-type doped conductivity semiconductor, an unintentionally doped intrinsic state semiconductor, or an intentionally doped high resistance state semiconductor.

Preferably, the width of the conductive region is in the range of 3 nm to 300 nm.

Preferably, the insulated gate bipolar transistor is a planar gate IGBT, a trench gate IGBT, a shielded gate IGBT or a super junction IGBT.

When the semiconductor is a single-element semiconductor, for example, it can be germanium, silicon, diamond, etc.; when the semiconductor is a compound semiconductor, for example, it can be gallium arsenide, indium phosphide, silicon carbide, gallium nitride, etc.; when the semiconductor is an oxide semiconductor, for example, it can be zinc oxide, tin oxide, gallium oxide, etc.

The present invention has the following beneficial effects:

1) In the on state of the conventional pn junction MOSFET, the electron conduction channel between the drain and the source must pass through both the n-type conduction region of the semiconductor layer and the p-type conduction region of the semiconductor layer. Among them, the electron conduction channel passing through the p-type conduction region is the narrowest and is the bottleneck affecting the flow capacity. The present invention improves the structure of the conventional pn junction MOSFET. The field effect transistor of the present invention is provided with a conductive region between the p-type conduction region connected to the source electrode and the gate insulating film. The conductive region is composed of a semiconductor with a conductivity type different from the p-type conduction (such as an n-type doped conductive semiconductor, an unintentionally doped intrinsic state semiconductor, or an intentionally doped high-resistance state semiconductor), so that the electron conduction channel between the drain and the source only passes through the n-type conduction region of the semiconductor layer, and no longer passes through the p-type conduction region of the semiconductor layer. Through this change in detail, the bottleneck of the electron conduction channel between the drain and the source is eliminated, the width of the electron conduction channel is widened, and the flow capacity of the electron conduction channel between the drain and the source is improved, which is helpful to further reduce the device loss and further miniaturize the device size.

2) The field effect tube of the present invention is also applicable to an insulated gate bipolar transistor (IGBT). When the field effect tube of the present invention is an insulated gate bipolar transistor (IGBT), the electron conductive channel located in the semiconductor layer adjacent to the gate insulating film no longer passes through the p-type conductive region connected to the emitter. Through this change in detail, the width of the electron conductive channel can be widened, thereby improving the flow capacity of the electron conductive channel, which helps to further reduce the loss of the IGBT device and further miniaturize the device size.

3) The pn junction field effect transistor of the present invention is a normally-off device while improving the current carrying capacity. The pn junction field effect transistor of the present invention realizes the normally-off function through the depletion of carriers by the MIS junction formed between the gate electrode-gate insulating film-n-type conductive region of the semiconductor layer and the pn junction formed between the p-type conductive region and the n-type conductive region of the semiconductor layer.

The present invention further provides a semiconductor element, which is a trench MOS type pin junction diode, and the trench MOS type pin junction diode comprises:

a first n-type semiconductor layer;

a second n-type semiconductor layer stacked on the first n-type semiconductor layer, wherein the donor concentration of the second n-type semiconductor layer is lower than the donor concentration of the first n-type semiconductor layer;

A p-type semiconductor region, the p-type semiconductor region being stacked on the second n-type semiconductor layer;

Trench MOS gate;

an anode electrode formed on the upper surface of the p-type semiconductor region and the trench MOS gate;

a cathode electrode formed on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer;

The conductive region is stacked on the second n-type semiconductor layer and is located between the trench MOS gate and the p-type semiconductor region. The conductive region is composed of a semiconductor whose conductivity type is different from the p-type conductivity or a conductor.

Preferably, the semiconductor other than the p-type semiconductor is an n-type doped conductive semiconductor.

Preferably, the width of the conductive region is in the range of 3 nm to 200 nm.

The present invention has the following beneficial effects:

The trench MOS type pn junction diode of the present invention, when forward conducting, the current will preferentially flow through the region without the pn junction barrier, that is, the current will preferentially flow through the region with a conductivity type different from the p-type conductivity provided between the p-type semiconductor layer and the trench MOS gate. Therefore, the trench MOS type pn junction diode of the present invention has a lower turn-on voltage compared to the traditional pn junction diode, so that a pn junction diode device with lower loss can be manufactured; when a reverse voltage is applied to the diode, through the reverse bias of the pn junction and the depletion effect of the electron carriers in the region of the trench MOS gate, only a very small leakage current flows between the anode and the cathode, and the diode is reversely cut off.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the drawings required for use in the embodiments or prior art descriptions. Obviously, some of the drawings in the following description are only illustrations of some embodiments of the present invention, and the protection scope required by the present invention is not limited to the embodiments. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work.

FIG. 1 is a vertical cross-sectional view of an embodiment of a conventional pn junction trench gate MOSFET.

FIG2 is a partial structural diagram extracted from the trench gate MOSFET structure shown in FIG1 .

FIG3 is a schematic diagram of structural modeling of a part of an existing pn junction MOSFET structure and a part of a pn junction MOSFET structure based on the present invention.

FIG. 4 is a vertical cross-sectional view of an embodiment of a conventional pn junction type vertical planar gate MOSFET.

FIG. 5 a is a vertical cross-sectional view of a first example of a vertical planar gate MOSFET according to an embodiment of the present invention.

FIG. 5 b is a vertical cross-sectional view of a second example of a vertical planar gate MOSFET according to an embodiment of the present invention.

FIG. 6 a is a vertical cross-sectional view of a first example of a vertical trench gate MOSFET according to an embodiment of the present invention.

FIG. 6 b is a vertical cross-sectional view of a second example of a vertical trench gate MOSFET according to an embodiment of the present invention.

FIG. 6 c is a vertical cross-sectional view of a third example of a vertical trench gate MOSFET according to an embodiment of the present invention.

FIG. 6 d is a vertical cross-sectional view of a fourth example of a vertical trench gate MOSFET according to an embodiment of the present invention.

FIG. 6 e is a vertical cross-sectional view of a fifth example of a vertical trench gate MOSFET according to an embodiment of the present invention.

FIG. 7 a is a vertical cross-sectional view of a first example of a vertical shielded gate MOSFET according to an embodiment of the present invention.

FIG. 7 b is a vertical cross-sectional view of a second example of a vertical shielded gate MOSFET according to an embodiment of the present invention.

FIG. 7 c is a vertical cross-sectional view of a third example of a vertical shielded gate MOSFET according to an embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view of an example of a vertical super junction MOSFET according to an embodiment of the present invention.

FIG. 9 is a vertical cross-sectional view of an embodiment of a conventional planar gate IGBT.

FIG. 10 is a vertical cross-sectional view of a first example of a planar gate IGBT according to an embodiment of the present invention.

11 is a vertical cross-sectional view of a first example of a trench MOS type pin junction diode according to an embodiment of the present invention.

The technical features corresponding to the marks in the accompanying drawings are:

11 Drain electrode

12 Source electrode

13. Gate electrode

14 Collector

15 Emitter

21a n+ type semiconductor region

21b n-type semiconductor region

21c Intrinsic semiconductor region

31a p+ type semiconductor region

31b p-type semiconductor region

41 High resistance semiconductor region

51. Gate insulating film (insulating film)

52 Insulation film layer

W _n n-type region electronic conduction channel width

W _p Width of the electron conduction channel in the p-type region

W _pn The width of the electron conduction channel in the depletion region of the pn junction

61 cathode

62 Anode

63 Trench MOS Gate

DETAILED DESCRIPTION

In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

FIG1 is a vertical cross-sectional view of an embodiment of an existing pn junction type vertical trench gate MOSFET. The pn junction type vertical trench gate MOSFET (hereinafter referred to as pn junction type MOSFET) has from bottom to top: a drain electrode 11, an n+ type semiconductor region 21a, an n- type semiconductor region 21b, a p- type semiconductor region 31b, an n+ type semiconductor region 21a, and a trench embedded from the upper surface of the n+ type semiconductor region 21a in the n+ type semiconductor region 21a, the p- type semiconductor region 31b, and the n- type semiconductor region 21b, a gate electrode 13 located in the trench and wrapped by a gate insulating film 51, and a source electrode 12.

The pn junction MOSFET shown in FIG1 has a pn junction in the body. When only a forward voltage is applied between the drain electrode 11 and the source electrode 12, the pn junction in the pn junction MOSFET body is reverse biased to widen the depletion region, so that a complete electron conduction channel is not formed between the drain electrode 11 and the source electrode 12, and no current flows between the drain and the source. Based on this principle, the pn junction MOSFET shown in FIG1 is a normally-off device. When the voltage V _GS applied to the gate electrode 13 is greater than V _GS(th) (the gate-source voltage when the channel is just formed), an n-type thin layer (inversion layer) containing only electron carriers will be formed in the region near the gate insulating film 51 of the p-type semiconductor region 31b. This n-type thin layer connects the electron conduction channel between the drain electrode 11 and the source electrode 12. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, a current flows between the drain and the source, and the pn junction MOSFET is turned on.

FIG2 is a partial structural diagram of the pn junction MOSFET structure shown in FIG1. When the voltage _VGS applied between the gate electrode 13 and the source electrode 12 is greater than _VGS(th) , an electron conductive channel is formed between the drain electrode 11 and the source electrode 12, and a portion of the electron conductive channel adjacent to the gate insulating film 51 is shown in FIG2. The width of the electron channel in the n-type conductive region of the semiconductor layer is recorded as _Wn , the width of the electron channel in the p-type conductive region of the semiconductor layer is recorded as _Wp , and the width of the electron channel in the pn junction depletion region of the semiconductor layer is recorded as _Wpn .

In the background technology introduction, the inventor has explained that in the on state of the existing pn junction MOSFET, the electron conduction channel between the drain and the source must pass through both the n-type conduction region of the semiconductor layer and the p-type conduction region of the semiconductor layer, among which the electron conduction channel passing through the p-type conduction region is the narrowest and is the bottleneck affecting the current carrying capacity. The concept of the present invention is to improve the structure of the conventional pn junction MOSFET. After the improvement, in the on state of the pn junction MOSFET under the new structure, the electron conduction channel between the drain and the source only passes through the n-type conduction region of the semiconductor layer, and no longer passes through the p-type conduction region of the semiconductor layer.

Based on the above-mentioned inventive concept, the present invention is modeled and simulated through semiconductor process and device simulation software (TCAD), which is specifically described below in conjunction with the modeling schematic diagram shown in Figure 3. Figure 3 is a modeling schematic diagram for a part of the existing pn junction MOSFET structure and a part of the pn junction MOSFET structure based on the present invention.

In the modeling schematic diagram shown in FIG. 3 , the area in the middle of the figure is the gate electrode 13, and the gate insulating film 51 is located on both sides of the gate electrode 13. The stacked structure in the left half is equivalent to a part of the conventional pn junction MOSFET structure, which is, from bottom to top, the following: the drain electrode 11, the n+ type semiconductor region 21a, the n- type semiconductor region 21b stacked thereon, the p- type semiconductor region 31b stacked on the n- type semiconductor region 21b, and the p+ type semiconductor region 31 stacked on the p- type semiconductor region 31b and away from the gate insulating film 51. a, an n+ type semiconductor region 21a stacked on the p-type semiconductor region 31b and in contact with the gate insulating film 51, and a source electrode 12; the stacked structure in the right half is a part of the pn junction MOSFET structure based on the scheme of the present invention, and the difference between it and the left half structure is that, in the pn junction MOSFET in the right half, the p-type semiconductor region 31b is no longer in contact with the gate insulating film 51, but an n-type semiconductor region 21b (conductive region) is introduced between the p-type semiconductor region 31b (p-type conductive region) and the gate insulating film 51. In the actual simulation, the materials of the n+ type semiconductor region 21a, the n- type semiconductor region 21b, the p+ type semiconductor region 31a and the p- type semiconductor region 31b are all set to SiC, the electron concentration of the n+ type semiconductor region 21a is set to 5x10 ¹⁸ cm ^-3 , the electron concentration of the n- type semiconductor region 21b is set to 1x10 ¹⁷ cm ^-3 , the electron concentration of the p- type semiconductor region 31b is set to 1x10 ¹⁷ cm ^-3 , the electron concentration of the p+ type semiconductor region 31a is set to 5x10 ¹⁸ cm ^-3 , the material of the gate insulating film is set to HfO ₂ , the thickness of the gate insulating film is set to 50 nm, and the drain electrode 11 and the source electrode 12 both form ohmic contact with the semiconductor layer.

In the modeling schematic diagram shown in FIG. 3 , when the voltage V _GS between the gate electrode 13 and the source electrode 12 is set to 0, for a portion of the existing pn junction MOSFET structure located in the left half, in the vertical direction, a space charge region is formed in the pn junction region formed by the p-type semiconductor region 31b and the n-type semiconductor region 21b, and a space charge region is formed in the pn junction region formed by the p-type semiconductor region 31b and the n+ type semiconductor region 21a. The influence range of each space charge region is about 250nm. In addition, a space charge region is formed at the MIS (metal-insulator-semiconductor) junction composed of the gate electrode 13, the gate insulating film 51 and the semiconductor layer located on the left side. The influence range of each space charge region is about 100nm; for a part of the pn junction MOSFET structure based on the solution of the present invention located in the right half, a space charge region will be formed in the pn junction region formed by the n-type semiconductor region 21b and the p-type semiconductor region 31b in the horizontal direction, and the influence range of this space charge region is about 250nm; in addition, a space charge region will be formed at the MIS (metal-insulator-semiconductor) junction composed of the gate electrode 13, the gate insulating film 51 and the semiconductor layer located on the right side, and the influence range of this space charge region is about 100nm.

In the modeling schematic diagram shown in FIG3 , when the voltage V _GS between the gate electrode 13 and the source electrode 12 is set to 10V, for a portion of the structure of the pn junction MOSFET located in the left half, a complete electron conduction channel is formed in the region of the semiconductor layer located between the drain electrode 11 and the source electrode 12 and adjacent to the gate insulating film 51. In the entire conduction channel, the widths of the region with an electron concentration of ≥1.5×10 ¹⁸ cm ^-3 are as follows: the width of the electron conduction channel in the p-type semiconductor region 31b (corresponding to W _p in FIG2 ) is about 3nm, the width of the electron conduction channel in the n-type semiconductor region 21b (corresponding to W _n in FIG2 ) is about 6.25nm, and the width of the electron conduction channel in the pn junction depletion region formed between the p-type semiconductor region 31b and the n-type semiconductor region 21b and the pn junction depletion region formed between the p+ type semiconductor region 31a and the n-type semiconductor region 21b (corresponding to W _pn in FIG2 ) is about 3nm to 6.25nm. Therefore, there is a complete and high-concentration electron conduction channel between the drain and source of the pn junction MOSFET. At this time, when a positive voltage is applied between the drain and source, the pn junction MOSFET can be turned on.

In the modeling schematic diagram shown in FIG. 3 , when the voltage V _GS between the gate electrode 13 and the source electrode 12 is set to 10V, for a portion of the pn junction MOSFET structure based on the present invention located in the right half, a complete electron conduction channel is formed in the region of the semiconductor layer located between the drain electrode 11 and the source electrode 12 and adjacent to the gate insulating film 51. The entire electron conduction channel no longer passes through the p-type semiconductor region 31b, but only passes through the n+ type semiconductor region 21a and the n-type semiconductor region 21b. At this time, the width of the region with an electron concentration ≥1.5x10 ¹⁸ cm ^-3 in the electron conduction channel in the n-type semiconductor region 21b is about 6.25nm (i.e., Wp, _Wn , and Wpn in FIG. 2 all become about 6.25nm). According to the conductivity σ=nqu (where n is the concentration of electron carriers involved in conduction, q is the amount of electron charge, and u is the mobility under a certain carrier concentration condition), and according to the current density J=σE (where E represents the electric field strength), combined with the current I=JS (where S represents the flow area), it can be known that the wider the electron conduction channel, the larger the flow area, and the stronger the flow capacity. Therefore, the pn junction MOSFET based on the present invention has a stronger flow capacity than the conventional pn junction MOSFET.

FIG4 is a vertical cross-sectional view of an embodiment of a conventional pn junction type vertical planar gate MOSFET. The pn junction type vertical planar gate MOSFET has, from bottom to top: a drain electrode 11, an n+ type semiconductor region 21a, an n- type semiconductor region 21b, and a p- type semiconductor region 31b located in the n- type semiconductor region 21b, which is in contact with both the source electrode 12 and the gate insulating film 51, and an n+ type semiconductor region 21a located in the p- type semiconductor region 31b, which is in contact with the source electrode 12, and a gate electrode 13 located on the gate insulating film 51.

In the existing pn junction type vertical planar gate MOSFET shown in FIG4, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, the pn junction formed by the p-type semiconductor region 31b and the n-type semiconductor region 21b is reverse biased, and the depletion layer widens. In this way, there is no conductive channel between the drain electrode 11 and the source electrode 12, that is, no current flows, and the device is normally off; when a positive bias voltage is applied between the gate electrode 13 and the source electrode 12, an inversion layer is formed in the area of the p-type semiconductor region 31b adjacent to the gate insulating film 51, forming a high-concentration electron gathering area. This inversion layer connects the electron conductive channel between the drain and the source. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, an electron current will flow between the drain and the source, and the device is turned on.

In the existing pn junction type vertical planar gate MOSFET shown in Figure 4, when it is in the on state, the electron conduction channel between the drain and the source must pass through the p-type semiconductor region 31b, and the width of the electron conduction channel in the p-type semiconductor region 31b is relatively narrowest in the entire electron conduction channel between the drain and the source, which is the bottleneck of the width of the entire electron conduction channel between the drain and the source. This has hindered the further improvement of the current conduction capacity of the existing pn junction MOSFET to a certain extent.

FIG5a is a vertical cross-sectional view of the first embodiment of the pn junction type vertical planar gate MOSFET involved in the embodiment of the present invention. The difference between the conventional pn junction type vertical planar gate MOSFET shown in FIG4 is that: in the structure of the conventional pn junction type vertical planar gate MOSFET shown in FIG4, the p-type semiconductor region 31b is in contact with both the source electrode 12 and the gate insulating film 51; the pn junction type vertical planar gate MOSFET of the present invention includes a semiconductor layer, a drain electrode 11, a source electrode 12, a gate electrode 13 and a gate insulating film 51, wherein the semiconductor layer includes an n+ type semiconductor region 21a stacked on the drain electrode 11, an n-type semiconductor region 21b stacked on the n+ type semiconductor region 21a, and a p-type semiconductor region 31b (p-type conductive region) disposed in the n-type semiconductor region 21b, which is connected to the source electrode 12, and the n+ type semiconductor region 21a connected to the source electrode 12; the gate insulating film 51 is between the gate electrode 13 and the semiconductor layer. In the pn junction type vertical planar gate MOSFET structure of the present invention, the p-type semiconductor region 31b is only in contact with the source electrode 12, and no longer in contact with the gate insulating film 51. A conductive region 21c (the region marked by the dotted box in FIG. 5a ) is provided between the p-type semiconductor region 31b and the gate insulating film 51. The conductive region 21c is composed of an n-type semiconductor (i.e., an n-type doped conductive semiconductor) having a conductivity type different from that of the p-type conductivity. In this embodiment, the conductive region 21c and the n-type semiconductor region 21b are also composed of an n-type semiconductor, and the conductive region 21c is integrated with the n-type semiconductor region 21b. The width of the conductive region 21c is in the range of 3nm to 300nm, preferably in the range of 3nm to 100nm.

For the MOSFET shown in FIG. 5a: in a balanced state, the MIS junction composed of the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21c will deplete the electron carriers in the n-type semiconductor region 21c adjacent to the gate insulating film 51, and the pn junction composed of the p-type semiconductor region 31b and the n-type semiconductor region 21c will also deplete the electron carriers in the conductive region 21c. Under the combined effect of these two depletion effects, the electron carriers in the conductive region 21c between the gate insulating film 51 and the p-type semiconductor region 31b are depleted; when a positive voltage is applied between the drain electrode 11 and the source electrode 12, the p-type semiconductor region 21c is depleted. The pn junction formed by 31b and the n-type semiconductor region 21c is reverse biased, and the depletion layer widens. In this way, the depletion effect on the electron carriers in the conductive region 21c located between the gate insulating film 51 and the p-type semiconductor region 31b is further strengthened. In this way, there is no conductive channel between the drain electrode 11 and the source electrode 12, that is, no current flows, and the device is normally off; when a positive bias voltage is applied between the gate electrode 13 and the source electrode 12, a high-concentration electron gathering area will be formed in the area of the n-type semiconductor region adjacent to the gate insulating film 51, which connects the electron conductive channel between the drain and the source. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, an electron current will flow between the drain and the source, and the device will be turned on.

In the MOSFET shown in FIG. 5a, in the on state, the electron conduction channel between the drain and the source no longer passes through the p-type conduction region of the semiconductor layer, and the entire electron conduction channel passes through the n-type conduction region of the semiconductor layer. Compared with the conventional pn junction type vertical planar gate MOSFET shown in FIG. 4, this change in detail eliminates the bottleneck of the width of the electron conduction channel between the drain and the source, widens the width of the electron conduction channel, and thus improves the flow capacity of the electron conduction channel between the drain and the source, which helps to further reduce device losses and further miniaturize device size.

In this embodiment, the conductive region 21 c is composed of an n-type semiconductor whose conductivity type is different from the p-type conductivity. In other embodiments, the conductive region 21 c may be composed of a conductor, such as a metal or an alloy.

FIG5b is a vertical cross-sectional view of the second embodiment of the vertical planar gate MOSFET of the present invention. The difference between this embodiment and the first embodiment of the vertical planar gate MOSFET (corresponding to FIG5a) is that in the vertical planar gate MOSFET of this embodiment, the conductive region between the gate insulating film 51 and the p-type semiconductor region 31b is no longer composed of n-type semiconductor, but is replaced by intentionally doped high-resistance semiconductor, the high-resistance semiconductor forms a high-resistance semiconductor region 41, and the semiconductor material is gallium oxide material as an example, which can achieve high resistance through intentional doping. When a positive bias is applied between the gate electrode 13 and the source electrode 12, a high-concentration electron gathering region will be formed in the region adjacent to the gate insulating film 51 in the high-resistance semiconductor region 41, which connects the electron conductive channel between the drain and the source. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, an electron current will flow between the drain and the source, and the MOSFET will be turned on. In other implementations, the material composition of the conductive region between the gate insulating film 51 and the p-type semiconductor region 31b can be replaced by a non-intentionally doped intrinsic semiconductor.

FIG6a is a vertical cross-sectional view of the first embodiment of the vertical trench gate MOSFET of the present invention. The difference between the MOSFET shown in FIG6a and the existing MOSFET shown in FIG1 is that: in the structure of the existing MOSFET shown in FIG1, the p-type semiconductor region 31b is in contact with both the source electrode 12 and the gate insulating film 51; while in the structure of the vertical trench gate MOSFET based on the present invention shown in FIG6a, the p-type semiconductor region 31b is only in contact with the source electrode 12, and no longer in contact with the gate insulating film 51, and between the gate insulating film 51 and the p-type semiconductor region 31b is an n-type semiconductor region 21b composed of an n-type semiconductor. For the MOSFET shown in FIG. 6a: in a balanced state, the MIS junction composed of the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21b will deplete the electron carriers in the n-type semiconductor region 21b adjacent to the gate insulating film 51, and the pn junction composed of the p-type semiconductor region 31b and the n-type semiconductor region 21b will also deplete the electron carriers in the n-type semiconductor region 21b. Under the combined effect of these two depletion effects, the electron carriers in the n-type semiconductor region 21b between the gate insulating film 51 and the p-type semiconductor region 31b are depleted; when a positive voltage is applied between the drain electrode 11 and the source electrode 12, the p-type semiconductor region 31b The pn junction formed with the n-type semiconductor region 21b is reverse biased, and the depletion layer widens. In this way, the depletion effect on the electron carriers in the n-type semiconductor region 21b located between the gate insulating film 51 and the p-type semiconductor region 31b is further strengthened. In this way, there is no conductive channel between the drain electrode 11 and the source electrode 12, that is, no current flows, and the device is normally off; when a positive bias voltage is applied between the gate electrode 13 and the source electrode 12, a high-concentration electron accumulation area will be formed in the area of the n-type semiconductor region adjacent to the gate insulating film 51, which connects the electron conductive channel between the drain and the source. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, an electron current will flow between the drain and the source, and the vertical trench gate MOSFET will be turned on.

Similarly, in the vertical trench gate MOSFET shown in FIG6a, the electron conduction channel between the drain and the source does not pass through the p-type conduction region of the semiconductor layer, but only passes through the n-type conduction region of the semiconductor layer. Compared with the conventional MOSFET shown in FIG1, this change in detail eliminates the bottleneck of the width of the electron conduction channel between the drain and the source, widens the width of the electron conduction channel, and thus improves the flow capacity of the electron conduction channel between the drain and the source, which helps to further reduce device losses and further miniaturize the device size.

In other embodiments, the vertical trench gate MOSFET shown in FIG. 6a can also be used as a diode. When it is used as a diode, the source electrode 12 serves as an anode, the drain electrode 11 serves as a cathode, and the gate electrode 13 is short-circuited with the source electrode 12 and also serves as an anode. At this time, when a positive voltage is applied between the anode (i.e., the source electrode 12 and the gate electrode 13) and the cathode (i.e., the drain electrode 11), a current will flow between the anode and the cathode, and the diode will be forward-conducted. There are two current paths: the first current path is along the source electrode 12—n+ type semiconductor region 21a—n- type semiconductor region 21b—n+ type semiconductor region 21a—drain electrode 11; the second current path is along the source electrode 12—p- type semiconductor region 31b—n- type semiconductor region 21b—n+ type semiconductor region 21a—drain electrode 11. When a negative voltage is applied between the anode (i.e., the source electrode 12 and the gate electrode 13) and the cathode (i.e., the drain electrode 11), the pn junction formed by the p-type semiconductor region 31b and the n-type semiconductor region 21b is reverse biased, and the depletion layer widens, which will produce longitudinal depletion and lateral depletion effects on the electron carriers in the n-type semiconductor region 21b respectively; the MIS junction formed by the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21b will also produce a lateral repulsive depletion effect on the electron carriers in the n-type semiconductor region 21b. Under the combined effect of the lateral depletion of the pn junction and the lateral depletion of the MIS junction, the electron carriers in the n-type semiconductor region 21b located between the gate insulating film 51 and the p-type semiconductor region 31b will gradually be depleted. At this time, only a small leakage current flows between the anode and the cathode, and the diode is reversely cut off.

FIG6b is a vertical cross-sectional view of the second embodiment of the vertical trench gate MOSFET of the present invention. The vertical trench gate MOSFET in this embodiment differs from the conventional MOSFET shown in FIG1 in that: in the structure of the conventional MOSFET, the p-type semiconductor region 31b is in contact with both the source electrode 12 and the gate insulating film 51; while in the structure of the vertical trench gate MOSFET in this embodiment, the p-type semiconductor region 31b is only in contact with the source electrode 12 and no longer in contact with the gate insulating film 51, and between the gate insulating film 51 and the p-type semiconductor region 31b is a high-resistance semiconductor region 41. Compared with the conventional MOSFET shown in FIG1, the vertical trench gate MOSFET in this embodiment also has an electronic conductive channel that no longer passes through the p-type conductive region of the semiconductor layer, which also helps to improve the flow capacity of the electronic conductive channel between the drain and the source.

FIG6c is a vertical cross-sectional view of the third embodiment of the vertical trench gate MOSFET of the present invention. The vertical trench gate MOSFET comprises from bottom to top: a drain electrode 11, an n+ type semiconductor region 21a, an n- type semiconductor region 21b, a p- type semiconductor region 31b, and a trench opening from the upper surface of the n- type semiconductor region 21b, a gate insulating film 51 covering the inner wall of the trench, and a gate electrode 13 surrounded by the gate insulating film 51, and a source electrode 12 in contact with the upper surface of the n- type semiconductor region 21b, wherein the n- type semiconductor region 21b is located between the p- type semiconductor region 31b and the gate insulating film 51. For the vertical trench gate MOSFET shown in FIG. 6c: in the equilibrium state, the pn junction formed by the p-type semiconductor region 31b and the n-type semiconductor region 21b will form a carrier depletion region, and the MIS junction formed by the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21b will repel the carriers in the n-type semiconductor layer to form a carrier depletion region. Under the combined effect of the pn junction depletion and the MIS junction depletion, the electron carriers in the n-type semiconductor region 21b located between the p-type semiconductor region 31b and the gate insulating film 51 will be depleted, thereby blocking the electronic conduction channel between the drain electrode 11 and the source electrode 12; when only a positive voltage is applied between the drain electrode 11 and the source electrode 12, the pn junction formed by the p-type semiconductor region 31b and the n-type semiconductor region 21b is reverse biased to further widen the depletion layer, and the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21b will form a carrier depletion region. The MIS junction formed by the p-type semiconductor region 21b has a stronger repulsive force on the carriers in the n-type semiconductor layer. The combined effect of the two strengthens the electron carrier depletion effect in the n-type semiconductor region 21b located between the p-type semiconductor region 31b and the gate insulating film 51. At this time, no current flows between the drain and the source, and the vertical trench gate MOSFET is in the off state; when a positive bias voltage is applied between the gate electrode 13 and the source electrode 12, it will have an attractive effect on the electron carriers. Therefore, a high-concentration electron accumulation area will be formed in the n-type semiconductor region 21b adjacent to the gate insulating film 51. This electron accumulation area constitutes a part of the electron conduction channel between the drain and the source. This part of the electron conduction channel does not pass through the p-type conductive region of the semiconductor layer. At this time, when a positive voltage is applied between the drain electrode 11 and the source electrode 12, current will flow between the drain and the source, and the vertical trench gate MOSFET will be turned on.

FIG6d is a vertical cross-sectional view of the fourth embodiment of the vertical trench gate MOSFET of the present invention. The vertical trench gate MOSFET in this embodiment is based on the vertical trench gate MOSFET structure in the third embodiment of the vertical trench gate MOSFET (corresponding to FIG6c), and a part of the source electrode 12 is embedded in the semiconductor layer, which is presented as another embodiment and will not be described in detail here.

FIG6e is a vertical cross-sectional view of the fifth embodiment of the vertical trench gate MOSFET of the present invention. The vertical trench gate MOSFET in this embodiment is based on the structure of the vertical trench gate MOSFET in FIG6d, and the depth of the p-type semiconductor region 31b is deeper than the depth of the source electrode 12 adjacent thereto. Such a design can further enhance the turn-off effect of the MOSFET and reduce the leakage current.

FIG7a is a vertical cross-sectional view of the first embodiment of the vertical shielded gate MOSFET of the present invention. Remarks on the structure of the vertical shielded gate MOSFET As shown in FIG7a, the vertical shielded gate MOSFET shown in FIG7a is still a normally-off device. In the vertical shielded gate MOSFET shown in FIG7a, in the on state, the electron conductive channel between the drain and the source does not pass through the p-type conductive region of the semiconductor layer, but only passes through the n-type conductive region of the semiconductor layer. Through this change in detail, the width of the electron conductive channel is widened, thereby improving the flow capacity of the electron conductive channel between the drain and the source, which helps to further reduce the device loss and further miniaturize the device size.

FIG7b is a vertical cross-sectional view of the second embodiment of the vertical shielded gate MOSFET of the present invention. The vertical shielded gate MOSFET in this embodiment is based on the vertical shielded gate MOSFET in the first embodiment of the vertical shielded gate MOSFET (refer to FIG7a), and the structure of the shielded gate region is locally optimized, and the gate electrode 13 located in the groove is arranged on both sides of the source electrode 12 in the groove, and the gate electrode 13 and the source electrode 12 are separated by a gate insulating film 51. Compared with the vertical shielded gate MOSFET shown in FIG7a, the vertical shielded gate MOSFET in FIG7b can improve the voltage resistance performance of the MOSFET and reduce the off-state leakage current through the optimization of the structural design of this region.

FIG7c is a vertical cross-sectional view of the third embodiment of the vertical shielded gate MOSFET of the present invention. The vertical shielded gate MOSFET in this embodiment is based on the vertical shielded gate MOSFET in the first embodiment of the vertical shielded gate MOSFET (refer to FIG7a), and the structure of the shielded gate region is locally optimized, and the gate electrode 13 located in the groove is arranged on both sides of the source electrode 12 in the groove, and the gate electrode 13 and the source electrode 12 are separated by a gate insulating film 51. Compared with the vertical shielded gate MOSFET shown in FIG7a, the vertical shielded gate MOSFET in FIG7c can improve the voltage resistance performance of the MOSFET and reduce the off-state leakage current through the optimization of the structural design of this region.

FIG8 is a vertical cross-sectional view of an embodiment of a vertical super junction MOSFET of the present invention. Based on the vertical planar gate MOSFET shown in FIG5a, a p-type conductive column region 31b is added to form a super junction MOSFET, which can further improve the voltage resistance of the MOSFET.

FIG9 is a vertical cross-sectional view of an embodiment of a conventional planar gate IGBT. The planar gate IGBT comprises, from bottom to top, a collector 14, a p+ type semiconductor region 31a, an n-type semiconductor region 21b, and a p-type semiconductor region 31b located in the n-type semiconductor region 21b, which is in contact with both the emitter 15 and the gate insulating film 51, and an n+ type semiconductor region 21a located in the p-type semiconductor region 31b, which is in contact with the emitter 15, and a gate electrode 13 located on the gate insulating film 51.

IGBT is a bipolar device. When the IGBT is in the on state, there are both electron current and hole current, as shown in FIG9 , where the dotted line represents the electron current and the long dashed line represents the hole current. In the IGBT shown in FIG9 , for ease of description, we mark the pn junction composed of the p+ type semiconductor region 31a and the n- type semiconductor region 21b as J1, and the pn junction composed of the p- type semiconductor region 31a and the n- type semiconductor region 21b as J2. When a positive voltage is applied between the collector 14 and the emitter 15, J2 is reverse biased to widen its depletion layer, thereby blocking the carrier conduction channel between the collector 14 and the emitter 15. At this time, no current flows between the collector 14 and the emitter 15. When a positive bias voltage is applied between the gate electrode 13 and the emitter 15, it attracts electrons, so a high-concentration electron accumulation region is formed in the p- type semiconductor region 31b below the gate insulating film 51. It repels holes, so a high-concentration hole accumulation region is formed in the area below the electron accumulation layer. When a positive voltage is applied between the collector 14 and the emitter 15, the electron accumulation region connects the electron conduction channel between the collector 14 and the emitter 15, and the hole accumulation region connects the hole conduction channel between the collector 14 and the emitter 15. Therefore, when the IGBT is in the on state, there is both electron current (marked by the dotted line in Figure 9) and hole current (marked by the long dashed line in Figure 9) between the collector 14 and the emitter 15.

In the IGBT shown in FIG9 , when the IGBT is in the on state, the electron conduction channel between the collector 14 and the emitter 15 must pass through the p-type semiconductor region 31b. Combined with the simulation results shown in FIG3 , it can be determined that the width of the electron conduction channel passing through the p-type semiconductor region 31b is the bottleneck of the entire electron conduction channel width between the collector 14 and the emitter 15, which to a certain extent hinders the further improvement of the current carrying capacity of the traditional IGBT.

FIG10 is a vertical cross-sectional view of an embodiment of the planar gate IGBT of the present invention. The difference between this IGBT and the IGBT shown in FIG9 is that: in the IGBT shown in FIG9, the p-type conductive region of the semiconductor layer in contact with the emitter (here refers to the p-type semiconductor region 31b) is also in contact with the gate insulating film 51; while in the IGBT shown in FIG10 based on the solution of the present invention, the p-type conductive region of the semiconductor layer in contact with the emitter is not in contact with the gate insulating film 51, and the n-type conductive region (here refers to the n-type semiconductor layer 21b) is between the p-type conductive region in contact with the emitter and the gate insulating film 51. For the convenience of description, we mark the pn junction composed of the p+ type semiconductor region 31a and the n-type semiconductor region 21b as J1, and the pn junction composed of the p-type semiconductor region 31a and the n-type semiconductor region 21b as J2.

For the IGBT shown in FIG10 : when in equilibrium, the pn junction composed of the n-type semiconductor region 21b and the p-type semiconductor region 31b located below the gate insulating film 51 will deplete the electron carriers in the n-type semiconductor layer 21b, and the MIS (metal-insulator-semiconductor) junction composed of the gate electrode 13, the gate insulating film 51 and the n-type semiconductor region 21b located thereunder will also deplete the electron carriers in the n-type semiconductor region 21b. Under the combined action of these two junctions, the carriers in the n-type semiconductor region 21b located between the gate insulating film 51 and the p-type semiconductor region 31b are depleted; when a positive voltage is applied between the collector 14 and the emitter 15, J2 is reverse biased to widen its depletion layer, thereby blocking the current carriers between the collector 14 and the emitter 15. The electron conductive channel, of course, also includes the electron conductive channel from the emitter 15—n+ type semiconductor region 21a—n- type semiconductor region 21b—p+ type semiconductor region 31a—collector 14; when a positive bias is applied between the gate electrode 13 and the emitter 15, a high-concentration electron accumulation area will be formed in the n- type semiconductor region 21b under the gate insulating film 51. This electron accumulation area constitutes a part of the electron conductive channel between the collector 14 and the emitter 15. At this time, when a positive voltage is applied between the collector 14 and the emitter 15, an electron current will flow between the collector 14 and the emitter 15. The path of this electron current (marked by the dotted line in Figure 10) is: collector 14—p+ type semiconductor region 31a—n- type semiconductor region 21b—n+ type semiconductor region 21a—emitter 15. The path of this electron current no longer passes through the p-type semiconductor region 31b. Combined with the simulation results shown in FIG3, it can be determined that through this change in detail, the width of the electron conductive channel between the collector 14 and the emitter 15 is widened, thereby improving the flow capacity of the electron conductive channel, which helps to improve the flow capacity of the IGBT. In addition, when a positive bias is applied between the gate electrode 13 and the emitter 15, it will repel holes, so that a high-concentration hole gathering area will be formed in the p-type semiconductor region 31b under the n-type semiconductor region 21b. This hole gathering area constitutes a part of the hole conductive channel between the collector 14 and the emitter 15. At this time, when a positive voltage is applied between the collector 14 and the emitter 15, a hole current will flow between the collector 14 and the emitter 15. The path of this hole current (marked by the long dashed line in FIG10) is: collector 14-p+ type semiconductor region 31a-n-type semiconductor region 21b-p-type semiconductor region 31b-emitter 15. The electron current and the hole current together constitute the current between the collector 14 and the emitter 15 .

The solution of the present invention is applicable not only to planar gate IGBT, but also to trench gate IGBT, shielded gate IGBT, super junction IGBT, etc., which are not listed one by one.

FIG11 is a vertical cross-sectional view of a first embodiment of a trench MOS pin junction diode according to an embodiment of the present invention. The trench MOS pin junction diode shown in FIG11 includes: a cathode electrode 61, an anode electrode 62, a trench, a trench MOS gate 63 disposed in the trench and wrapped by a gate insulating film 51, an n+ type semiconductor layer 21a in contact with the cathode electrode 61, an n- type semiconductor layer 21b stacked on the n+ type semiconductor layer 21a, a plurality of spaced p+ type semiconductor regions 31a stacked on the n- type semiconductor layer 21b, an n- type semiconductor layer 21b and an n+ type semiconductor layer 21a (corresponding to a conductive region) stacked on the n- type semiconductor layer 21b and located between the insulating film 51 and the p+ type semiconductor region 31a. Among them, the n- type semiconductor layer 21b and the n+ type semiconductor layer 21a are located between the trench MOS gate 63 and the p+ type semiconductor region 31a.

In the trench MOS type pin junction diode shown in FIG11, the region between the p+ type semiconductor layer 31a and the insulating film 51 is the n+ type semiconductor layer 21a and the n- type semiconductor layer 21b. When a forward voltage is applied between the anode electrode 62 and the cathode electrode 61, the trench MOS type pin junction diode shown in FIG11 is forward-conducted, and there are two current paths: the first current path is along the anode electrode 62—n+ type semiconductor layer 21a—n- type semiconductor layer 21b—n+ type semiconductor layer 21a—cathode electrode 61, and this current path has no pn junction barrier; the second current path is along the anode electrode 62—p+ type semiconductor layer 31a—n- type semiconductor layer 21b—n+ type semiconductor layer 21a—cathode electrode 61, and this current path has a pn junction barrier. When the current is small, the current will preferentially flow through the first current path, because this current path has no pn junction barrier, and compared with the traditional pn junction diode, it will have a lower turn-on voltage and lower forward conduction loss; when the current continues to increase to a certain value, in addition to the first current path continuing to flow, a part of the current will flow through the second current path. Therefore, the trench MOS type pin junction diode of the present invention also has the ability to handle large currents and resist surge currents.

In the trench MOS type pin junction diode shown in FIG11, when a reverse voltage is applied between the anode electrode 62 and the cathode electrode 61, on the one hand, the reverse bias of the pn junction composed of the p+ type semiconductor layer 31a and the n-type semiconductor layer 21b will produce longitudinal depletion and lateral depletion effects on the electron carriers in the n-type semiconductor layer 21b; on the other hand, the trench MOS gate repels the electron carriers in the n-type semiconductor layer 21b and produces a lateral depletion effect; under the combined effect of these two depletion effects, the electron carriers in the n-type semiconductor layer 21b located between the gate insulating film 51 and the p+ type semiconductor layer 31a are depleted, and at this time, only a small leakage current flows between the anode electrode 62 and the cathode electrode 61, and the diode is reversely cut off.

As used herein, spatially relative terms, such as "upper," "lower," "upper," "above," "lower," and the like, are used for convenience in describing the relationship between one element or feature shown in the figures and another element or feature. It will be understood that the spatially relative terms are intended to include different orientations of the device in use in addition to the orientation described in the accompanying drawings. For example, if the device in the figure is reversed, elements that are technically described as being "under" or "below" other elements or features will be "above" the other elements or features. Thus, terms such as "under" can include directions of under or over. The device can also be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein interpreted accordingly.

It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims (14)

1. A semiconductor element which is a pn junction field effect transistor, comprising:

A semiconductor layer including at least an n-type conductive region and a p-type conductive region;

An electrode comprising a drain electrode, a source electrode, and a gate electrode, wherein the source electrode is connected with the p-type conductive region;

a gate insulating film interposed between the gate electrode and the semiconductor layer;

The method is characterized in that: the p-type conductive region is not in contact with the gate insulating film, a conductive region is arranged between the p-type conductive region and the gate insulating film, the conductive region is composed of a semiconductor with a conductivity type different from that of p-type conductivity or composed of a conductor, and the conductive region enables the electron concentration of a conductive channel formed between the drain electrode and the source electrode to be increased under the action of the bias voltage of the gate electrode.

2. The semiconductor element according to claim 1, wherein the semiconductor of a conductivity type different from p-type conductivity is an n-type doped conductive semiconductor, an unintentionally doped intrinsic state semiconductor, or an intentionally doped high-resistance state semiconductor.

3. The semiconductor device according to claim 1, wherein the width of the conductive region is in a range of 3nm to 300 nm.

4. The semiconductor device according to claim 4, wherein the width of the conductive region is in a range of 3nm to 100 nm.

5. The semiconductor element according to claim 1, wherein the pn junction field effect transistor is a lateral MOSFET or a vertical MOSFET.

6. The semiconductor device according to claim 5, wherein the vertical MOSFET is a vertical planar gate MOSFET, a vertical trench gate MOSFET, a vertical shield gate MOSFET, or a vertical superjunction MOSFET.

7. The semiconductor element according to claim 1, wherein the semiconductor layer is composed of an elemental semiconductor, a compound semiconductor, or an oxide semiconductor.

8. A semiconductor element which is an insulated gate bipolar transistor, comprising:

A semiconductor layer including at least an n-type conductive region and a p-type conductive region;

an electrode including an emitter electrode, a collector electrode, and a gate electrode;

a gate insulating film interposed between the gate electrode and the semiconductor layer; the method is characterized in that:

The p-type conductive region of the semiconductor layer connected to the emitter is not in contact with the gate insulating film, and a conductive region is provided between the p-type conductive region of the semiconductor layer connected to the emitter and the gate insulating film, the conductive region being composed of a semiconductor having a conductivity type different from that of the p-type conductivity or composed of a conductor, and the conductive region being configured such that an electron concentration of a conductive channel formed between the emitter and the collector is increased under the effect of the gate electrode bias.

9. The semiconductor element according to claim 8, wherein the semiconductor having a conductivity type different from that of the p-type conductivity is an n-type doped conductive semiconductor, an unintentionally doped intrinsic state semiconductor, or an intentionally doped high-resistance state semiconductor.

10. The semiconductor device according to claim 8, wherein a width of the conductive region is in a range of 3nm to 300 nm.

11. The semiconductor element according to claim 8, wherein the insulated gate bipolar transistor is a planar gate IGBT, a trench gate IGBT, a shielded gate IGBT, or a superjunction IGBT.

12. A semiconductor element that is a trench MOS type pin junction diode, the trench MOS type pin junction diode comprising:

A first n-type semiconductor layer;

a second n-type semiconductor layer stacked over the first n-type semiconductor layer, the second n-type semiconductor layer having a donor concentration less than that of the first n-type semiconductor layer;

A p-type semiconductor region stacked over the second n-type semiconductor layer;

A trench MOS gate;

An anode electrode formed on the upper surfaces of the p-type semiconductor region and the trench MOS gate;

A cathode electrode formed on a surface of the first n-type semiconductor layer opposite to the second n-type semiconductor layer;

the method is characterized in that: and a conductive region is further arranged, the conductive region is laminated on the second n-type semiconductor layer, the conductive region is positioned between the trench MOS gate and the p-type semiconductor region, and the conductive region is composed of a semiconductor with a conductivity type different from that of the p-type semiconductor or a conductor.

13. The semiconductor element according to claim 12, wherein the semiconductor having a conductivity type different from that of the p-type conductivity is an n-type doped conductive semiconductor.

14. The semiconductor device according to claim 12, wherein a width of the conductive region is in a range of 3nm to 200 nm.