CN118737847A - Method for manufacturing semiconductor device, corresponding semiconductor device and mounting assembly - Google Patents

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device, a corresponding semiconductor device and a mounting assembly. A "packageless" integrated circuit semiconductor device is manufactured by laminating first and second insulating films on opposite first and second surfaces of a semiconductor wafer having a semiconductor die integrated thereon. A conductive structure toward a die pad of the semiconductor die is provided in a via opening through the first insulating film laminated on the first surface of the semiconductor wafer and leading to the semiconductor wafer. The semiconductor wafer provided with these conductive structures is divided at a separation line between adjacent semiconductor dies to produce separate semiconductor devices. Each device has: opposite first and second device surfaces, a protective portion having first and second insulating films laminated thereon, and side surfaces extending between the opposite first and second device surfaces, which side surfaces are not covered by the first and second insulating films.

Description

Method for manufacturing semiconductor device, corresponding semiconductor device and mounting assembly

Priority claim

This application claims the benefit of priority from Italian Patent Application No. 102023000005985, filed on March 29, 2023, the entire contents of which are incorporated herein by reference to the maximum extent permitted by law.

Technical Field

This description relates to fabricating semiconductor devices.

The solutions described herein can be applied to power (integrated circuit) semiconductor devices, for example, in automotive or consumer products.

Background Art

There are various manufacturing methods for producing devices for the automotive and/or consumer markets.

Desirable qualities of such manufacturing methods include low production cost, simplicity of manufacturing process and reduced package size.

A conventional approach to reducing package size is the so-called wafer-level chip-scale packaging (WLCSP). This approach involves (soldering) ball mounting of the final device on a substrate like a printed circuit board (PCB). However, it should be appreciated that mounting the balls on the package is not a simple assembly step.

Another conventional and widely used approach is based on the so-called quad flat no-lead (QFN) package, which is based on the use of a substrate (eg a lead frame).

The substrate for QFN packages requires special design, ie, depending on the specific device design, and such customized leadframes may involve high costs.

Furthermore, conventional approaches are based on wire interconnects, which have been observed to introduce undesirable resistance, thereby degrading the electrical performance of the device.

By way of background, the following documents are incorporated herein by reference:

C-H Chien, et al.: “Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization”, International Microelectronics Symposium, 1October 2016; 2016(1):000013–000017;

N. Kumbhat, et al.: “Chip-last fan-out package with embedded power ICs in ultra-thin laminates” Proceedings of the Conference on Electronic Components and Technology, 1372-1377;

U.S. Patent Nos. 9,502,336 and 10,636,734;

The above-mentioned documents are examples of various recent advances in semiconductor device manufacturing methods, aiming at achieving low production cost, simplicity of manufacturing process and reduction of package size.

There is a need in the art for solutions directed to addressing the aforementioned problems.

Summary of the invention

One or more embodiments are directed to a method.

One or more embodiments relate to a corresponding (integrated circuit) semiconductor device.

One or more embodiments are directed to a corresponding mounted assembly (ie, a semiconductor device mounted on a support member such as a printed circuit board PCB).

The solution described herein proposes a simple and cost-effective method for manufacturing semiconductor devices with the aim of reducing the size of the final package.

In the solution described herein, the manufacturing process can be performed entirely at wafer level.

In the solution as described herein, the external metal pads are finished with a solderable layer to facilitate final mounting on a substrate.

In the solution described herein, wire interconnects are advantageously replaced with direct metal interconnects provided via an electroplating process.

The solutions described herein can also be used to provide a final device with wettable flanks.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

1A to 1J are steps in sequence showing a conventional manufacturing process of a semiconductor device;

2A to 2K are examples of the order of steps in an embodiment of implementing the present description;

FIG. 3 is a cross-sectional view of a device according to an embodiment of the present description mounted on a substrate; and

4A through 4C are intended to provide an example of an alternative sequence of steps for a device having wettable sides as described herein.

DETAILED DESCRIPTION

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The edges of a feature drawn in a drawing do not necessarily indicate the end of the extent of the feature.

In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

Furthermore, in one or more embodiments, the particular conformations, structures or characteristics may be combined in any suitable manner.

The headings/references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

For simplicity and ease of explanation, throughout the specification, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals in the various drawings, and the corresponding description is not repeated for each drawing.

There are various manufacturing processes that involve concurrent processing of multiple (integrated circuit) semiconductor devices.

As described above, this conventional approach may have various disadvantages. For example, standard wafer level chip scale packaging (WLCSP) involves ball mounting the final device on a substrate (eg, a printed circuit board (PCB)), and providing solder balls to the package is not a simple process step.

On the other hand, the quad flat no-lead (QFN) package does not involve ball mounting because the lead frame can be directly soldered to the PCB; however, providing a customized lead frame according to the device design may involve high production costs.

The sequence of FIGS. 1A to 1J illustrates a conventional manufacturing process for an integrated circuit semiconductor device.

This process is often referred to as wafer/panel-level fan-out packaging.

1A shows an insulating film 100 disposed on a semiconductor (eg, silicon) wafer 14 including integrated circuits, ICs (chips or dies) formed therein for possible processing together. As used throughout this specification, the terms chip and die are considered synonymous.

For the sake of simplicity, these circuits (which may be arranged in wafer 14 in any manner known to those skilled in the art) are not visible in the figure.

The membrane 100 may be, for example, a membrane such as Ajinomoto stacked film (ABF), which is available from Ajinomoto Fine Technology Co., Ltd., 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki, Japan, 210-0801.

Thin film 100 may be laminated on a first (active) surface of wafer 14 .

FIG. 1B illustrates a via 181' opening (e.g., via a laser beam) toward the active surface of the wafer 14 to a die pad (not visible in the figure for reasons of scale).

In a first singulation step via a blade or saw B, the wafer 14 may be cut (singulated) into individual dies or chips 140 , for example as shown in FIG. 1C .

As shown in FIGS. 1A-1C , the steps discussed are performed at the wafer level.

According to conventional methods, after the first segmentation step (as shown in FIG. 1C ), concurrent processing of multiple devices can be performed after the wafer or panel has been reconstructed; that is, a single (segmented) die 140 is arranged on a carrier (wafer or formed panel) to facilitate concurrent processing of the devices.

FIG. 1D shows individual chips/dies 140 arranged on a first carrier C (eg, a stainless steel carrier) having a release tape laminated thereon (not labeled in the figure for simplicity).

As known to those skilled in the art, such a release tape facilitates separation and subsequent transfer of die 140 from carrier C.

As shown in FIG. 1D , in this step, the dies 140 may be flipped (i.e., flipped so that their active surfaces face toward the carrier C, e.g., so that the active surfaces face downward) and arranged by allowing greater spacing between adjacent dies 140 relative to what is typically done for a fan-out wafer (panel) level packaging process FOW(P)LP.

As described below, the fan-out region may be used to provide space for a redistribution layer. The actual size of the "fan-out" region may depend on the desired device design.

FIG. 1E illustrates a molding step in which an insulating molding compound 16 (eg, epoxy) is molded onto the die 140 to provide a protective plastic package.

As shown in FIG. 1F , the wafer/panel (i.e., the device 140 held together by the molding compound 16 ) is released from the first carrier C and transferred to a second carrier (again indicated by the same reference numerals in the figure for simplicity, it being understood that different carriers may be used) with the active surface facing upward (i.e., opposite to the carrier) to facilitate further processing of the surface of the wafer/panel.

1G shows a redistribution layer RL provided at the active surface of the die 140 in the panel. As known to those skilled in the art, a redistribution layer (e.g., RL in FIG. 1G ) is a metal (e.g., copper) layer including conductive lines/traces for rerouting input/output (I/O) pads of an integrated circuit.

Note that the vias 181 are now plated with metal (eg, copper) to provide a conductive path from the die pad (not visible in the figure due to scale) on the active surface of the die 140 to the redistribution layer RL.

The redistribution layer RL as shown in Figure 1G may be provided by a photolithographic deposition/growth process, which is conventional in the art per se. A more detailed description of such a method will be given below when describing the embodiments of the present specification.

The redistribution layer RL shown in FIG. 1G comprises only one layer; in some cases, multiple layers may be provided to reroute the die pads to external pads (eg, studs 12 illustrated in FIGS. 1H to 1J ), each layer being provided via a photolithography/electroplating deposition process.

1H shows studs/external pads 12 disposed on top of the redistribution layer RL. The studs 12 may be grown via a process similar to that used to form the redistribution layer RL.

FIG. 1I shows an insulating film 110 (eg, another - possibly different - ABF) laminated on the wafer/panel assembly to provide an insulating/protective layer to the device.

Alternatively, the protective plastic encapsulation may be completed via a second molding step of an insulating molding compound such as epoxy.

Either option (eg, laminating a sufficiently thick film or applying a second compression mold layer) helps encapsulate the device traces and studs.

Film (eg, ABF) lamination may use a laminator to heat a film foil as large as the entire panel, which is unrolled over the panel via a combination of vacuum and pressure.

After packaging is completed, such as by insulating film lamination or resin molding, the wafer/panel can be separated from the carrier.

1J illustrates a second (final) singulation step, in which the panel/wafer is cut (e.g., via sawing) into individual devices 10. This second singulation step may be performed after a final plating step of the input/output (I/O) studs 12 in order to enhance solderability (e.g., on a final substrate such as a printed circuit board PCB).

As mentioned above, this manufacturing process, often referred to as Fan-Out Wafer (Panel) Level Packaging (FOW(P)LP), is conventional in the art, such that a more detailed description need not be provided herein.

Additionally, the sequence of FIGS. 1A to 1J is intended to merely give a schematic description of a conventional manufacturing process.

In particular: one or more steps shown in Figures 1A to 1J may be omitted, performed in a different manner (e.g., with other tools) and/or replaced by other steps; additional steps may be added; and one or more steps may be performed in an order different from that shown.

There are situations where a simpler process is needed. For example, certain products for the automotive or consumer markets can benefit from simplification of the manufacturing process, which translates into lower production costs and shorter processing times.

The solution described herein aims to provide a simple and cost-effective method for manufacturing semiconductor devices.

In the solution described herein, the manufacturing process can be performed entirely at wafer level.

In the solution described herein, insulating films laminated on opposing surfaces of the wafer replace conventional plastic packaging, thereby reducing the size of the device and making the molding step unnecessary.

In the solution described herein, external pads disposed on the active surface of a wafer may be trimmed with a solderable protective layer.

The solution described herein in connection with FIGS. 2A to 2K may optionally be modified as illustrated in FIGS. 4A to 4C in order to provide a final device having wettable sides.

Also note that the order of FIGS. 2A-2K and 4A-4C is intended to give only exemplary representations of the relevant processes.

For example: one or more steps shown in Figures 2A to 2K and Figures 4A to 4C may be omitted, performed in a different manner (e.g., with other tools) and/or replaced with other steps; additional steps may be added; one or more steps may be performed in an order different from the order shown.

The representations in FIGS. 2A and 2B are themselves identical to those in FIGS. 1A and 1B .

FIG. 2A again shows an insulating film 101 laminated on a first (upper in the figure) surface of a semiconductor (eg silicon) wafer 14 having integrated circuits IC already formed therein in a manner known to those skilled in the art so that these can be processed simultaneously.

Furthermore, the film 101 may be, for example, a film such as the Ajinomoto built-up film (ABF) that has been mentioned above.

2B shows a via hole 181' opening toward the die pad 141 located at the first active surface of the wafer 14. As indicated by LB, the via hole 181' may be provided at a desired position of the insulating film 101 by laser ablation.

However, in contrast to FIG. 1C , the components of FIG. 2B are not “divided” and are in fact subject to various types of processing.

For example, in order to reduce the thickness of the wafer 14, a grinding step may be advantageously performed as indicated by G in Figure 2C. This step may be used to minimize the thickness of the final device.

FIG. 2D shows a second insulating film 102 laminated on a second surface of the wafer 14, which is opposite to the surface on which the film 101 is laminated.

For example, the second insulating film 102 may also be a film such as Ajinomoto built-up film (ABF), which has been mentioned above, but is not necessarily of the same type as the first insulating film 101. For example, different thicknesses and/or chemical compositions are conceivable for the second insulating film 102.

For example, the film 102 may be different from the film 101 and/or either of the films 101 , 102 may be a molded film for protecting the (eg, backside) side of a semiconductor wafer.

Different types of ABF/mold films can be used as needed, for example according to specific requirements.

As shown, applying the second insulating film 102 on the second surface of the wafer 14 may include flipping the wafer 14 , as this may facilitate associated processing.

However, in an implementation, laminating insulating films (e.g., 101 and 102) on both surfaces of wafer 14 can facilitate providing protection to wafer 14 (and therefore to the ICs formed therein) without using, for example, plastic packaging (e.g., as provided by a molding compound as illustrated in FIG. 1J ), which would involve an additional molding step.

Replacing conventional packages with insulating films (eg, 101 and 102) is advantageous in terms of both simplicity of assembly process and final package size.

As will be described below, after singulation of the wafer assembly (shown in FIGS. 2K and 4C ), the final device 20 produced in accordance with an embodiment of the present specification may leave the semiconductor material (e.g., silicon) of the wafer 14 exposed on its lateral surfaces (or, in any case, not covered by films 101 and 102 ).

That is, as shown herein, dividing (e.g., via blade B) the semiconductor wafer 14 produces individual semiconductor devices 20, each semiconductor device 20 having opposing first and second device surfaces (corresponding to opposing surfaces of the wafer 14), the first and second device surfaces having respective portions of the first and second insulating films 101, 102 laminated thereon and a side surface 142 extending between the opposing first and second device surfaces.

It has been observed that laminating the insulating films 101, 102 (only) on the opposite first and second surfaces of the wafer 14 (and on the opposite first and second surfaces of the final device after segmentation) is beneficial for providing sufficient protection for the IC included in the wafer 14 (device 20) while facilitating reducing the package size.

2E to 2I illustrate steps that may be performed on the assembly of FIG. 2D having insulating films 101 , 102 laminated on two opposing surfaces thereof.

FIG. 2E shows a (photolithographic) process of providing external pads for the ICs in wafer 14 by growing a metallic (eg copper) material on a first (active) surface of wafer 14 .

2E shows the growth/deposition (eg, by sputtering) of a seed layer 200 on the first insulating film 101. As known to those skilled in the art, growing such a seed layer 200 may include, for example, first depositing a Ti layer and then depositing a Cu layer.

The seed layer (eg, 200 ) facilitates the growth of additional metal (eg, copper) material, such as via electrolytic/galvanic plating.

FIG. 2F shows a photoresist material DF provided on the first (active) surface of the wafer 14 , ie, on the seed layer 200 thereon.

Dry film DF may advantageously be used for this step; the thickness of dry film DF may be selected according to the device design, since the "height" of the external pads (shown in FIG. 2I and denoted here by reference numeral 12) is determined by the thickness of dry film DF.

For example, the thickness of the dry film DF may be selected in consideration of, for example, the desired thickness (height) of a copper pad grown therein.

FIG. 2G shows a dry film DF patterned by laser direct imaging (LDI) and subsequently developed to transfer a desired pattern onto the dry film DF.

It should be noted that such patterning may advantageously replace providing (eg, via a back end of line or BEOL process) a “redistribution” layer to redistribute pads of the (IC) dies formed in wafer 14 as used in some conventional device designs.

In the solution described herein, such a redistribution layer (similar to the redistribution layer RL shown in Figure 1G) can be avoided, where the pattern transferred to the dry film DF (shown in Figure 2G) only includes openings at the pads of the tube core in the chip 14, and there are no metal traces or wiring.

Therefore, as shown in Figure 2G, the pattern transferred to the dry film DF (via the laser beam LB) may consist (only) of holes/openings located at the via openings 181'.

2H shows a conductive (eg, metal such as copper) material deposited/grown on the patterned dry film DF, facilitated by the seed layer 200. Such a plating step may be performed, for example, by electrolytic/galvanic plating.

A stud or (external) pad 12 is formed at the via 181 of the first insulating film 101; the opening 181' of the first insulating film 101 (e.g. as shown in Fig. 2G) is now plated with a conductive material, such as copper.

These are indicated generally at 181 (again not with single quotes for emphasis) and provide electrical coupling between the pads of the IC on the first (active) surface of the wafer 14 and the studs 12 .

The dry film DF is stripped off and the seed layer 200 is etched away (where it is not covered by the metal material of the via 181 and the pillar 12), thereby obtaining the assembly shown in FIG. 2I.

FIG. 2J illustrates a trimming step of the pad/stud 12 , where an additional layer 300 may be deposited on the pad 12 to enhance solderability.

This layer may include a Ni layer (eg, provided via an electroless plating process) and an Au layer (eg, provided via immersion in a gold salt bath), resulting in a finish commonly referred to as electroless nickel immersion gold (ENIG).

ENIG trimming itself is conventional in the art and enhances the solderability of the external pads 12 and provides a protective layer against oxidation of the external pads 12 .

Alternatively, the metal layer 300 may be an electroless Ni-electroless Pd-immersion Au (ENEPIG) trim having the same purpose as the ENIG layer (ie, enhanced solderability and oxidation prevention).

FIG. 2K shows a singulation step, in which the wafer 14 is finally cut (singulated) into individual devices 20 , for example via sawing with a blade B. FIG.

The individual devices 20 shown in FIG. 2K include respective portions of a semiconductor (eg, silicon) wafer 14 , each having at least one semiconductor die integrated therein.

The final device 20 as shown in FIG. 3 may be mounted on a substrate S such as a printed circuit board (PCB) via a solder material SM.

3 includes first and second insulating films 101, 102 laminated on opposite first and second surfaces of a portion of a semiconductor wafer 14. The device has one or more semiconductor dies 140 integrated therein, the die 140 having a die pad 141 on a first surface.

The conductive structure 12 , 181 is disposed toward the die pad 141 , which includes, for example, a metal such as copper (Cu).

The conductive structure 12, 181 extending in the via hole 181' is opened (e.g., by a laser beam LB) in the first insulating film 101 laminated on the first surface.

Device 20 as shown in FIG. 3 includes side surfaces 142 extending between opposing first and second surfaces.

These side surfaces 142 are not covered by the first and second insulating films 101 , 102 .

3 , the final device 20 may have the semiconductor material (e.g., silicon) of the wafer 14 exposed on its side 142. For example, if not otherwise covered, the semiconductor die 140 is visible on the side 142 of the device 20 because the films 101, 102 are "covered" (only) laminated on its opposing first and second surfaces.

That is, as shown herein, dividing (e.g., via blade B) the semiconductor wafer 14 produces individual semiconductor devices 20, each semiconductor device 20 having opposing first and second device surfaces (corresponding to opposing surfaces of the wafer 14), the first and second device surfaces having respective portions of first and second insulating films 101, 102 laminated thereon and a side surface 142 extending between the opposing first and second device surfaces.

It can be seen that the side surface 142 is not covered by the first and second insulating films 101 and 102. It can further be seen that the individual semiconductor devices 20 are not encapsulated by an encapsulation material other than said first and second insulating films.

As described above, it has been observed that laminating insulating films 101, 102 on (only) opposing first and second surfaces of device 20 can provide adequate protection for an IC including the device (in the absence of other packaging materials) while maintaining a reduced package size.

This is primarily in contrast to conventional arrangements where a molding compound (eg, epoxy) is molded onto the device to complete its plastic encapsulation, thereby also covering the side surfaces (eg, see FIG. 1J ).

The external pads 12 may advantageously be trimmed with a layer of ENIG or ENEPIG for enhanced solderability and protection (eg, from oxidation).

The metal features (vias 181 and pads/studs 12 ) may be provided by a photolithography electroplating process (as described previously), possibly leaving a seed layer 200 underneath the metal features 181 , 12 .

The sequence of Figures 4A to 4C illustrates processing steps directed toward providing a device 20 having wettable sides.

As known to those skilled in the art, wettable sides are a desirable feature that aids in forming a solder meniscus when the device is mounted (via solder material) on a final substrate (eg, a PCB).

In addition to benefiting the integrity/reliability of the solder joint, the solder meniscus facilitates visual inspection and testing of the solder joint by automated optical inspection (AOI).

Fig. 4A shows a partial cut (e.g., by a first blade B2) made on a semiconductor wafer 14 having metal features 181, 12 formed on its first/active surface. That is, Fig. 4A is obtained by making a partial cut on the processed wafer 14 as shown in Fig. 2I, and the sequence of Figs. 4A to 4C represents an alternative sequence of steps.

Partial cutting is performed at the cutting line CL of the final singulation cut (shown in FIG. 4C ) so as to expose the side surfaces of the pads 12 located at the periphery of the device (at the periphery of the device).

Figure 4B shows a trimming step of the pad/stud 12, where a layer of ENIG or ENEPIG 300 is deposited on the pad 12 to enhance solderability and provide protection against oxidation. This step is similar to the step shown in Figure 2J.

FIG. 4C shows the final singulation step, in which the wafer 14 is cut (eg, by sawing with a second blade B) into singulated devices 20 .

A second blade B different from the first blade B2 may be used to perform the segmentation step shown; for example, a second blade B thinner than the first blade B2 may be used, which results in a "step" (an undercut) shown in FIG. 4C and is denoted herein by reference numeral WF.

The claims are an integral part of the technical teaching provided with respect to the embodiments.

Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection, which is determined by the appended claims.

Claims (17)

1. A method, comprising:

laminating a first insulating film and a second insulating film on opposing first and second surfaces of a semiconductor wafer having a plurality of semiconductor die integrated therein, the semiconductor die having a die pad at the first surface;

Opening a via hole penetrating through the first insulating film laminated on the first surface of the semiconductor wafer to the semiconductor wafer;

Providing a conductive member toward the die pad, the conductive member extending in the via; and

Dividing the semiconductor wafer provided with the conductive member at a dividing line between adjacent semiconductor dies of the plurality of semiconductor dies;

Wherein dividing the semiconductor wafer produces individual semiconductor devices, each semiconductor device having: opposite first and second device surfaces, and side surfaces of the semiconductor wafer singulated; portions of the first and second insulating films are laminated on the opposing first and second device surfaces, with side surfaces of the semiconductor wafer being divided extending between the opposing first and second device surfaces, the side surfaces not being covered by the first and second insulating films.

2. The method of claim 1, wherein providing the conductive member toward the die pad comprises: a conductive material is grown at the via through the first insulating film laminated on the first surface of the semiconductor wafer to the semiconductor wafer.

3. The method of claim 2, wherein providing the conductive member toward the die pad comprises: a contact pad is provided on the first insulating film laminated on the first surface of the semiconductor wafer.

4. The method of claim 3, wherein providing a contact pad on the first insulating film laminated on the first surface of the semiconductor wafer comprises: electroplating deposition is performed.

5. A method according to claim 3, comprising: the contact pads are trimmed with a solderable protective electroless nickel-plated gold-plated ENIG layer or an electroless nickel electroless palladium-plated gold-plated ENEPIG layer.

6. The method according to claim 1, wherein one or both of the first insulating film and the second insulating film is a monosodium glutamate deposited film.

7. The method according to claim 1, comprising:

providing selected ones of the conductive members toward the die pad at the split line between adjacent semiconductor dies;

Wherein dividing the semiconductor wafer at the dividing lines between adjacent semiconductor die comprises: the semiconductor wafer is partially diced starting from the first surface of the semiconductor wafer on which the first insulating film is laminated, wherein a wettable side is formed at selected ones of the conductive members in response to the partial dicing.

8. The method of claim 1, wherein the side surfaces not covered by the first and second insulating films are made of a semiconductor material of the wafer.

9. The method of claim 1, wherein each individual semiconductor device is not encapsulated by an encapsulation material other than the first insulating film and the second insulating film.

10. A semiconductor device, comprising:

A first insulating film and a second insulating film laminated on opposing first and second surfaces, respectively, of a portion of a semiconductor wafer having at least one semiconductor die integrated therein, the semiconductor die having a die pad at the first surface;

A conductive member extending in a via hole opened in the first insulating film laminated on the first surface to be connected with the die pad; and

Wherein a side surface of the at least one semiconductor die extends between the opposing first and second surfaces, wherein the side surface is not covered by the first and second insulating films.

11. The semiconductor device of claim 10, wherein selected ones of the conductive members have wettable sides.

12. The semiconductor device according to claim 10, further comprising a contact pad on the first insulating film.

13. The semiconductor device of claim 12, further comprising a solderable protective trim layer on the contact pad, the solderable protective trim layer comprising one of an electroless nickel-plated gold ENIG layer or an electroless nickel-plated palladium-plated gold ENEPIG layer.

14. The semiconductor device according to claim 10, wherein one or both of the first insulating film and the second insulating film is a monosodium glutamate stacked film.

15. The semiconductor device according to claim 10, wherein the side surface not covered by the first insulating film and the second insulating film is made of a semiconductor material of the wafer.

16. The semiconductor device according to claim 10, wherein the semiconductor device is not encapsulated by an encapsulation material other than the first insulating film and the second insulating film.

17. An assembly, comprising:

A semiconductor device support; and

The semiconductor device of claim 10, wherein the semiconductor device is electrically coupled to the semiconductor device support via the conductive member.