CN118737021A - Display device and driving method thereof - Google Patents

Abstract

The present invention discloses a display device and a driving method thereof. The display device includes at least two display areas, at least one shift circuit and at least one data line, wherein the data line connects at least two display areas; the data lines of corresponding columns between adjacent display areas are connected through a shift circuit, and the shift circuit is used to shift the data voltage on the data line in the previous display area to the data line in the next display area in response to a clock signal. The display device provided in this embodiment first shifts the data voltage and then scans, so that the entire display device can realize the writing and scanning of the data voltage by a timing control chip and a driving chip. Compared with the existing spliced display device, the number of chips in the display device can be reduced, and the cost and power consumption can be reduced. At the same time, the data voltage is shifted first, so that each display area can be scanned line by line at the same time, reducing the scanning time of the entire device.

Description

Display device and driving method thereof

Technical Field

The present invention relates to the field of display technology, and in particular to a display device and a driving method thereof.

Background Art

Micro-LED (Micro-Light Emitting Diode, Micro-LED) is a new generation of display technology. Compared with the existing Organic Light-Emitting Diode (Organic Light-Emitting Diode, OLED) or Liquid Crystal Display (Liquid Crystal Display, LCD) technology, it has the advantages of high resolution, high brightness, ultra-power saving, fast response speed, high light output efficiency and long life. It is widely used in display fields such as mobile phones, laptops and TVs.

Since Micro-LED or Mini-LED is packaged in particles, it is not necessary to ship the whole large screen. Generally, it adopts a spliced form, that is, multiple boxes are spliced into Micro-LED to facilitate shipment and debugging.

However, after Micro-LED adopts a spliced form, each box requires a driving system, which greatly increases the cost, box thickness and driving power consumption.

Summary of the invention

The present invention provides a display device and a driving method thereof, so as to reduce the cost and power consumption of the device and shorten the scanning time.

According to one aspect of the present invention, there is provided a display device, comprising: at least one shift circuit and at least one data line, wherein the data line connects at least two display areas;

The data lines of corresponding columns between adjacent display areas are connected through the shift circuit, and the shift circuit is used to shift the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal.

Optionally, the shift circuit includes: a first node control unit, a cache unit, a second node control unit, a data transmission unit and a voltage follower unit;

The first end of the first node control unit is electrically connected to the data line of the corresponding column in the previous display area, the second end of the first node control unit is electrically connected to the control end of the cache unit, the control end of the first node control unit is connected to the clock signal, the first end of the cache unit is connected to the fixed potential signal, the second end of the cache unit is electrically connected to the first end of the second node control unit, the second end of the second node control unit is electrically connected to the control end of the data transmission unit, the control end of the second node control unit is connected to the clock signal, the input end of the voltage follower unit is electrically connected to the control end of the cache unit, the output end of the voltage follower unit is electrically connected to the first end of the data transmission unit, and the second end of the data transmission unit is connected to the data line of the corresponding column in the next display area.

Optionally, the first node control unit is used to respond to the clock signal and transmit the data voltage on the connected data line to the control end of the cache unit;

and/or, the cache unit is used to store the data voltage and transmit a fixed potential signal to the first end of the second node control unit in response to the data voltage;

And/or, the second node control unit is used to transmit the fixed potential signal to the control end of the data transmission unit in response to the clock signal;

And/or, the voltage follower unit is used to transmit the data voltage to its own output terminal;

And/or, the data transmission unit is used for transmitting the data voltage outputted by the output terminal of the voltage follower unit to a data line in the next display area in response to the fixed potential signal;

Optionally, the first node control unit includes a first transistor, a first electrode of the first transistor is electrically connected to the data line connected to the corresponding column in the previous display area, a second electrode of the first transistor is electrically connected to the control end of the cache unit, and a gate of the first transistor is connected to the clock signal;

Optionally, the cache unit includes a second transistor and a storage capacitor, a first electrode of the second transistor is connected to the fixed potential signal, a second electrode of the second transistor is electrically connected to a first end of the second node control unit, a gate of the second transistor is electrically connected to a second end of the first node control unit, a first end of the storage capacitor is electrically connected to the gate of the second transistor, and a second end of the storage capacitor is connected to the fixed potential signal;

Optionally, the second node control unit includes a third transistor, a first electrode of the third transistor is electrically connected to the second end of the cache unit, a second electrode of the third transistor is electrically connected to the control end of the data transmission unit, and a gate of the third transistor is connected to the clock signal;

Optionally, the voltage follower unit includes an operational amplifier follower, a first input end of the operational amplifier follower is electrically connected to the control end of the cache unit, a second input end of the operational amplifier follower is electrically connected to its own output end, and an output end of the operational amplifier follower is electrically connected to the first end of the data transmission unit;

Optionally, the data transmission unit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the output end of the voltage follower unit, a second electrode of the fourth transistor is electrically connected to a data line connected to a corresponding column of the next display area, and a gate of the fourth transistor is electrically connected to the second end of the second node control unit.

Optionally, the clock signal includes an alternating first potential signal and a second potential signal, the first potential signal and the second potential signal are high and low level signals to each other; the first node control unit is used to respond to the first potential signal to turn on, or respond to the second potential signal to turn off, and transmit the data voltage on the connected data line to the control end of the cache unit when it is turned on;

The second node control unit is used to be turned on in response to the second potential signal, or turned off in response to the first potential signal, and transmit the fixed potential signal connected to the cache unit to the control end of the data transmission unit when turned on;

Optionally, along the extension direction of the data line, the types of the first transistors and the types of the third transistors of two adjacent shift circuits are opposite.

Optionally, all the shift circuits include first transistors of the same type, second transistors of the same type, third transistors of the same type, and fourth transistors of the same type;

Optionally, the first transistor and the fourth transistor are of the same type, the second transistor and the third transistor are of the same type, and the first transistor and the third transistor are of opposite types;

Alternatively, the first transistor and the second transistor are of the same type, the third transistor and the fourth transistor are of the same type, and the first transistor and the third transistor are of opposite types.

Optionally, the display device further comprises a plurality of scan lines, and each display area is used to respond to a scan signal on a corresponding scan line and write the data voltage on the data line in the display area row by row after the data voltage shift of all the display areas is completed.

Optionally, the display device includes a plurality of spliced display panels, and at least two of the display areas belong to different display panels.

According to another aspect of the present invention, a method for driving a display device is provided, for driving any of the above-mentioned display devices, the driving method comprising:

The shift circuit shifts the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal.

Optionally, the clock signal includes an alternating first potential signal and a second potential signal, the first potential signal and the second potential signal are high and low level signals to each other, and the shift circuit shifts the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal, including:

The shift circuit connected between the Kth display area and the K-1th display area is used to respond to the first potential signal to cache the data voltage on the data line in the K-1th display area into the shift circuit, and is also used to respond to the second potential signal to transmit the cached data voltage to the data line in the Kth display area; wherein K≥2.

Optionally, the clock signal includes an alternating first potential signal and a second potential signal, the first potential signal and the second potential signal are high and low level signals to each other, and the shift circuit shifts the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal, including:

The shift circuit connected between the Kth display area and the K-1th display area is used to respond to the first potential signal and cache the data voltage on the data line in the K-1th display area into the shift circuit, and the shift circuit connected between the Kth display area and the K+1th display area is used to respond to the first potential signal and transmit the data voltage cached by the shift circuit to the data line in the K+1th display area;

The shift circuit connected between the Kth display area and the K-1th display area is also used to respond to the second potential signal to transmit the data voltage cached by the shift circuit to the data line in the Kth display area, and the shift circuit connected between the Kth display area and the K+1th display area is also used to respond to the second potential signal to cache the data voltage on the data line in the Kth display area into the shift circuit; wherein, K≥2.

The display device provided by the embodiment of the present invention includes at least two display areas, at least one shift circuit and at least one data line, and the data line connects at least two display areas; the shift circuit is used to shift the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal. The display device includes a plurality of sub-pixels arranged in an array. When the display device is used for display, the data voltages required for the same column of sub-pixels in different display areas to display may be different. Through the shift circuits arranged between adjacent display areas, after multiple pulses of the clock signal, the different data voltages are shifted to the corresponding display area. Among them, one display area can be regarded as a display panel, and multiple display panels are spliced to form a display device. After the data voltage shift of all display areas is completed, each display area starts scanning at the same time to write the data voltage. The display device provided in this embodiment first shifts the data voltage and then scans, so that the entire display device can realize the writing and scanning of the data voltage by a timing control chip and a driver chip. Compared with the existing spliced display device, the number of chips in the display device can be reduced, and the cost and power consumption can be reduced. At the same time, the data voltage is shifted first, so that each display area can be scanned line by line at the same time, thereby reducing the scanning time of the entire device.

It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic structural diagram of a display device;

FIG2 is a schematic structural diagram of a display device provided by an embodiment of the present invention;

3 is a schematic structural diagram of a shift circuit of a display device provided by an embodiment of the present invention;

4 is a schematic structural diagram of another shift circuit of a display device provided by an embodiment of the present invention;

FIG5 is a driving timing diagram of a display device provided by an embodiment of the present invention;

6 is a schematic structural diagram of another shift circuit of a display device provided by an embodiment of the present invention;

7 is a schematic structural diagram of another shift circuit of a display device provided by an embodiment of the present invention;

8 is a flow chart of a method for driving a display device provided by an embodiment of the present invention;

FIG. 9 is a flow chart of another method for driving a display device provided by an embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

As described in the background art, the existing Micro-LED in a spliced form is costly and consumes high power. FIG1 is a schematic diagram of the structure of a display device, which may be a Micro-LED formed by splicing a plurality of boxes 01. Each box 01 includes at least two array substrates 011, a support substrate 012, and a driving component 013. Each box is an independent driving environment. The control signal of each box 01 is supplied by a unified timing control chip (TCON IC). The driving component 013 includes a sub-timing control chip (Sub-TCON IC). After receiving the signal from the TCON IC, the Sub-TCON IC of each box 01 controls the pixels in the box 01 to which it belongs to perform data writing and scanning, etc., to achieve debugging and normal display of the box 01. Because each box 01 is an independent driving environment, the entire display device has a large number of chips, high cost, and high power consumption.

In view of the above technical problems, an embodiment of the present invention provides a novel display device. FIG2 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Referring to FIG2 , the display device includes: at least two display areas 2, at least one shift circuit 1 and at least one data line Vdata, and the data line Vdata connects the at least two display areas 2;

The shift circuit 1 is used for shifting the data voltage on the data line Vdata in the previous display area 2 to the data line Vdata in the next display area 2 in response to the clock signal CLK.

Optionally, the display device includes a plurality of sub-pixels arranged in an array, and in different display areas 2, sub-pixels in the same column are connected to the same data line Vdata, and sub-pixels in different columns are connected to different data lines Vdata. Different display areas 2 are arranged along the direction in which the data line Vdata extends. The data lines Vdata of corresponding columns between adjacent display areas 2 are connected through a shift circuit 1. Specifically, the input end of the shift circuit 1 is electrically connected to the data line Vdata of the previous display area 2, and the output end of the shift circuit 1 is electrically connected to the data line Vdata of the next display area 2, wherein the data line Vdata of the next display area 2 connected to the output end of the shift circuit 1 can be the data line Vdata of the next display area 2 adjacent to the previous display area 2, or can be the data line Vdata of the next display area 2 not adjacent to the previous display area 2. In this embodiment, the output end of the shift circuit 1 is electrically connected to the data line Vdata of the next adjacent display area 2 as an example, and the shift circuit 1 is connected to two adjacent display areas 2 to simplify the wiring structure. In this embodiment, multiple shift circuits 1 and multiple data lines Vdata are exemplarily shown, and the data lines Vdata of corresponding columns between adjacent display areas 2 are connected through the shift circuits 1. Exemplarily, the display device includes n display areas, and n-1 rows of shift circuits 1 are required to shift the data voltage, where n≥2.

Exemplarily, the display device includes three display areas, and the first display area is used to be electrically connected to the driver chip to directly obtain the data voltage output by the driver chip. And for the convenience of description, the data voltages on different data lines Vdata in the same display area are the same as an example. In the first stage, the voltage on the data line Vdata in the first display area is the first data voltage, and the shift circuit 1 between the first display area and the second display area shifts the first data voltage to the second display area under the control of the clock signal CLK. In the second stage, the voltage on the data line Vdata of the first display area is updated to the second data voltage, and the shift circuit 1 between the first display area and the second display area shifts the second data voltage to the second display area under the control of the clock signal CLK. At the same time, the shift circuit 1 between the second display area and the third display area shifts the first data voltage to the third display area under the control of the clock signal CLK. In the third stage, the voltage on the data line Vdata of the first display area is updated to the third data voltage, while the shift circuit 1 between the first display area and the second display area and the shift circuit between the second display area and the third display area do not perform data shift under the control of the clock signal CLK. At this point, the voltage on the data line Vdata of the first display area is the third data voltage, the data voltage on the data line Vdata of the second display area is the second data voltage, and the voltage on the data line Vdata of the third display area is the first data voltage, so that the voltage on the data line Vdata is moved before scanning to move the corresponding data voltage to the corresponding display area 2.

The display device includes a plurality of sub-pixels arranged in an array. When the display device is used for display, the data voltages required for displaying the same column of sub-pixels in different display areas may be different. Through the shift circuits arranged between adjacent display areas, different data voltages are shifted to the corresponding display areas after multiple pulses of the clock signal. Among them, one display area can be regarded as a display panel, and multiple display panels are spliced to form a display device. After the data voltage shift of all display areas is completed, each display area starts scanning at the same time to write the data voltage. The display device provided in this embodiment first shifts the data voltage and then scans, so that the entire display device can realize the writing and scanning of the data voltage by a timing control chip and a driving chip. Compared with the existing splicing display device, the number of chips in the display device can be reduced, and the cost and power consumption can be reduced. At the same time, the data voltage is shifted first, so that each display area can be scanned line by line at the same time, reducing the scanning time of the entire device.

Continuing to refer to FIG. 2 , optionally, the display device further includes a plurality of scan lines S, and each display area 2 is used to respond to a scan signal on a corresponding scan line S and write the data voltage on the data line Vdata in the display area 2 row by row after the data voltage shift of all display areas 2 is completed.

Exemplarily, taking the display device including three display areas as an example, the data voltage required for the first display area to display is the third data voltage, the data voltage required for the second display area to display is the second data voltage, and the data voltage required for the third display area to display is the first data voltage. The data voltage shift of all display areas 2 is completed, and it can be that after multiple pulses of the clock signal CLK, the voltage on the data line Vdata of the first display area is the third data voltage, the voltage on the data line Vdata of the second display area is the second data voltage, and the voltage on the data line Vdata of the third display area is the first data voltage, that is, the data voltage in each display area is the required data voltage, which indicates that the data voltage shift of all display areas 2 is completed. After the data voltage shift is completed, the sub-pixels of the first row of the first display area, the sub-pixels of the first row of the second display area, and the sub-pixels of the first row of the third display area start scanning at the same time to write the data voltage of the corresponding display area 2, that is, each display area starts scanning line by line at the same time to write the data voltage. Each display area 2 starts scanning line by line at the same time, which can greatly shorten the scanning time and improve the scanning efficiency.

FIG3 is a schematic diagram of the structure of a shift circuit of a display device provided in an embodiment of the present invention. Referring to FIG3 , optionally, the shift circuit includes: a first node control unit 11, a cache unit 12, a second node control unit 13, a data transmission unit 14 and a voltage follower unit 15;

The first end of the first node control unit 11 is electrically connected to the data line of the corresponding column in the previous display area, the second end of the first node control unit 11 is electrically connected to the control end of the cache unit 12, the control end of the first node control unit 11 is connected to the clock signal CLK, the first end of the cache unit 12 is connected to the fixed potential signal VGL, the second end of the cache unit 12 is electrically connected to the first end of the second node control unit 13, the second end of the second node control unit 13 is electrically connected to the control end of the data transmission unit 14, the control end of the second node control unit 13 is connected to the clock signal CLK, the input end of the voltage follower unit 15 is electrically connected to the control end of the cache unit 12, the output end of the voltage follower unit 15 is electrically connected to the first end of the data transmission unit 14, and the second end of the data transmission unit 14 is connected to the data line of the corresponding column in the next display area.

The first node control unit 11 is used to respond to the clock signal CLK and transmit the data voltage on the connected data line to the control end of the buffer unit 12. The buffer unit 12 is used to store the data voltage and transmit the fixed potential signal VGL to the first end of the second node control unit 13 in response to the data voltage.

The second node control unit 13 is used to respond to the clock signal CLK and transmit the fixed potential signal VGL to the control end of the data transmission unit 14. The voltage follower unit 15 is used to transmit the data voltage to its own output end.

The data transmission unit 14 is used for transmitting the data voltage outputted from the output terminal of the voltage follower unit 15 to the data line in the next display area in response to the fixed potential signal VGL.

The first end of the first node control unit 11 is connected to the data line of the corresponding column of the previous display area, that is, the first end of the first node control unit 11 is used as the input end of the shift circuit, and the second end of the first node control unit 11 is electrically connected to the control end of the cache unit 12. The control end of the first node control unit 11 is connected to the clock signal CLK, and the first node control unit 11 is used to control the potential of the control end of the cache unit 12. The first node control unit 11 is equivalent to a switch unit, and after being turned on, it transmits the voltage on the data line of the corresponding column of the previous display area to the control end of the cache unit 12. The cache unit 12 is turned on under the control of the data voltage connected to its control end, and after being turned on, it transmits the fixed potential signal VGL to the first end of the second node control unit 13. The second node control unit 13 is used to control the potential of the control end of the data transmission unit 14. The second node control unit 13 is turned on or off under the control of the clock signal CLK, and after being turned on, it transmits the fixed potential signal VGL connected to its first end through the cache unit 12 to the control end of the data transmission unit 14. The output end of the data transmission unit 14 is used as the output end of the shift circuit and is electrically connected to the data line of the corresponding column of the next display area. The voltage follower unit 15 is used to transmit the voltage of its own input end to its own output end. The data transmission unit 14 is equivalent to a switch unit, which is turned on or off in response to the potential of its own control end, and when the potential of its own control end is the fixed potential signal VGL, it is turned on to connect its own input end and its own output end, that is, the data voltage on the data line of the corresponding column of the previous display area output by the voltage follower unit 15 is transmitted to its own output end. Among them, the fixed potential signal VGL is the effective potential signal of the data transmission unit 14, that is, when the potential of the control end of the data transmission unit 14 is the fixed potential signal VGL, the data transmission unit 14 is controlled to be turned on.

FIG3 exemplarily shows that the display device includes three display areas and two shift circuits, the two shift circuits are a first shift circuit 1-1 and a second shift circuit 1-2, the first shift circuit 1-1 is arranged between the first display area and the second display area, and the second shift circuit 1-2 is arranged between the second display area and the third display area. Among them, the input end of the first node control unit 11 of the first shift circuit 1-1 is connected to the data line Vi connected to the corresponding column of the first display area, and the output end of the data transmission unit 14 of the first shift circuit 1-1 is electrically connected to the data line Vo connected to the corresponding column of the second display area. The input end of the first node control unit 11 of the second shift circuit 1-2 is connected to the data line Vo connected to the corresponding column of the second display area, and the output end of the data transmission unit 14 of the second shift circuit 1-2 is electrically connected to the data line Vh connected to the corresponding column of the third display area.

Continuing to refer to Figure 3, optionally, the clock signal CLK includes an alternating first potential signal and a second potential signal, and the first potential signal and the second potential signal are high and low level signals to each other; the first node control unit 11 is used to respond to the first potential signal to turn on, or respond to the second potential signal to turn off, and when turned on, transmits the data voltage on the connected data line to the control end of the cache unit 12.

The second node control unit 13 is used to be turned on in response to the second potential signal, or turned off in response to the first potential signal, and transmits the fixed potential signal VGL connected to the cache unit 12 to the control end of the data transmission unit 14 when turned on.

Exemplarily, the first potential signal is a high level, and the second potential signal is a low level, or the first potential signal is a low level, and the second potential signal is a high level. After the first node control unit 11 is turned on, the data voltage on the data line connected to the corresponding column of the previous display area is cached to the cache unit 12. After the second node control unit 13 is turned on, the fixed potential signal VGL is transmitted to the control end of the data transmission unit 14, so that the data transmission unit 14 is turned on, and then the cached data voltage is transmitted to the data line connected to the corresponding column of the next display area. In the process of data voltage shifting, at a moment, one of the first node control unit 11 and the second node control unit 13 is turned on and the other is turned off, so that the cache and shift of the data voltage are completed at different moments, so as to avoid the voltage change on the data line of the previous display area, which affects the voltage shift on the data line of the previous display area at the previous moment, and ensures that the voltage on the data line of the previous display area at the previous moment is normally shifted to the next display area.

Figure 4 is a structural schematic diagram of another shift circuit of the display device provided in an embodiment of the present invention. Figure 4 may correspond to the specific structure of the shift circuit shown in Figure 3. Referring to Figures 3 and 4, optionally, the first node control unit 11 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to a data line connected to a corresponding column in a previous display area, a second electrode of the first transistor T1 is electrically connected to a control end of the cache unit 12, and a gate of the first transistor T1 is connected to a clock signal CLK.

Exemplarily, the first electrode of the first transistor T1 serves as the first end of the first node control unit 11, the second electrode of the first transistor T1 serves as the second end of the first node control unit 11, and the gate of the first transistor T1 serves as the control end of the first node control unit 11. The first transistor T1 may be an NMOS transistor or a PMOS transistor, which is not specifically limited in this embodiment. The first transistor T1 is turned on or off under the control of the clock signal CLK, and when turned on, transmits the data voltage on the data line connected to the corresponding column in the previous display area connected to its first electrode to the control end of the cache unit 12 and the input end of the voltage follower unit 15. The first node control unit 11 includes only one transistor, has a simple structure, and is easy to implement.

Continuing to refer to Figures 3 and 4, optionally, the cache unit 12 includes a second transistor T2 and a storage capacitor Cst, the first electrode of the second transistor T2 is connected to the fixed potential signal VGL, the second electrode of the second transistor T2 is electrically connected to the first end of the second node control unit 13, the gate of the second transistor T2 is electrically connected to the first end of the first node control unit 11 (may be electrically connected to the second electrode of the first transistor T1), the first end of the storage capacitor Cst is electrically connected to the gate of the second transistor T2, and the second end of the storage capacitor Cst is connected to the fixed potential signal VGL.

Exemplarily, the first electrode of the second transistor T2 serves as the first end of the cache unit 12, the second electrode of the second transistor T2 serves as the second end of the cache unit 12, and the gate of the second transistor T2 serves as the control end of the cache unit 12. The second transistor T2 can be an NMOS tube or a PMOS tube, which is not specifically limited in this embodiment. The first transistor T1 is turned on to write the data voltage into the gate of the second transistor T2. After the first transistor T1 is turned off, the storage capacitor Cst can store the potential of the gate of the second transistor T2, that is, the data voltage. The second transistor T2 is turned on under the control of the data voltage written to its own gate to transmit the fixed potential signal VGL to the first end of the second node control unit 13.

Continuing to refer to Figures 3 and 4, optionally, the second node control unit 13 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the second end of the cache unit 12 (may be electrically connected to the second electrode of the second transistor T2), a second electrode of the third transistor T3 is electrically connected to the control end of the data transmission unit 14, and a gate of the third transistor T3 is connected to the clock signal CLK.

Exemplarily, the first electrode of the third transistor T3 serves as the first end of the second node control unit 13, the second electrode of the third transistor T3 serves as the second end of the second node control unit 13, and the gate of the third transistor T3 serves as the control end of the second node control unit 13. The third transistor T3 may be an NMOS transistor or a PMOS transistor, which is not specifically limited in this embodiment. The third transistor T3 is turned on or off under the control of the clock signal CLK, and when turned on, transmits the fixed potential signal VGL connected through the cache unit 12 to the control end of the data transmission unit 14. The second node control unit 13 includes only one transistor, has a simple structure, and is easy to implement.

Continuing to refer to Figures 3 and 4, optionally, the voltage follower unit 15 includes an op amp follower Q1, a first input terminal of the op amp follower Q1 is electrically connected to the control terminal of the cache unit 12 (which can be the gate of the second transistor T2), a second input terminal of the op amp follower Q1 is electrically connected to its own output terminal, and an output terminal of the op amp follower Q1 is electrically connected to a first terminal of the data transmission unit 14.

Specifically, the first input end of the operational amplifier follower Q1 is electrically connected to the control end of the cache unit 12 as the input end of the voltage follower unit 15, and the output end of the operational amplifier follower Q1 is electrically connected to the first end of the data transmission unit 14 as the output end of the voltage follower unit 15. The voltage follower unit 15 includes only one operational amplifier follower Q1, which has a simple structure and is easy to implement.

Continuing to refer to Figures 3 and 4, optionally, the data transmission unit 14 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the output end of the voltage follower unit 15 (which may be the output end of the operational amplifier follower Q1), a second electrode of the fourth transistor T4 is electrically connected to a data line connected to a corresponding column of the next display area, and a gate of the fourth transistor T4 is electrically connected to the second end of the second node control unit 13 (which may be electrically connected to the second electrode of the third transistor T3).

Exemplarily, the first electrode of the fourth transistor T4 serves as the first end of the data transmission unit 14, the second electrode of the fourth transistor T4 serves as the second end of the data transmission unit 14, and the gate of the fourth transistor T4 serves as the control end of the data transmission unit 14. The fourth transistor T4 may be an NMOS transistor or a PMOS transistor, which is not specifically limited in this embodiment. The fourth transistor T4 is turned on in response to the fixed potential signal VGL connected via the cache unit 12 and the second node control unit 13, so as to transmit the data voltage output by the voltage follower unit 15 to its own second electrode, thereby shifting the data voltage. The data transmission unit 14 includes only one transistor, has a simple structure, and is easy to implement.

Continuing to refer to FIG. 4 , optionally, all shift circuits include first transistors T1 of the same type, second transistors T2 of the same type, third transistors T3 of the same type, and fourth transistors T4 of the same type.

The shift circuits included in the display device not only have the same structure, but also have the same types of corresponding transistors, which can reduce the process complexity of preparing all the shift circuits in the display device.

Continuing to refer to FIG. 4 , optionally, the first transistor T1 and the fourth transistor T4 are of the same type, the second transistor T2 and the third transistor T3 are of the same type, and the first transistor T1 and the third transistor T3 are of opposite types.

Exemplarily, the first transistor T1 and the fourth transistor T4 are PMOS transistors, the second transistor T2 and the third transistor T3 are NMOS transistors, or the first transistor T1 and the fourth transistor T4 are NMOS transistors, the second transistor T2 and the third transistor T3 are PMOS transistors.

5 is a driving timing diagram of a display device provided in an embodiment of the present invention, and exemplarily shows that in FIG. 4 , the first transistor T1 and the fourth transistor T4 are PMOS transistors, the second transistor T2 and the third transistor T3 are NMOS transistors, and referring to FIGS. 4 and 5 , optionally, the data shifting process of the display device includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5.

In the first stage t1, the voltage on the data line Vi of the first display area is the first data voltage Vdata0, and the clock signal CLK is at a low level. The low level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 to turn on. The turned-on first transistor T1 of the first shift circuit 1-1 caches the first data voltage Vdata0 to the gate of the second transistor T2 of the first shift circuit 1-1, and at the same time, the operational amplifier follower Q1 of the first shift circuit 1-1 transmits the first data voltage Vdata0 connected to the first input terminal to its own output terminal. The second transistor T2 of the first shift circuit 1-1 is turned on in response to the first data voltage Vdata0, and transmits the fixed potential signal VGL to the first electrode of the third transistor T3 of the first shift circuit 1-1. The third transistor T3 is turned off in response to the clock signal CLK, and the fourth transistor T4 is also turned off. Although the first transistor T1 in the second shift circuit 1-2 is also turned on, the first shift circuit 1-1 has not yet shifted the first data voltage Vdata0 to the second electrode of the fourth transistor T4 of the first shift circuit 1-1. Therefore, the second shift circuit 1-2 does not cache the data voltage. In the second stage t2, the voltage on the data line Vi of the first display area is still the first data voltage Vdata0, and the clock signal CLK is at a high level. The high level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the first transistor of the second shift circuit 1-2 to be turned off, and controls the third transistor T3 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 to be turned on. After the third transistor of the first shift circuit 1-1 is turned on, the fixed potential signal VGL is transmitted to the gate of the fourth transistor T4 of the first shift circuit 1-1 so that the fourth transistor T4 is turned on in response to the fixed potential signal VGL, and then the first data voltage Vdata0 outputted from the output end of the operational amplifier follower Q1 is transmitted to the second electrode of the fourth transistor T4 of the first shift circuit 1-1, that is, the first electrode of the first transistor T1 of the second shift circuit 1-2. Because the second shift circuit 1-2 does not cache the data voltage in the first stage t1, the second shift circuit 1-2 has no data voltage to shift in the second stage t2. After the first stage t1 and the second stage t2 , the first shift circuit 1 - 1 shifts the first data voltage Vdata0 to the second display area.

In the third stage t3, the voltage on the data line Vi of the first display area is refreshed to the second data voltage Vdata1, and the clock signal CLK is at a low level. The low level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 to turn on, and controls the third transistor T3 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 to turn off. After the first transistor T1 of the first shift circuit 1-1 is turned on, the second data voltage Vdata1 is cached to the gate of the second transistor T2. The second transistor T2 of the first shift circuit 1-1 is turned on in response to the second data voltage Vdata1 to transmit the fixed potential signal VGL to the first electrode of the third transistor T3 of the first shift circuit 1-1, and the operational amplifier follower Q1 transmits the second data voltage Vdata1 connected to the first input terminal to its own output terminal. After the first transistor T1 of the second shift circuit 1-2 is turned on, the first data voltage Vdata0 is cached to the gate of the second transistor T2 of the second shift circuit 1-2. The second transistor T2 of the second shift circuit 1-2 is turned on in response to the first data voltage Vdata0 to transmit the fixed potential signal VGL to the first electrode of the third transistor T3 of the second shift circuit 1-2, and the operational amplifier follower Q1 of the second shift circuit 1-2 transmits the first data voltage Vdata0 connected to its first input terminal to its own output terminal. In the fourth stage t4, the voltage on the data line of the first display area is still the second data voltage Vdata1, and the clock signal CLK is at a high level. The high level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 to be turned off, and controls the third transistor T3 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 to be turned on. After the third transistor T3 of the first shift circuit 1-1 is turned on, the fixed potential signal VGL is transmitted to the gate of the fourth transistor T4 of the first shift circuit 1-1 to turn on the fourth transistor T4. After the fourth transistor T4 of the first shift circuit 1-1 is turned on, the second data voltage Vdata1 output by the operational amplifier follower Q1 of the first shift circuit 1-1 is shifted to the input end of the second shift circuit 1-2, that is, shifted to the second display area. At the same time, after the third transistor T3 of the second shift circuit 1-2 is turned on, the fixed potential signal VGL is transmitted to the gate of the fourth transistor T4 of the second shift circuit 1-2 to turn on the fourth transistor T4. After the fourth transistor T4 of the second shift circuit 1-2 is turned on, the first data voltage Vdata0 output by the operational amplifier follower Q1 of the second shift circuit 1-2 is shifted to the third display area. After the third stage t3 and the fourth stage t4, the first shift circuit 1-1 shifts the second data voltage Vdata1 to the second display area, and the second shift circuit 1-2 shifts the first data voltage Vdata0 to the third display area.

In the fifth stage t5, the voltage of the data line Vi on the first display area is refreshed to the third data voltage Vdata2, and the clock signal CLK is at a low level. Although the first transistor T1 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 are turned on, the third transistor T3 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 are turned off. The first shift circuit 1-1 cannot shift the third data voltage Vdata2 to the second display area, that is, the second display area is still the second data voltage Vdata1, and the second shift circuit 1-2 cannot shift the second data voltage Vdata1 to the third display area, that is, the third display area is still the first data voltage Vdata0. After the fifth stage t5, the voltage in the first display area is updated to the third data voltage Vdata2.

After the first stage t1 to the fifth stage t5, the voltage on the data line Vi of the first display area is the third data voltage Vdata2, the voltage on the data line Vo of the second display area is the second data voltage Vdata1, and the voltage on the data line Vh of the third display area is the first data voltage Vdata0. At this point, the shifting process of the data voltages of each display area is completed.

FIG6 is a schematic diagram of the structure of another shift circuit of a display device provided in an embodiment of the present invention. Referring to FIG6 , optionally, the first transistor T1 and the second transistor T2 are of the same type, the third transistor T3 and the fourth transistor T4 are of the same type, and the first transistor T1 and the third transistor T3 are of opposite types.

Exemplarily, the first transistor T1 and the second transistor T2 are NMOS transistors, and the third transistor T3 and the fourth transistor T4 are PMOS transistors, or, the first transistor T1 and the second transistor T2 are PMOS transistors, and the third transistor T3 and the fourth transistor T4 are NMOS transistors. In this embodiment, it is exemplarily shown that the first transistor T1 and the second transistor T2 are NMOS transistors, the third transistor T3 and the fourth transistor T4 are PMOS transistors, and the shift process of the circuit shown in Figure 6 is similar to the shift process shown in Figure 4, which will not be repeated here.

FIG7 is a schematic diagram of the structure of another shift circuit of a display device provided by an embodiment of the present invention. Referring to FIG7, optionally, along the extension direction of the data line, the types of the first transistors T1 and the third transistors T3 of two adjacent shift circuits are opposite. It is also shown by way of example that the first transistor T1 and the fourth transistor T4 of the previous shift circuit (first shift circuit 1-1) in FIG7 are PMOS tubes, the second transistor T2 and the third transistor T3 are NMOS tubes, and the first transistor T1 and the second transistor T2 of the next adjacent shift circuit (second shift circuit 1-2) are NMOS tubes, and the third transistor T3 and the fourth transistor T4 are PMOS tubes. The driving timing of FIG7 can refer to FIG5.

In the first stage t1, the voltage on the data line Vi of the first display area is the first data voltage Vdata0, the clock signal CLK is at a low level, and the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 to turn on. After the first transistor T1 of the first shift circuit 1-1 is turned on, the first data voltage Vdata0 is cached to the gate of the second transistor T2 of the first shift circuit 1-1, and at the same time, the operational amplifier follower Q1 of the first shift circuit 1-1 transmits the first data voltage Vdata0 connected to its first input terminal to its own output terminal. The second transistor T2 of the first shift circuit 1-1 is turned on in response to the first data voltage Vdata0 to transmit the fixed potential signal VGL to the first electrode of the third transistor T3 of the first shift circuit 1-1, and the third transistor T3 of the first shift circuit 1-1 is turned off in response to the clock signal CLK, and the fourth transistor T4 is turned off. Although the third transistor T3 in the second shift circuit 1-2 is also turned on, the first shift circuit 1-1 has not yet shifted the first data voltage Vdata0 to the data line Vo of the second display area, so the second shift circuit 1-2 does not shift the data voltage. In the second stage t2, the data voltage on the first display area is still the first data voltage Vdata0, the clock signal CLK is at a high level, the first transistor T1 of the first shift circuit 1-1 is turned off in response to the high level of the clock signal CLK, and the third transistor T3 is turned on in response to the high level of the clock signal CLK, and the turned-on third transistor T3 of the first shift circuit 1-1 transmits the fixed potential signal VGL to the gate of the fourth transistor T4 of the first shift circuit 1-1, so that the fourth transistor T4 is turned on, and then the first data voltage Vdata0 outputted from the output end of the operational amplifier follower Q1 of the first shift circuit 1-1 is transmitted to the second electrode of the fourth transistor T4, that is, the first electrode of the first transistor T1 of the second shift circuit 1-2. After the first stage t1 and the second stage t2 , the first shift circuit 1 - 1 shifts the first data voltage Vdata0 to the second display area.

In the third stage t3, the voltage on the data line Vi of the first display area is refreshed to the second data voltage Vdata1, and the clock signal CLK is at a low level. The low level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the third transistor T1 of the second shift circuit 1-2 to turn on, and controls the third transistor T3 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 to turn off. After the first transistor T1 of the first shift circuit 1-1 is turned on, the second data voltage Vdata1 is cached to the gate of the second transistor T2 of the first shift circuit 1-1. The second transistor T2 of the first shift circuit 1-1 is turned on in response to the second data voltage Vdata1 to transmit the fixed potential signal VGL to the first electrode of the third transistor T3 of the first shift circuit 1-1, and the operational amplifier follower Q1 of the first shift circuit 1-1 transmits the second data voltage Vdata1 connected to the first input terminal to its own output terminal. Although the third transistor T1 of the second shift circuit 1-2 is also turned on, the fourth transistor T4 of the second shift circuit 1-2 is turned off because the first electrode of the third transistor T1 has not yet been connected to the fixed potential signal VGL. In the fourth stage t4, the voltage on the data line Vi of the first display area is still the second data voltage Vdata1, and the clock signal CLK is at a high level. The high level of the clock signal CLK controls the first transistor T1 of the first shift circuit 1-1 and the third transistor T3 of the second shift circuit 1-2 to be turned off, and controls the third transistor T3 of the first shift circuit 1-1 and the first transistor T1 of the second shift circuit 1-2 to be turned on. After the third transistor T3 of the first shift circuit 1-1 is turned on, the fixed potential signal VGL is transmitted to the gate of the fourth transistor T4 of the first shift circuit 1-1 to turn on the fourth transistor T4. After the fourth transistor T4 of the first shift circuit 1-1 is turned on, the second data voltage Vdata1 output by the operational amplifier follower Q1 of the first shift circuit 1-1 is shifted to the input end of the second shift circuit 1-2, that is, shifted to the second display area. At the same time, after the first transistor T1 of the second shift circuit 1-2 is turned on, the first data voltage Vdata0 is transmitted to the gate of the second transistor T2 of the second shift circuit 1-2 to turn on the second transistor T2. After the second transistor T2 of the second shift circuit 1-2 is turned on, the fixed potential signal VGL is transmitted to the first electrode of the third transistor T3 of the second shift circuit 1-2.

In the fifth stage t5, the voltage on the data line Vi of the first display area begins to be refreshed to the third data voltage Vtata2. At this point, the shift process is completed. In the fifth stage t5, whether the clock signal CLK is high or low does not affect the data voltages of other display areas. Taking the fifth stage t5, when the clock signal CLK is low as an example, the voltage on the data line Vi of the first display area is refreshed to the third data voltage Vdata2. The clock signal CLK is low, which controls the first transistor T1 of the first shift circuit 1-1 and the third transistor T1 of the second shift circuit 1-2 to be turned on. After the first transistor T1 of the first shift circuit 1-1 is turned on, the data voltage is cached to the gate of the second transistor T2. The second transistor T2 of the first shift circuit 1-1 is turned on in response to the third data voltage Vdata2 to transmit the fixed potential signal VGL to the first electrode of the third transistor T3 of the first shift circuit 1-1. After the third transistor T3 of the second shift circuit 1-2 is turned on, the fixed potential signal VGL is transmitted to the fourth transistor T4 of the second shift circuit 1-2 to turn on the fourth transistor T4. After the fourth transistor T4 is turned on, the first data voltage Vdata0 output by the operational amplifier follower Q1 of the second shift circuit 1-2 is transmitted to the data line Vh of the third display area.

It can be seen from the above process that in the first stage t1 and the second stage t2, the first shift circuit 1-1 shifts the first data voltage Vdata0 to the second display area. In the third stage t3, the fourth stage t4 and the fifth stage t5, the second shift circuit 1-2 shifts the first data voltage Vdata0 to the third display area. In the third stage t3 and the fourth stage t4, the first shift circuit 1-1 shifts the second data voltage Vdata1 to the second display area. In the fifth stage t5, the voltage on the data line of the first display area is refreshed to the third data voltage Vdata2. So far, after the first stage t1 to the fifth stage t5, the voltage on the data line Vi of the first display area is the third data voltage Vdata2, the voltage on the data line Vo of the second display area is the second data voltage Vdata1, and the voltage on the data line Vh of the third display area is the first data voltage Vdata0, and the shift process of the data voltages of each display area is completed.

The setting of the shift circuit shown in Figure 7 can enable the previous shift circuit to shift the data voltage connected to the previous shift circuit at the current moment to the adjacent next display area when the clock signal is at a high level, while the next shift circuit caches the data voltage transmitted by the previous shift circuit at the previous moment into the next shift circuit, so that at the next low level, the next shift circuit completes the shifting of the data voltage.

Optionally, the display device includes a plurality of spliced display panels, and at least two display areas belong to different display panels.

Different display panels are spliced into a display device, and before the scanning process is performed, the data voltage is moved to the corresponding display area through the shift circuit between adjacent display areas, and then each display area starts the scanning process at the same time. Compared with the conventional display device spliced by multiple display panels, which requires a timing control chip and multiple sub-timing control chips, this embodiment only requires one timing control chip to realize the data shifting and scanning process, reducing the cost of the device, simplifying the structure of the display device, compressing the volume of the display panel, and reducing the power consumption of the display device.

An embodiment of the present invention further provides a method for driving a display device, which is used to drive the above-mentioned display device. The driving method includes:

The shift circuit shifts the data voltage on the data line in the previous display area to the data line in the next display area in response to the clock signal.

Specifically, after the shift circuit receives the set number of pulses of the clock signal, it can transfer the data voltage on the data line in the previous display area to which it is connected to the data line in the next display area to achieve the shift of the data voltage.

The beneficial effects of the driving method of the display device are the same as those of the display device, and will not be described in detail in this embodiment.

FIG8 is a flow chart of a method for driving a display device provided by an embodiment of the present invention. Referring to FIG4 and FIG8 , or FIG6 and FIG8 , optionally, the clock signal CLK includes an alternating first potential signal and a second potential signal, the first potential signal and the second potential signal are high and low level signals to each other, and the method for driving the display device includes:

S110: A shift circuit connected between the Kth display area and the K-1th display area is used to respond to the first potential signal and cache the data voltage on the data line in the K-1th display area into the shift circuit.

Exemplarily, the first potential signal is a low level, and the second potential signal is a high level. Referring to FIG4 and FIG8, K=2, the shift circuit connected between the second display area and the first display area is the first shift circuit 1-1, and the first shift circuit 1-1 caches the data voltage on the data line in the first display area into the first shift circuit 1-1 (the gate of the second transistor T2) in response to the first potential signal. K=3, the shift circuit connected between the third display area and the second display area is the second shift circuit 1-2, and the second shift circuit 1-2 caches the data voltage on the data line in the second display area into the second shift circuit 1-2 (the gate of the second transistor T2) in response to the first potential signal.

S120: The shift circuit connected between the Kth display area and the K-1th display area is further used to respond to the second potential signal and transmit the buffered data voltage to the data line in the Kth display area, wherein K≥2.

K=2, the first shift circuit 1-1 shifts the data voltage buffered in the first display area to the data line in the second display area in response to the second potential signal. K=3, the second shift circuit 1-2 shifts the data voltage buffered in the second display area to the third display area in response to the second potential signal.

In this embodiment, the specific structures of the shift circuits are the same, and the shift circuits cache the data voltage in response to the first potential signal and shift the voltage in response to the second potential signal. The same structure of the shift circuits can simplify the control logic and reduce the process complexity of preparing all the shift circuits in the device.

FIG9 is a flow chart of another method for driving a display device provided by an embodiment of the present invention. Referring to FIG7 and FIG9 , optionally, the clock signal CLK includes an alternating first potential signal and a second potential signal, and the first potential signal and the second potential signal are high-low level signals to each other. The method for driving the display device includes:

S111: The shift circuit connected between the Kth display area and the K-1th display area is used to respond to the first potential signal and cache the data voltage on the data line in the K-1th display area into the shift circuit, and the shift circuit connected between the Kth display area and the K+1th display area is used to respond to the first potential signal and transmit the data voltage cached by the shift circuit to the data line in the K+1th display area.

Specifically, the shift circuit connected between the Kth display area and the K-1th display area is a first shift circuit, and the first shift circuit is used to respond to the first potential signal and cache the data voltage on the data line in the K-1th display area in the current stage into the first shift circuit. The shift circuit connected between the Kth display area and the K+1th display area is a second shift circuit, and the second shift circuit is used to respond to the first potential signal and transmit the data voltage of the Kth display area in the first two stages cached by the second shift circuit to the K+1th display area.

S121: The shift circuit connected between the Kth display area and the K-1th display area is also used to respond to the second potential signal to transmit the data voltage cached by the shift circuit to the data line in the Kth display area, and the shift circuit connected between the Kth display area and the K+1th display area is also used to respond to the second potential signal to cache the data voltage on the data line in the Kth display area into the shift circuit; wherein, K≥2.

Specifically, the first shift circuit is used to respond to the second potential signal and shift the data voltage cached under the adjacent previous first potential signal to the Kth display area. The second shift circuit is used to respond to the second potential signal and cache the voltage on the data line of the Kth display area in the previous stage into the second shift circuit.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A display device, comprising: the display device comprises at least two display areas, at least one shift circuit and at least one data line, wherein the data line is connected with the at least two display areas;

the data lines of the corresponding columns between the adjacent display areas are connected through the shift circuit, and the shift circuit is used for shifting and transmitting the data voltage on the data line in the former display area to the data line in the latter display area in response to a clock signal.

2. The display device according to claim 1, wherein the shift circuit includes: the device comprises a first node control unit, a buffer unit, a second node control unit, a data transmission unit and a voltage following unit;

The first end of the first node control unit is electrically connected with the data line of the corresponding column in the previous display area, the second end of the first node control unit is electrically connected with the control end of the buffer unit, the control end of the first node control unit is connected with the clock signal, the first end of the buffer unit is connected with the fixed potential signal, the second end of the buffer unit is electrically connected with the first end of the second node control unit, the second end of the second node control unit is electrically connected with the control end of the data transmission unit, the control end of the second node control unit is connected with the clock signal, the input end of the voltage following unit is electrically connected with the control end of the buffer unit, the output end of the voltage following unit is electrically connected with the first end of the data transmission unit, and the second end of the data transmission unit is connected with the data line of the corresponding column in the next display area.

3. The display device according to claim 2, wherein the first node control unit is configured to transmit the data voltage on the accessed data line to the control terminal of the buffer unit in response to the clock signal;

And/or the buffer unit is used for storing the data voltage and transmitting a fixed potential signal to the first end of the second node control unit in response to the data voltage;

And/or the second node control unit is used for responding to the clock signal and transmitting the fixed potential signal to the control end of the data transmission unit;

And/or the voltage following unit is used for transmitting the data voltage to an output end of the voltage following unit;

And/or the data transmission unit is used for responding to the fixed potential signal and transmitting the data voltage output by the output end of the voltage following unit to a data line in the next display area;

Preferably, the first node control unit includes a first transistor, a first pole of the first transistor is electrically connected to the data line connected to a corresponding column in the previous display area, a second pole of the first transistor is electrically connected to a control terminal of the buffer unit, and a gate of the first transistor is connected to the clock signal;

Preferably, the buffer unit includes a second transistor and a storage capacitor, a first electrode of the second transistor is connected to the fixed potential signal, a second electrode of the second transistor is electrically connected to a first end of the second node control unit, a gate of the second transistor is electrically connected to a second end of the first node control unit, a first end of the storage capacitor is electrically connected to a gate of the second transistor, and a second end of the storage capacitor is connected to the fixed potential signal;

Preferably, the second node control unit includes a third transistor, a first pole of the third transistor is electrically connected to the second end of the buffer unit, a second pole of the third transistor is electrically connected to the control end of the data transmission unit, and a gate of the third transistor is connected to the clock signal;

Preferably, the voltage following unit comprises an operational amplifier follower, a first input end of the operational amplifier follower is electrically connected with a control end of the buffer unit, a second input end of the operational amplifier follower is electrically connected with an output end of the operational amplifier follower, and an output end of the operational amplifier follower is electrically connected with a first end of the data transmission unit;

preferably, the data transmission unit includes a fourth transistor, a first pole of the fourth transistor is electrically connected to the output terminal of the voltage follower unit, a second pole of the fourth transistor is electrically connected to a data line connected to a corresponding column of the next display area, and a gate of the fourth transistor is electrically connected to the second terminal of the second node control unit.

4. A display device according to claim 3, wherein the clock signal comprises alternating first and second potential signals, the first and second potential signals being high and low level signals with respect to each other; the first node control unit is used for responding to the first potential signal to be conducted or responding to the second potential signal to be turned off, and transmitting the data voltage on the accessed data line to the control end of the cache unit when the first node control unit is conducted;

The second node control unit is used for responding to the second potential signal to be conducted or responding to the first potential signal to be turned off, and transmitting the fixed potential signal accessed by the buffer unit to the control end of the data transmission unit when the second node control unit is conducted;

Preferably, along the extending direction of the data line, the types of the first transistors and the types of the third transistors of the adjacent two shift circuits are opposite.

5. The display device according to claim 4, wherein all of the shift circuits include a same type of first transistor, a same type of second transistor, a same type of third transistor, and a same type of fourth transistor;

preferably, the first transistor and the fourth transistor are the same in type, the second transistor and the third transistor are the same in type, and the first transistor and the third transistor are opposite in type;

Or the first transistor and the second transistor are the same in type, the third transistor and the fourth transistor are the same in type, and the first transistor and the third transistor are opposite in type.

6. The display device of claim 1, further comprising a plurality of scan lines, each of the display areas for writing data voltages on data lines in the display area row by row in response to a scan signal on the corresponding scan line after data voltage shifting of all the display areas is completed.

7. The display device according to claim 1, comprising a plurality of spliced display panels, at least two of the display areas respectively belonging to different ones of the display panels.

8. A driving method of a display device, characterized by being used for driving the display device according to any one of claims 1 to 7, the driving method comprising:

The shift circuit shifts and transmits the data voltage on the data line in the former display area to the data line in the latter display area in response to a clock signal.

9. The driving method of a display device according to claim 8, wherein the clock signal includes alternating first and second potential signals, the first and second potential signals being high and low level signals with each other, the shift circuit shifting and transmitting data voltages on data lines in a preceding one of the display areas to data lines in a succeeding one of the display areas in response to the clock signal, comprising:

The shift circuit connected between the Kth display area and the Kth-1 display area is used for responding to the first potential signal, buffering the data voltage on the data line in the Kth-1 display area into the shift circuit and transmitting the buffered data voltage to the data line in the Kth display area in response to the second potential signal; wherein K is more than or equal to 2.

10. The driving method of a display device according to claim 8, wherein the clock signal includes alternating first and second potential signals, the first and second potential signals being high and low level signals with each other, the shift circuit shifting and transmitting data voltages on data lines in a preceding one of the display areas to data lines in a succeeding one of the display areas in response to the clock signal, comprising:

The shift circuit is connected between the Kth display area and the Kth-1 display area and used for responding to the first potential signal, buffering the data voltage on the data line in the Kth-1 display area into the shift circuit, and the shift circuit is connected between the Kth display area and the Kth-1 display area and used for responding to the first potential signal, and transmitting the data voltage buffered by the shift circuit to the data line in the Kth-1 display area;

The shift circuit connected between the Kth display area and the Kth-1 display area is further used for responding to the second potential signal, transmitting the data voltage buffered by the shift circuit to the data line in the Kth display area, and buffering the data voltage on the data line in the Kth display area into the shift circuit; wherein K is more than or equal to 2.