CN118713475A - A BURST control circuit based on forced continuous mode DC-DC - Google Patents
A BURST control circuit based on forced continuous mode DC-DC Download PDFInfo
- Publication number
- CN118713475A CN118713475A CN202410995594.8A CN202410995594A CN118713475A CN 118713475 A CN118713475 A CN 118713475A CN 202410995594 A CN202410995594 A CN 202410995594A CN 118713475 A CN118713475 A CN 118713475A
- Authority
- CN
- China
- Prior art keywords
- transistor
- burst
- gate
- output
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims abstract description 41
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 claims abstract description 17
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 31
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 claims description 12
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 claims description 12
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 claims description 12
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 claims description 12
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 claims description 12
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 claims description 12
- KIWSYRHAAPLJFJ-DNZSEPECSA-N n-[(e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enyl]pyridine-3-carboxamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/CNC(=O)C1=CC=CN=C1 KIWSYRHAAPLJFJ-DNZSEPECSA-N 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 9
- 229920001621 AMOLED Polymers 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 2
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
本发明公开了一种基于强制连续模式DC‑DC的BURST控制电路，包含DC‑DC变换器、误差放大器EA、电流采样电路CURRENT SENSE、PWM比较器CMP1、调制器PWM MODULE、BURST比较器CMP2和BURST_VREF产生器BURST_VREF_GEN。本发明在FCCM前提下加入BURST模式，当轻负载时DC‑DC可以跳周期工作，有效减少开关次数，跳周频率与带载电流成正比，并且可以规避每个开关周期都出现反流的情况，从而大幅度提高轻负载效率。
The present invention discloses a BURST control circuit based on a forced continuous mode DC-DC, comprising a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN. The present invention adds a BURST mode under the premise of FCCM. When the load is light, the DC-DC can skip cycles to effectively reduce the number of switches. The skip cycle frequency is proportional to the load current, and the reverse current in each switching cycle can be avoided, thereby greatly improving the light load efficiency.
Description
技术领域Technical Field
本发明涉及一种BURST控制电路，特别是一种基于强制连续模式DC-DC的BURST控制电路，属于半导体集成电路技术领域。The invention relates to a BURST control circuit, in particular to a BURST control circuit based on a forced continuous mode DC-DC, belonging to the technical field of semiconductor integrated circuits.
背景技术Background Art
随着电子产品应用愈发广泛，使用场景愈发复杂，对开关电源芯片的要求增多；尤其是手机芯片，需要在尽可能小的尺寸内实现多种功能指标。AMOLED屏幕驱动芯片，为了规避屏幕的“水波纹”，输出电压纹波要尽可能小，并且开关频率不能与屏幕刷新频率重叠。因此，DC-DC的调制模式被限制为定频PWM控制。并且由于宽输入范围，正压输出Boost存在100%占空比，无法使用过零检测模块（Zero Current Detection，ZCD），轻负载时只能是强制连续导通模式（FCCM），图1所示就是典型FCCM的谷值电流PWM控制环路，目前主流手机芯片供应商都是采用该架构。因此，正压输出Boost的每个时钟周期内都有开关动作，并且出现反流，如图7所示。为了满足高亮度显示，芯片需要输出大功率电流，DC-DC功率管尺寸不能选取太小。因此，受限于功率管的Cgs、Cgd等寄生电容，每个开关周期内的开关损耗较大。综上，采用FCCM控制的芯片始终无法获得极轻载下的高效率，进而导致AMOLED无法实现超低功耗熄屏显示时间等功能。As electronic products are increasingly used and their usage scenarios become more complex, the requirements for switching power supply chips are increasing; especially mobile phone chips, which need to achieve multiple functional indicators in the smallest possible size. For AMOLED screen driver chips, in order to avoid the "water ripple" of the screen, the output voltage ripple should be as small as possible, and the switching frequency cannot overlap with the screen refresh frequency. Therefore, the modulation mode of DC-DC is limited to fixed-frequency PWM control. And due to the wide input range, the positive voltage output Boost has a 100% duty cycle, and the zero current detection module (ZCD) cannot be used. When the load is light, it can only be forced continuous conduction mode (FCCM). Figure 1 shows the valley current PWM control loop of a typical FCCM. Currently, mainstream mobile phone chip suppliers all use this architecture. Therefore, there is a switching action in each clock cycle of the positive voltage output Boost, and reverse flow occurs, as shown in Figure 7. In order to meet the high-brightness display, the chip needs to output a high-power current, and the size of the DC-DC power tube cannot be selected too small. Therefore, limited by the parasitic capacitance of the power tube such as Cgs and Cgd, the switching loss in each switching cycle is large. In summary, chips using FCCM control are unable to achieve high efficiency under extremely light loads, which in turn causes AMOLED to be unable to achieve functions such as ultra-low power consumption and screen-off display time.
文献1【V. Kadlimatti, P. Thota and S. Bhat, "A Novel Methodology ofPWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter forAMOLED Display Applications," 2020 33rd International Conference on VLSIDesign and 2020 19th International Conference on Embedded Systems (VLSID),Bangalore, India, 2020, pp. 165-170, doi: 10.1109/VLSID49098.2020.00046】使用PWM-DCM/PFM模式切换来提高效率，但牺牲了宽输入范围的应用，并且PFM开关周期与负载呈反比，存在与屏幕刷新频率重叠的风险，且输出纹波变大。Reference 1 [V. Kadlimatti, P. Thota and S. Bhat, "A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display Applications," 2020 33rd International Conference on VLSIDesign and 2020 19th International Conference on Embedded Systems (VLSID), Bangalore, India, 2020, pp. 165-170, doi: 10.1109/VLSID49098.2020.00046] uses PWM-DCM/PFM mode switching to improve efficiency, but sacrifices the application of a wide input range, and the PFM switching period is inversely proportional to the load, there is a risk of overlapping with the screen refresh frequency, and the output ripple becomes larger.
文献2【S. -W. Hong, S. -H. Park, T. -H. Kong and G. -H. Cho, "Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction Mode," in IEEE Journal of Solid-StateCircuits, vol. 50, no. 10, pp. 2380-2393, Oct. 2015, doi: 10.1109/JSSC.2015.2450713】优化了DC-DC驱动电路功耗来提高全负载效率，但效果有限，无法从根本上解决极轻载下的开关损耗问题。Reference 2 [S. -W. Hong, S. -H. Park, T. -H. Kong and G. -H. Cho, "Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction Mode," in IEEE Journal of Solid-StateCircuits, vol. 50, no. 10, pp. 2380-2393, Oct. 2015, doi: 10.1109/JSSC.2015.2450713] optimized the power consumption of the DC-DC drive circuit to improve the full-load efficiency, but the effect was limited and it could not fundamentally solve the switching loss problem under extremely light loads.
综上所述，由于AMOLED屏幕驱动芯片有诸多应用需求，其正压输出Boost没有过零检测模式（ZCD），芯片无法进入DCM模式，当芯片轻负载工作时，Boost电感电流存在反流现象，并且每个时钟周期都会有开关动作。这会极大地降低AMOLED屏幕驱动芯片的轻负载效率。并且由于手机芯片纹波限制，芯片也无法采用常见的COT PFM调制。In summary, due to the many application requirements of AMOLED screen driver chips, its positive voltage output Boost does not have a zero-crossing detection mode (ZCD), and the chip cannot enter the DCM mode. When the chip is working under light load, the Boost inductor current has a reverse flow phenomenon, and there will be a switching action in each clock cycle. This will greatly reduce the light load efficiency of the AMOLED screen driver chip. And due to the ripple limit of the mobile phone chip, the chip cannot use the common COT PFM modulation.
发明内容Summary of the invention
本发明所要解决的技术问题是提供一种基于强制连续模式DC-DC的BURST控制电路，提高轻负载效率并避免不同占空比下由于斜坡补偿电流导致BURST模式的电流单位偏差太大的问题。The technical problem to be solved by the present invention is to provide a BURST control circuit based on forced continuous mode DC-DC, which improves light load efficiency and avoids the problem of too large current unit deviation in BURST mode due to slope compensation current under different duty cycles.
为解决上述技术问题，本发明所采用的技术方案是：In order to solve the above technical problems, the technical solution adopted by the present invention is:
一种基于强制连续模式DC-DC的BURST控制电路，包含DC-DC变换器、误差放大器EA、电流采样电路CURRENT SENSE、PWM比较器CMP1、调制器PWM MODULE、BURST比较器CMP2和BURST_VREF产生器BURST_VREF_GEN，误差放大器EA的反向输入端连接DC-DC变换器分压反馈电路的输出信号FB，误差放大器EA的同向输入端连接基准电压信号VREF，误差放大器EA的输出端与PWM比较器CMP1的同向输入端和BURST比较器CMP2的反向输入端连接，电流采样电路CURRENT SENSE的输入端连接DC-DC变换器中功率管M2的源极，电流采样电路CURRENTSENSE的输出端输出电压信号CS，电压信号CS加上斜坡补偿电压SLOPE后与PWM比较器CMP1的反向输入端连接，PWM比较器CMP1的输出端与调制器PWM MODULE的第一输入端连接，BURST_VREF产生器BURST_VREF_GEN的输出端与BURST比较器CMP2的同向输入端连接，BURST比较器CMP2的输出端与调制器PWM MODULE的第三输入端连接，调制器PWM MODULE的第二输入端连接时钟信号CLK。A BURST control circuit based on a forced continuous mode DC-DC comprises a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN, wherein the inverse input terminal of the error amplifier EA is connected to the output signal FB of the voltage-dividing feedback circuit of the DC-DC converter, the same-direction input terminal of the error amplifier EA is connected to the reference voltage signal VREF, the output terminal of the error amplifier EA is connected to the same-direction input terminal of the PWM comparator CMP1 and the inverse input terminal of the BURST comparator CMP2, the input terminal of the current sampling circuit CURRENT SENSE is connected to the source of a power tube M2 in the DC-DC converter, the output terminal of the current sampling circuit CURRENT SENSE outputs a voltage signal CS, the voltage signal CS is added with a slope compensation voltage SLOPE and connected to the inverse input terminal of the PWM comparator CMP1, the output terminal of the PWM comparator CMP1 is connected to the modulator PWM The output end of the BURST comparator CMP2 is connected to the third input end of the modulator PWM MODULE, and the second input end of the modulator PWM MODULE is connected to the clock signal CLK.
进一步地，所述DC-DC变换器包含电源V0、电感L、功率管M11、功率管M12、电容C和分压反馈电路，电源V0的正极与电感L的一端连接，电感L的另一端与功率管M11的漏极和功率管M12的漏极连接于开关节点SW，功率管M11的栅极和功率管M12的栅极与调制器PWMMODULE的输出端连接，功率管M12的源极与电流采样电路CURRENT SENSE的输入端、电容C的一端和分压反馈电路的一端连接，电源V0的负极、功率管M11的源极、电容C的另一端和分压反馈电路的另一端接地。Further, the DC-DC converter includes a power supply V0, an inductor L, a power tube M11, a power tube M12, a capacitor C and a voltage divider feedback circuit, the positive electrode of the power supply V0 is connected to one end of the inductor L, the other end of the inductor L and the drain of the power tube M11 and the drain of the power tube M12 are connected to the switch node SW, the gate of the power tube M11 and the gate of the power tube M12 are connected to the output end of the modulator PWMMODULE, the source of the power tube M12 is connected to the input end of the current sampling circuit CURRENT SENSE, one end of the capacitor C and one end of the voltage divider feedback circuit, and the negative electrode of the power supply V0, the source of the power tube M11, the other end of the capacitor C and the other end of the voltage divider feedback circuit are grounded.
进一步地，所述分压反馈电路包含电阻R11和电阻R12，电阻R11的一端与功率管M12的源极、电流采样电路CURRENT SENSE的输入端和电容C的一端连接于输出节点OUT，电阻R11的另一端与电阻R12的一端连接并产生输出信号FB，电阻R12的另一端接地。Furthermore, the voltage divider feedback circuit includes a resistor R11 and a resistor R12, one end of the resistor R11 is connected to the source of the power tube M12, the input end of the current sampling circuit CURRENT SENSE and one end of the capacitor C at the output node OUT, the other end of the resistor R11 is connected to one end of the resistor R12 and generates an output signal FB, and the other end of the resistor R12 is grounded.
进一步地，所述误差放大器EA的输出端产生输出信号EAO，BURST_VREF产生器BURST_VREF_GEN的输出端产生输出电压BURST_VREF，BURST比较器CMP2的输出端产生输出电压IN_BURST。Furthermore, the output terminal of the error amplifier EA generates an output signal EAO, the output terminal of the BURST_VREF generator BURST_VREF_GEN generates an output voltage BURST_VREF, and the output terminal of the BURST comparator CMP2 generates an output voltage IN_BURST.
进一步地，所述BURST_VREF产生器包含采样保持模块SENSE_HOLD、匹配电阻R2和偏置电流源IB2，采样保持模块SENSE_HOLD输入端输入斜坡补偿电流ISLOPE，采样保持模块SENSE_HOLD采样并保持前一周期的斜坡补偿最大电流值ISLOPE_MAX，采样保持模块SENSE_HOLD的输出端与匹配电阻R2的一端和偏置电流源IB2的输出端连接并作为BURST_VREF产生器的输出端，匹配电阻R2的另一端接地。Further, the BURST_VREF generator includes a sampling and holding module SENSE_HOLD, a matching resistor R2 and a bias current source I B2 , the input end of the sampling and holding module SENSE_HOLD inputs the slope compensation current I SLOPE , the sampling and holding module SENSE_HOLD samples and holds the maximum current value I SLOPE_MAX of the slope compensation in the previous cycle, the output end of the sampling and holding module SENSE_HOLD is connected to one end of the matching resistor R2 and the output end of the bias current source I B2 and serves as the output end of the BURST_VREF generator, and the other end of the matching resistor R2 is grounded.
进一步地，所述采样保持模块SENSE_HOLD输入端与电阻R1的一端、电流采样电路CURRENT SENSE的主体电路CURRENT MIRROR的输出端、偏置电流源IB1的输出端连接。Furthermore, the input end of the sampling and holding module SENSE_HOLD is connected to one end of the resistor R1, the output end of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE, and the output end of the bias current source I B1 .
进一步地，所述匹配电阻R2和电阻R1的阻值相等，偏置电流源IB2和偏置电流源IB1的电流相等。Furthermore, the matching resistor R2 and the resistor R1 have the same resistance value, and the bias current source I B2 and the bias current source I B1 have the same current value.
进一步地，所述采样保持模块SENSE_HOLD包含晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、晶体管M7、电阻R3、电阻R4、运算放大器OP1、运算放大器OP2、运算放大器OP3、开关S1、开关S2、保持电容CHOLD1和CHOLD2，晶体管M1的漏极与晶体管M1的栅极、晶体管M2的栅极和晶体管M3的栅极连接并输入斜坡补偿电流的源头SLOPE CURRENTSOURCE，晶体管M2的漏极与晶体管M4的漏极、晶体管M4的栅极和晶体管M5的栅极连接，晶体管M3的漏极输出斜坡补偿电流SLOPE CURRENT，晶体管M4的源极与晶体管M5的源极、晶体管M6的源极和晶体管M7的源极连接，晶体管M5的漏极与电阻R3的一端和运算放大器OP1的同向输入端连接，运算放大器OP1的输出端与运算放大器OP1的反向输入端和开关S1的一端连接，开关S1的另一端与运算放大器OP2的同向输入端和保持电容CHOLD1的一端连接，运算放大器OP2的输出端与运算放大器OP2的反向输入端和开关S2的一端连接，开关S2的另一端与运算放大器OP3的同向输入端和保持电容CHOLD2的一端连接，运算放大器OP3的输出端与运算放大器OP3的反向输入端、电阻R4的一端、晶体管M6的漏极、晶体管M6的栅极和晶体管M7的栅极连接，晶体管M7的漏极输出斜坡补偿电流的最大值SLOPE CURRENT MAX，晶体管M1的源极、晶体管M2的源极、晶体管M3的源极、电阻R3的另一端、保持电容CHOLD1的另一端、保持电容CHOLD2的另一端和电阻R4的另一端接地。Further, the sampling and holding module SENSE_HOLD includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a resistor R3, a resistor R4, an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP3, a switch S1, a switch S2, and holding capacitors C HOLD1 and C HOLD2 . The drain of the transistor M1 is connected to the gate of the transistor M1, the gate of the transistor M2, and the gate of the transistor M3 and inputs the source SLOPE CURRENT SOURCE of the slope compensation current. The drain of the transistor M2 is connected to the drain of the transistor M4, the gate of the transistor M4, and the gate of the transistor M5. The drain of the transistor M3 outputs the slope compensation current SLOPE CURRENT, the source of the transistor M4 is connected to the source of the transistor M5, the source of the transistor M6 and the source of the transistor M7, the drain of the transistor M5 is connected to one end of the resistor R3 and the non-inverting input of the operational amplifier OP1, the output of the operational amplifier OP1 is connected to the inverting input of the operational amplifier OP1 and one end of the switch S1, the other end of the switch S1 is connected to the non-inverting input of the operational amplifier OP2 and one end of the holding capacitor C HOLD1 , the output of the operational amplifier OP2 is connected to the inverting input of the operational amplifier OP2 and one end of the switch S2, the other end of the switch S2 is connected to the non-inverting input of the operational amplifier OP3 and one end of the holding capacitor C HOLD2 , the output of the operational amplifier OP3 is connected to the inverting input of the operational amplifier OP3, one end of the resistor R4, the drain of the transistor M6, the gate of the transistor M6 and the gate of the transistor M7, and the drain of the transistor M7 outputs the maximum value of the slope compensation current SLOPE CURRENT MAX, the source of the transistor M1, the source of the transistor M2, the source of the transistor M3, the other end of the resistor R3, the other end of the holding capacitor C HOLD1 , the other end of the holding capacitor C HOLD2 and the other end of the resistor R4 are grounded.
进一步地，所述调制器PWM MODULE包含或非门NOR1、或非门NOR2、或非门NOR3和或非门NOR4，或非门NOR1的第一输入端与比较器CMP1的输出端连接，或非门NOR1的第二输入端与或非门NOR2的输出端连接，或非门NOR1的输出端与或非门NOR2的第一输入端和或非门NOR3的第一输入端连接，或非门NOR2的第二输入端连接时钟信号CLK，或非门NOR3的第二输入端和或非门NOR4的第二输入端连接输出电压IN_BURST，或非门NOR3的输出端与或非门NOR4的第一输入端连接并产生信号M2_ON，或非门NOR4的输出端产生信号M1_ON。Further, the modulator PWM MODULE includes a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4, a first input end of the NOR gate NOR1 is connected to the output end of the comparator CMP1, a second input end of the NOR gate NOR1 is connected to the output end of the NOR gate NOR2, an output end of the NOR gate NOR1 is connected to a first input end of the NOR gate NOR2 and a first input end of the NOR gate NOR3, a second input end of the NOR gate NOR2 is connected to a clock signal CLK, a second input end of the NOR gate NOR3 and a second input end of the NOR gate NOR4 are connected to an output voltage IN_BURST, an output end of the NOR gate NOR3 is connected to a first input end of the NOR gate NOR4 and generates a signal M2_ON, and an output end of the NOR gate NOR4 generates a signal M1_ON.
本发明与现有技术相比，具有以下优点和效果：本发明在FCCM前提下加入BURST模式，当轻负载时DC-DC可以跳周期工作，有效减少开关次数，跳周频率与带载电流成正比，并且可以规避每个开关周期都出现反流的情况，从而大幅度提高轻负载效率。并且本发明还引入了自适应消除斜坡补偿影响，可以避免在不同占空比下由于斜坡补偿电流导致进入BURST模式的电流档位偏差太大、甚至无法进入BURST模式的问题。Compared with the prior art, the present invention has the following advantages and effects: the present invention adds the BURST mode under the premise of FCCM, and the DC-DC can skip cycles when the load is light, effectively reducing the number of switches, the skip frequency is proportional to the load current, and the reverse current in each switching cycle can be avoided, thereby greatly improving the light load efficiency. In addition, the present invention also introduces adaptive elimination of the influence of slope compensation, which can avoid the problem that the current gear deviation of entering the BURST mode is too large due to the slope compensation current under different duty cycles, or even the problem that the BURST mode cannot be entered.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明的基于强制连续模式DC-DC的BURST控制电路的示意图。FIG1 is a schematic diagram of a BURST control circuit based on a forced continuous mode DC-DC according to the present invention.
图2是本发明的BURST_VREF产生器的电路图。FIG. 2 is a circuit diagram of a BURST_VREF generator according to the present invention.
图3是本发明的基于强制连续模式DC-DC的BURST控制电路的BURST控制波形示意图。FIG3 is a schematic diagram of a BURST control waveform of a BURST control circuit based on a forced continuous mode DC-DC according to the present invention.
图4是本发明的采样保持模块SENSE_HOLD的电路图。FIG. 4 is a circuit diagram of a sample-and-hold module SENSE_HOLD of the present invention.
图5是本发明的调制器PWM MODULE的电路图。FIG. 5 is a circuit diagram of a modulator PWM MODULE according to the present invention.
图6是本发明的采样保持模块SENSE_HOLD的波形示意图。FIG. 6 is a waveform diagram of the sample and hold module SENSE_HOLD of the present invention.
图7是现有技术的强制连续模式的谷值电流PWM控制环路示意图。FIG. 7 is a schematic diagram of a valley current PWM control loop in a forced continuous mode in the prior art.
图8是现有技术的强制连续模式的谷值电流PWM控制波形示意图。FIG. 8 is a schematic diagram of a valley current PWM control waveform in a forced continuous mode in the prior art.
具体实施方式DETAILED DESCRIPTION
为了详细阐述本发明为达到预定技术目的而所采取的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清晰、完整地描述，显然，所描述的实施例仅仅是本发明的部分实施例，而不是全部的实施例，并且，在不付出创造性劳动的前提下，本发明的实施例中的技术手段或技术特征可以替换，下面将参考附图并结合实施例来详细说明本发明。In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative labor. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
如图1所示，本发明的一种基于强制连续模式DC-DC的BURST控制电路，包含DC-DC变换器、误差放大器EA、电流采样电路CURRENT SENSE、PWM比较器CMP1、调制器PWM MODULE、BURST比较器CMP2和BURST_VREF产生器BURST_VREF_GEN，误差放大器EA的反向输入端连接DC-DC变换器分压反馈电路的输出信号FB，误差放大器EA的同向输入端连接基准电压信号VREF，误差放大器EA的输出端与PWM比较器CMP1的同向输入端和BURST比较器CMP2的反向输入端连接，电流采样电路CURRENT SENSE的输入端连接DC-DC变换器中功率管M2的源极，电流采样电路CURRENT SENSE的输出端输出电压信号CS，电压信号CS加上斜坡补偿电压SLOPE后与PWM比较器CMP1的反向输入端连接，PWM比较器CMP1的输出端与调制器PWM MODULE的第一输入端连接，BURST_VREF产生器BURST_VREF_GEN的输出端与BURST比较器CMP2的同向输入端连接，BURST比较器CMP2的输出端与调制器PWM MODULE的第三输入端连接，调制器PWMMODULE的第二输入端连接时钟信号CLK。As shown in FIG1 , a BURST control circuit based on a forced continuous mode DC-DC of the present invention comprises a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN, wherein the inverting input terminal of the error amplifier EA is connected to the output signal FB of the voltage divider feedback circuit of the DC-DC converter, the non-inverting input terminal of the error amplifier EA is connected to the reference voltage signal VREF, the output terminal of the error amplifier EA is connected to the non-inverting input terminal of the PWM comparator CMP1 and the inverting input terminal of the BURST comparator CMP2, the input terminal of the current sampling circuit CURRENT SENSE is connected to the source of the power tube M2 in the DC-DC converter, the output terminal of the current sampling circuit CURRENT SENSE outputs a voltage signal CS, the voltage signal CS is added with a slope compensation voltage SLOPE and connected to the inverting input terminal of the PWM comparator CMP1, the output terminal of the PWM comparator CMP1 is connected to the modulator PWM The output end of the BURST comparator CMP2 is connected to the third input end of the modulator PWM MODULE, and the second input end of the modulator PWM MODULE is connected to the clock signal CLK.
DC-DC变换器包含电源V0、电感L、功率管M11、功率管M12、电容C和分压反馈电路，电源V0的正极与电感L的一端连接，电感L的另一端与功率管M11的漏极和功率管M12的漏极连接于开关节点SW，功率管M11的栅极和功率管M12的栅极与调制器PWM MODULE的输出端连接，功率管M12的源极与电流采样电路CURRENT SENSE的输入端、电容C的一端和分压反馈电路的一端连接，电源V0的负极、功率管M11的源极、电容C的另一端和分压反馈电路的另一端接地。该实施例提供了一种Boost结构的DC-DC变换器的电路结构，本发明的技术方案同样适用于其他DC-DC开关电源结构。The DC-DC converter includes a power supply V0, an inductor L, a power tube M11, a power tube M12, a capacitor C and a voltage-dividing feedback circuit, wherein the positive electrode of the power supply V0 is connected to one end of the inductor L, the other end of the inductor L is connected to the drain of the power tube M11 and the drain of the power tube M12 at the switch node SW, the gate of the power tube M11 and the gate of the power tube M12 are connected to the output end of the modulator PWM MODULE, the source of the power tube M12 is connected to the input end of the current sampling circuit CURRENT SENSE, one end of the capacitor C and one end of the voltage-dividing feedback circuit, and the negative electrode of the power supply V0, the source of the power tube M11, the other end of the capacitor C and the other end of the voltage-dividing feedback circuit are grounded. This embodiment provides a circuit structure of a DC-DC converter with a Boost structure, and the technical solution of the present invention is also applicable to other DC-DC switching power supply structures.
调制器PWM MODULE的输出端输出的控制信号同时控制功率管M11和功率管M12的栅极，实现功率管M11和功率管M12交错导通或都关闭。当输出电压IN_BURST的电压为低电平时，调制器PWM MODULE的输出由PWM比较器CMP1的输出信号控制，输出周期性的PWM信号控制功率管M11、M12栅极驱动；当输出电压IN_BURST的电压为高电平时，调制器PWM MODULE的输出被输出电压IN_BURST屏蔽，输出信号控制功率管M11、M12都关闭。The control signal output from the output end of the modulator PWM MODULE controls the gates of the power tubes M11 and M12 at the same time, so that the power tubes M11 and M12 are switched on alternately or both are turned off. When the voltage of the output voltage IN_BURST is at a low level, the output of the modulator PWM MODULE is controlled by the output signal of the PWM comparator CMP1, and the output periodic PWM signal controls the gate drive of the power tubes M11 and M12; when the voltage of the output voltage IN_BURST is at a high level, the output of the modulator PWM MODULE is shielded by the output voltage IN_BURST, and the output signal controls the power tubes M11 and M12 to be turned off.
分压反馈电路包含电阻R11和电阻R12，电阻R11的一端与功率管M12的源极、电流采样电路CURRENT SENSE的输入端和电容C的一端连接于输出节点OUT，电阻R11的另一端与电阻R12的一端连接并产生输出信号FB，电阻R12的另一端接地。The voltage divider feedback circuit includes a resistor R11 and a resistor R12. One end of the resistor R11 is connected to the source of the power tube M12, the input end of the current sampling circuit CURRENT SENSE and one end of the capacitor C at the output node OUT. The other end of the resistor R11 is connected to one end of the resistor R12 to generate an output signal FB. The other end of the resistor R12 is grounded.
误差放大器EA的输出端产生输出信号EAO。The output terminal of the error amplifier EA generates an output signal EAO.
BURST_VREF产生器BURST_VREF_GEN的输出端产生输出电压BURST_VREF。The output terminal of the BURST_VREF generator BURST_VREF_GEN generates an output voltage BURST_VREF.
BURST比较器CMP2的输出端产生输出电压IN_BURST。当输出信号EAO的电压低于输出电压BURST_VREF时，输出电压IN_BURST的电压输出为高电平。The output terminal of the BURST comparator CMP2 generates an output voltage IN_BURST. When the voltage of the output signal EAO is lower than the output voltage BURST_VREF, the voltage of the output voltage IN_BURST is output as a high level.
BURST_VREF产生器包含采样保持模块SENSE_HOLD、匹配电阻R2和偏置电流源IB2，采样保持模块SENSE_HOLD输入端输入斜坡补偿电流ISLOPE，采样保持模块SENSE_HOLD采样并保持前一周期的斜坡补偿最大电流值ISLOPE_MAX，采样保持模块SENSE_HOLD的输出端与匹配电阻R2的一端和偏置电流源IB2的输出端连接并作为BURST_VREF产生器的输出端，匹配电阻R2的另一端接地。斜坡补偿最大电流值ISLOPE_MAX从匹配电阻R2的正端流出，偏置电流IB2流入匹配电阻R2的正端，对应的输出电压BURST_VREF为R2*(IB2-ISLOPE_MAX)。The BURST_VREF generator includes a sampling and holding module SENSE_HOLD, a matching resistor R2, and a bias current source I B2 . The input end of the sampling and holding module SENSE_HOLD inputs the slope compensation current I SLOPE . The sampling and holding module SENSE_HOLD samples and holds the maximum current value of the slope compensation I SLOPE_MAX of the previous cycle. The output end of the sampling and holding module SENSE_HOLD is connected to one end of the matching resistor R2 and the output end of the bias current source I B2 and serves as the output end of the BURST_VREF generator. The other end of the matching resistor R2 is grounded. The maximum current value of the slope compensation I SLOPE_MAX flows out from the positive end of the matching resistor R2, and the bias current I B2 flows into the positive end of the matching resistor R2. The corresponding output voltage BURST_VREF is R2*(I B2 -I SLOPE_MAX ).
采样保持模块SENSE_HOLD输入端与电阻R1的一端、电流采样电路CURRENT SENSE的主体电路CURRENT MIRROR的输出端、偏置电流源IB1的输出端连接。CURRENT MIRROR是电流采样电路CURRENT SENSE的主体电路，可以按比例径向功率管M2的电流，电流采样电路CURRENT SENSE的主体电路CURRENT MIRROR流出的电流ICS叠加偏置店楼IB1再减去斜坡补偿电流ISLOPE就是流经采样电阻R1上的总电流，采样电阻R1上的输出电压CS with Slope为R1*(ICS+IB1-ISLOPE)。The input end of the sampling and holding module SENSE_HOLD is connected to one end of the resistor R1, the output end of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE, and the output end of the bias current source I B1 . CURRENT MIRROR is the main circuit of the current sampling circuit CURRENT SENSE, which can proportionally measure the current of the power tube M2. The current I CS flowing out of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE superimposed on the bias store I B1 and then subtracted from the slope compensation current I SLOPE is the total current flowing through the sampling resistor R1. The output voltage CS with Slope on the sampling resistor R1 is R1*(I CS +I B1 -I SLOPE ).
匹配电阻R2和电阻R1的阻值相等，偏置电流源IB2和偏置电流源IB1的电流相等。The resistance values of the matching resistor R2 and the resistor R1 are equal, and the currents of the bias current source I B2 and the bias current source I B1 are equal.
BURST_VREF电压始终跟随前一周期的斜坡补偿。EAO电压的均值近似等于CS withSlope电压的最低点The BURST_VREF voltage always follows the slope compensation of the previous cycle. The average value of the EAO voltage is approximately equal to the lowest point of the CS withSlope voltage.
EAO≈(CS with Slope)min= R1*(ICS+IB1-ISLOPE_MAX)EAO≈(CS with Slope) min = R1*(I CS +I B1 -I SLOPE_MAX )
可以设计BURST_VREF_GEN匹配电阻R2等于R1，偏置电流IB2等于IB1，BURST_VREF数值就会是The BURST_VREF_GEN matching resistor R2 can be designed to be equal to R1, the bias current I B2 is equal to I B1 , and the BURST_VREF value will be
BURST_VREF = R1*(IB1-ISLOPE_MAX)BURST_VREF = R1*(I B1 -I SLOPE_MAX )
这就意味着当EAO接近BURST_VREF时，ICS近似为0，即此时的电感电流为0mA，进而阻止了DC-DC进入反流状态。因为，不同占空比下ISLOPE_MAX数值不同，上述设计可以有效对消掉斜坡补偿带来的影响。This means that when EAO is close to BURST_VREF, I CS is approximately 0, that is, the inductor current is 0mA at this time, thereby preventing the DC-DC from entering the reverse flow state. Because the I SLOPE_MAX value is different under different duty cycles, the above design can effectively eliminate the impact of slope compensation.
采样保持模块SENSE_HOLD包含晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、晶体管M7、电阻R3、电阻R4、运算放大器OP1、运算放大器OP2、运算放大器OP3、开关S1、开关S2、保持电容CHOLD1和CHOLD2，晶体管M1的漏极与晶体管M1的栅极、晶体管M2的栅极和晶体管M3的栅极连接并输入斜坡补偿电流的源头SLOPE CURRENT SOURCE，晶体管M2的漏极与晶体管M4的漏极、晶体管M4的栅极和晶体管M5的栅极连接，晶体管M3的漏极输出斜坡补偿电流SLOPE CURRENT，晶体管M4的源极与晶体管M5的源极、晶体管M6的源极和晶体管M7的源极连接，晶体管M5的漏极与电阻R3的一端和运算放大器OP1的同向输入端连接，运算放大器OP1的输出端与运算放大器OP1的反向输入端和开关S1的一端连接，开关S1的另一端与运算放大器OP2的同向输入端和保持电容CHOLD1的一端连接，运算放大器OP2的输出端与运算放大器OP2的反向输入端和开关S2的一端连接，开关S2的另一端与运算放大器OP3的同向输入端和保持电容CHOLD2的一端连接，运算放大器OP3的输出端与运算放大器OP3的反向输入端、电阻R4的一端、晶体管M6的漏极、晶体管M6的栅极和晶体管M7的栅极连接，晶体管M7的漏极输出斜坡补偿电流的最大值SLOPE CURRENT MAX，晶体管M1的源极、晶体管M2的源极、晶体管M3的源极、电阻R3的另一端、保持电容CHOLD1的另一端、保持电容CHOLD2的另一端和电阻R4的另一端接地。The sampling and holding module SENSE_HOLD includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a resistor R3, a resistor R4, an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP3, a switch S1, a switch S2, and holding capacitors C HOLD1 and C HOLD2 . The drain of the transistor M1 is connected to the gate of the transistor M1, the gate of the transistor M2, and the gate of the transistor M3 and inputs the source of the slope compensation current SLOPE CURRENT SOURCE. The drain of the transistor M2 is connected to the drain of the transistor M4, the gate of the transistor M4, and the gate of the transistor M5. The drain of the transistor M3 outputs the slope compensation current SLOPE CURRENT, the source of the transistor M4 is connected to the source of the transistor M5, the source of the transistor M6 and the source of the transistor M7, the drain of the transistor M5 is connected to one end of the resistor R3 and the non-inverting input of the operational amplifier OP1, the output of the operational amplifier OP1 is connected to the inverting input of the operational amplifier OP1 and one end of the switch S1, the other end of the switch S1 is connected to the non-inverting input of the operational amplifier OP2 and one end of the holding capacitor C HOLD1 , the output of the operational amplifier OP2 is connected to the inverting input of the operational amplifier OP2 and one end of the switch S2, the other end of the switch S2 is connected to the non-inverting input of the operational amplifier OP3 and one end of the holding capacitor C HOLD2 , the output of the operational amplifier OP3 is connected to the inverting input of the operational amplifier OP3, one end of the resistor R4, the drain of the transistor M6, the gate of the transistor M6 and the gate of the transistor M7, and the drain of the transistor M7 outputs the maximum value of the slope compensation current SLOPE CURRENT MAX, the source of the transistor M1, the source of the transistor M2, the source of the transistor M3, the other end of the resistor R3, the other end of the holding capacitor C HOLD1 , the other end of the holding capacitor C HOLD2 and the other end of the resistor R4 are grounded.
晶体管M1、晶体管M2和晶体管M3构成1:1:1电流镜，晶体管M4和晶体管M5构成1:1电流镜，节点V1的电压与斜坡补偿电流成正比：Transistor M1, transistor M2 and transistor M3 form a 1:1:1 current mirror, transistor M4 and transistor M5 form a 1:1 current mirror, and the voltage of node V1 is proportional to the slope compensation current:
V1=ISLOPE*R3。V1=I SLOPE *R3.
运算放大器OP1构成的单位增益负反馈运放输出与节点V1相等的电压。在斜坡电流上升阶段，开关S1闭合，运算放大器OP1给保持电容CHOLD1充电使得节点V2近似等于节点V1的电压；在斜坡电流下降前一刻，开关S1断开，保持电容CHOLD1保持当前最大电压：The unit gain negative feedback op amp formed by operational amplifier OP1 outputs a voltage equal to node V1. In the rising phase of the ramp current, switch S1 is closed, and operational amplifier OP1 charges the holding capacitor C HOLD1 so that node V2 is approximately equal to the voltage of node V1; just before the ramp current drops, switch S1 is disconnected, and holding capacitor C HOLD1 maintains the current maximum voltage:
V2_MAX=V1_MAX=ISLOPE_MAX*R3。V2_MAX=V1_MAX=I SLOPE_MAX *R3.
运算放大器OP2构成的单位增益负反馈运放输出与节点V2相等的电压。在节点V2保持当前最大电压阶段，开关S2闭合，运算放大器OP2给保持电容CHOLD2充电使得节点V3近似等于节点V2的电压；在节点V2进入充电前一刻，开关S2断开，保持电容CHOLD2保持当前电压，因此，节点V3每个周期都保持：The unit gain negative feedback amplifier formed by the operational amplifier OP2 outputs a voltage equal to the node V2. When the node V2 maintains the current maximum voltage, the switch S2 is closed, and the operational amplifier OP2 charges the holding capacitor C HOLD2 so that the node V3 is approximately equal to the voltage of the node V2; before the node V2 enters the charging state, the switch S2 is opened, and the holding capacitor C HOLD2 maintains the current voltage. Therefore, the node V3 maintains:
V3= V2_MAX=ISLOPE_MAX*R3。V3= V2_MAX=I SLOPE _MAX*R3.
运算放大器OP3构成的单位增益负反馈运放输出与节点V3相等的电压，因此电阻R4上的电压是V3。晶体管M6和M7构成1:1电流镜，则输出电流为ISLOPE_MAX*R3/R4；R3、R4取值相同，则输出电流为ISLOPE_MAX。上述整个过程如图6所示。The unit gain negative feedback amplifier formed by operational amplifier OP3 outputs a voltage equal to node V3, so the voltage on resistor R4 is V3. Transistors M6 and M7 form a 1:1 current mirror, and the output current is I SLOPE _MAX*R3/R4; if R3 and R4 have the same value, the output current is I SLOPE _MAX. The above whole process is shown in Figure 6.
如图5所示，调制器PWM MODULE包含或非门NOR1、或非门NOR2、或非门NOR3和或非门NOR4，或非门NOR1的第一输入端与比较器CMP1的输出端连接，或非门NOR1的第二输入端与或非门NOR2的输出端连接，或非门NOR1的输出端与或非门NOR2的第一输入端和或非门NOR3的第一输入端连接，或非门NOR2的第二输入端连接时钟信号CLK，或非门NOR3的第二输入端和或非门NOR4的第二输入端连接输出电压IN_BURST，或非门NOR3的输出端与或非门NOR4的第一输入端连接并产生信号M2_ON，或非门NOR4的输出端产生信号M1_ON。当输出电压IN_BURST为1时，信号M1_ON和信号M2_ON同时为0，即输出信号控制功率管M11、M12都关闭。As shown in FIG5 , the modulator PWM MODULE includes a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4, wherein the first input end of the NOR gate NOR1 is connected to the output end of the comparator CMP1, the second input end of the NOR gate NOR1 is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2 and the first input end of the NOR gate NOR3, the second input end of the NOR gate NOR2 is connected to the clock signal CLK, the second input end of the NOR gate NOR3 and the second input end of the NOR gate NOR4 are connected to the output voltage IN_BURST, the output end of the NOR gate NOR3 is connected to the first input end of the NOR gate NOR4 and generates a signal M2_ON, and the output end of the NOR gate NOR4 generates a signal M1_ON. When the output voltage IN_BURST is 1, the signal M1_ON and the signal M2_ON are both 0, that is, the output signal controls the power tubes M11 and M12 to be turned off.
本发明解决了由于AMOLED驱动芯片正压输出Boost工作在强制连续模式，轻负载下存在反流现象并且每个时钟周期都会开关动作，导致的轻载效率过低的问题。如图8所示为传统方案对应的波形图，每个开关周期都会带来开关损耗，并且电感电流反流也会带来额外损耗。The present invention solves the problem of low light load efficiency caused by the positive voltage output Boost of the AMOLED driver chip working in a forced continuous mode, the reverse flow phenomenon under light load, and the switching action in each clock cycle. As shown in Figure 8, the waveform corresponding to the traditional solution will cause switching loss in each switching cycle, and the reverse flow of the inductor current will also cause additional loss.
本发明在强制连续模式前提下加入BURST模式，当轻负载时DC-DC可以跳周期工作，有效减少开关次数，跳周频率与带载电流成正比，并且可以规避每个开关周期都出现反流的情况，从而大幅度提高轻负载效率。并且本发明还引入了自适应消除斜坡补偿影响，可以避免在不同占空比下由于斜坡补偿电流导致进入BURST模式的电流档位偏差太大、甚至无法进入BURST模式的问题。如图3所示为本发明方案对应的波形图，随着负载降低，跳周期的频率会越低；当负载足够小时，跳周周期远大于时钟周期时，开关损耗也将比传统方案小至少一个数量级，这将极大地提高轻载效率。并且，本发明方案的BURST_VREF信号跟随斜坡电流动态调节，消除斜坡补偿带来的偏差，可以在不同占空比下保证进入BURST模式的负载电流不明显变化。The present invention adds the BURST mode under the premise of forced continuous mode. When the load is light, the DC-DC can work in a skip cycle, effectively reducing the number of switches. The skip cycle frequency is proportional to the load current, and the reverse current in each switching cycle can be avoided, thereby greatly improving the light load efficiency. In addition, the present invention also introduces adaptive elimination of the influence of slope compensation, which can avoid the problem that the current gear deviation entering the BURST mode is too large or even cannot enter the BURST mode due to the slope compensation current under different duty cycles. As shown in Figure 3, the waveform diagram corresponding to the scheme of the present invention is that as the load decreases, the frequency of the skip cycle will be lower; when the load is small enough and the skip cycle is much larger than the clock cycle, the switching loss will also be at least one order of magnitude smaller than the traditional scheme, which will greatly improve the light load efficiency. In addition, the BURST_VREF signal of the scheme of the present invention follows the dynamic adjustment of the slope current, eliminates the deviation caused by the slope compensation, and can ensure that the load current entering the BURST mode does not change significantly under different duty cycles.
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质，在本发明的精神和原则之内，对以上实施例所作的任何简单的修改、等同替换与改进等，均仍属于本发明技术方案的保护范围之内。The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410995594.8A CN118713475B (en) | 2024-07-24 | 2024-07-24 | A BURST control circuit based on forced continuous mode DC-DC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410995594.8A CN118713475B (en) | 2024-07-24 | 2024-07-24 | A BURST control circuit based on forced continuous mode DC-DC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118713475A true CN118713475A (en) | 2024-09-27 |
| CN118713475B CN118713475B (en) | 2024-12-13 |
Family
ID=92818001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410995594.8A Active CN118713475B (en) | 2024-07-24 | 2024-07-24 | A BURST control circuit based on forced continuous mode DC-DC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118713475B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119482294A (en) * | 2024-12-09 | 2025-02-18 | 深圳市微源半导体股份有限公司 | Switching power supply protection circuit and electronic equipment based on forced continuous mode |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123395A (en) * | 2006-08-04 | 2008-02-13 | 凌特公司 | Circuit and method for adjustable peak inductor current and hysteresis in burst mode in switching regulator |
| US20110037446A1 (en) * | 2009-08-14 | 2011-02-17 | Linear Technology Corporation | Switch mode power supply with dynamic topology |
| US10763738B1 (en) * | 2019-07-03 | 2020-09-01 | Silanna Asia Pte Ltd | Light load mode entry or exit for power converter |
| CN115037127A (en) * | 2022-07-22 | 2022-09-09 | 西安水木芯邦半导体设计有限公司 | Pulse hopping modulation circuit capable of realizing light load and high efficiency and control method |
| CN115276407A (en) * | 2022-08-09 | 2022-11-01 | 重庆邮电大学 | DC-DC mode switching circuit based on self-adaptive peak current |
| CN117526711A (en) * | 2024-01-03 | 2024-02-06 | 拓尔微电子股份有限公司 | Voltage conversion circuit, voltage conversion method and power management chip |
-
2024
- 2024-07-24 CN CN202410995594.8A patent/CN118713475B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123395A (en) * | 2006-08-04 | 2008-02-13 | 凌特公司 | Circuit and method for adjustable peak inductor current and hysteresis in burst mode in switching regulator |
| US20110037446A1 (en) * | 2009-08-14 | 2011-02-17 | Linear Technology Corporation | Switch mode power supply with dynamic topology |
| US10763738B1 (en) * | 2019-07-03 | 2020-09-01 | Silanna Asia Pte Ltd | Light load mode entry or exit for power converter |
| CN115037127A (en) * | 2022-07-22 | 2022-09-09 | 西安水木芯邦半导体设计有限公司 | Pulse hopping modulation circuit capable of realizing light load and high efficiency and control method |
| CN115276407A (en) * | 2022-08-09 | 2022-11-01 | 重庆邮电大学 | DC-DC mode switching circuit based on self-adaptive peak current |
| CN117526711A (en) * | 2024-01-03 | 2024-02-06 | 拓尔微电子股份有限公司 | Voltage conversion circuit, voltage conversion method and power management chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119482294A (en) * | 2024-12-09 | 2025-02-18 | 深圳市微源半导体股份有限公司 | Switching power supply protection circuit and electronic equipment based on forced continuous mode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118713475B (en) | 2024-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105356734B (en) | It is a kind of that the Buck circuit power managing chips containing ripple compensation are controlled based on COT | |
| TWI387191B (en) | Voltage mode switching regulator and control circuit and method therefor | |
| CN209134299U (en) | Switching power converter and its load current detection circuit | |
| US11469668B2 (en) | Step-up switching converter and control circuit and method thereof | |
| CN106787652B (en) | A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit | |
| CN101471603B (en) | DC-DC buck converter and ripple improvement circuit | |
| CN118713475A (en) | A BURST control circuit based on forced continuous mode DC-DC | |
| CN111900878B (en) | Adaptive hysteresis control converter for enhancing transient characteristics, control method and device | |
| CN114865913B (en) | On-time generator with low power consumption function | |
| CN112953224B (en) | DC-DC conversion circuit and power supply | |
| CN111786556A (en) | A Dual-Mode Compensation System for Peak Current Control Mode Boost Converters | |
| CN113422512A (en) | Four-switch control circuit | |
| TWM653794U (en) | Power converter circuit and control circuit thereof | |
| CN117375422A (en) | Buck-Boost converter mode switching circuit | |
| CN216672860U (en) | Four-switch control circuit | |
| CN114421756A (en) | Circuit to eliminate the effect of slope compensation on load capacity | |
| CN115276407A (en) | DC-DC mode switching circuit based on self-adaptive peak current | |
| CN114696608A (en) | Valley mode DC-DC converter | |
| CN116317559B (en) | A mode switching circuit for peak current mode Buck converter | |
| CN221553101U (en) | Power converter circuit and control circuit thereof | |
| Li et al. | Design of valley current sensing with low output voltage ripple based on CMCOT | |
| TWI848881B (en) | Power converter circuit and control circuit thereof | |
| CN117498658B (en) | Ramp signal generating circuit and generating method | |
| Chen et al. | PT controlled PCCM buck converter with adaptive pulse train generator and NMOS current sensor | |
| CN118748512B (en) | Ripple injection type direct current converter and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |