CN118709635A - Layout generation method, device, medium, program product and terminal for optimizing pattern density distribution - Google Patents

Abstract

The present application provides a layout generation method, device, medium, program product and terminal for optimizing the distribution of graphic density. Through the scheme of equalizing grid filling, the original curve layout is gridded and the blank grids are filled. Taking the surrounding layout graphics into consideration, the effective filling of complex curves and irregular shapes is successfully achieved. While increasing the layout density, the present application greatly improves the density distribution of the layout, ensures the uniformity of filling, and avoids the problem of poor CMP effect caused by uneven filling. In addition, the present application is applicable to both Manhattan layouts and curved layouts, has fast and convenient operation characteristics, and effectively improves layout utilization, design efficiency and layout performance.

Description

Layout generation method, device, medium, program product and terminal for optimizing graphic density distribution

Technical Field

The present application relates to the semiconductor field, and in particular to a layout generation method, device, medium, program product and terminal for optimizing the distribution of graphic density.

Background Art

In modern integrated circuit design and manufacturing, filling technology is a key process, and its main purpose is to optimize electrical performance, improve manufacturing yield and ensure chip reliability. Layout filling is usually used to fill blank areas in the design to ensure the uniformity and stability of the structure to reduce the risk of defects in the manufacturing process. The existence of blank areas may lead to a decrease in structural uniformity, which will affect the overall manufacturing quality. Through filling, a consistent density distribution can be maintained, thereby avoiding the problem of non-uniformity in subsequent processes. Filling technology can also effectively improve the electrical performance of the circuit. After filling the blank area, the current flow becomes more stable, which not only improves the integrity of the signal, but also reduces the risk of crosstalk and interference. In addition, a good filling design can prevent uneven material distribution and improve the overall manufacturing yield. It is also particularly important for subsequent processes such as lithography and chemical mechanical polishing (CMP, Chemical Mechanical Polishing), because uniform density distribution can reduce the problems caused by non-uniformity during processing.

Existing filling technologies are mainly divided into several types, including regular filling, random filling, density filling, etc. These methods improve electrical characteristics and manufacturing yield by filling blank areas. Specifically, the regular filling method uses fixed geometric shapes to fill blank areas, while the density filling optimizes the filling strategy according to the specific density distribution in the design. However, these traditional methods are mainly based on the assumption of Manhattan geometry, that is, the graphics in the design are mainly composed of horizontal and vertical line segments, forming regular straight lines and rectangular structures. Therefore, most of the above filling techniques are suitable for simple straight lines and rectangular structures, but when dealing with complex curved layouts, it is difficult to respond flexibly, resulting in insufficient filling or uneven shapes.

In addition, due to the limitation of fixed geometric shapes and density distribution, existing filling technologies may also introduce periodic effects, affecting signal integrity and further affecting the overall performance of the chip. At the same time, dynamically changing design requirements also make these methods insufficient in adaptability and often fail to meet the manufacturing requirements of high efficiency and yield.

Summary of the invention

In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a layout generation method, device, medium, program product and terminal for optimizing the distribution of graphic density, so as to solve the problem that the existing filling technology lacks flexibility when dealing with complex curves and irregular shapes, resulting in uneven filling effects and possible manufacturing defects.

To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a method for generating a layout for optimizing the distribution of graphic density, the method comprising: obtaining an original layout and a minimum spacing between graphics, the original layout containing one or more layout graphics; generating a layout prohibited area corresponding to the original layout based on the minimum spacing between graphics and all layout graphics; square-gridding the original layout, traversing each grid, and determining the overlapping relationship between each grid and the layout prohibited area, marking the grids that do not overlap with the layout prohibited area to generate one or more marked grids; filling each marked grid according to a preset filling rule to generate a filled grid; merging the filled grid with the original layout to generate a layout with optimized graphic density.

In some embodiments of the first aspect of the present application, based on the minimum spacing between graphics and all layout graphics, the process of generating a layout prohibited area corresponding to the original layout includes: generating a minimum area outer frame surrounding the graphic according to the upper, lower, left and right limit coordinate values of each layout graphic; expanding each of the minimum area outer frames in a direction away from the center of the corresponding layout graphic by the minimum spacing between graphics to generate a prohibited area of the corresponding layout graphic; and merging the prohibited areas of all layout graphics to generate a layout prohibited area.

In some embodiments of the first aspect of the present application, the outer frame of the minimum area includes: one or more of a circle, an ellipse, a polygon, and an irregular shape.

In some embodiments of the first aspect of the present application, each marked grid is filled according to a preset filling rule to generate a filled grid. The process includes: traversing each marked grid and performing the following operations: taking the current marked grid as the center, looping through a preset direction set, and for each preset direction, searching for a layout graphic that is closest to the direction; overlapping the searched multiple layout graphics in a manner of aligning the center points to generate a to-be-filled graphic corresponding to the current marked grid; scaling the to-be-filled graphic so that the scaled to-be-filled graphic does not exceed the grid boundary of the current marked grid, and filling the scaled to-be-filled graphic into the current marked grid to generate a filled grid.

In some embodiments of the first aspect of the present application, the preset direction set includes: up, down, left, and right.

In some embodiments of the first aspect of the present application, a set of preset directions is traversed in a loop, and for each preset direction, a process of searching for a layout graphic that is closest to the direction also includes: if no layout graphic is found in the current preset direction, skipping the current preset direction and continuing to traverse the next preset direction in the preset direction set.

To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a layout generation device for optimizing the distribution of graphic density, including: a restricted area generation module: used to obtain the original layout and the minimum spacing between graphics, the original layout containing one or more layout graphics; based on the minimum spacing between graphics and all layout graphics, generate a layout prohibited area corresponding to the original layout; a grid marking module: used to square grid the original layout, traverse each grid, and determine the overlapping relationship between each grid and the layout prohibited area, mark the grids that do not overlap with the layout prohibited area to generate one or more marked grids; a filling optimization module: used to fill each marked grid according to a preset filling rule to generate a filled grid; merge the filled grid with the original layout to generate a graphic density optimized layout.

To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the layout generation method for optimizing the graphic density distribution is implemented.

To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code is run on a computer, the computer implements the layout generation method for optimizing the graphic density distribution.

To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the layout generation method for optimizing the graphic density distribution.

As described above, the layout generation method, device, medium, program product and terminal for optimizing the distribution of graphic density of the present application have the following beneficial effects: through the scheme of equalizing grid filling, the original curve layout is gridded and the blank grids are filled, and the surrounding layout graphics are comprehensively considered to successfully achieve the effective filling of complex curves and irregular shape layouts. While improving the layout density, the present application greatly improves the density distribution of the layout, ensures the uniformity of filling, and avoids the problem of poor CMP effect caused by uneven filling. In addition, the present application is applicable to both Manhattan layouts and curved layouts, has fast and convenient operation characteristics, and effectively improves the layout utilization, design efficiency and layout performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flow chart showing an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 2 shows an original layout in an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 3 shows a schematic diagram of the minimum area outer frame in an embodiment of a layout generation method for optimizing the pattern density distribution of the present application.

FIG. 4 shows a layout forbidden area in an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 5 shows a schematic diagram of square gridding in an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 6 shows a schematic diagram of blank grid marking in an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 7 shows a schematic diagram of a graphic to be filled in an embodiment of a layout generation method for optimizing the distribution of graphic density of the present application.

FIG8 shows a schematic diagram of a filling and marking grid in an embodiment of a layout generation method for optimizing pattern density distribution of the present application.

FIG. 9 shows a schematic structural diagram of an embodiment of a layout generation device for optimizing pattern density distribution of the present application.

FIG. 10 shows a schematic structural diagram of an embodiment of a layout generation terminal for optimizing the pattern density distribution of the present application.

DETAILED DESCRIPTION

The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

Before further describing the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

<1> Chip layout: Chip layout is a planar graphic representation used to depict device layout and circuit connections during the integrated circuit design process. It contains the physical location and size information of semiconductor devices (such as transistors, diodes, etc.), interconnect wires and other functional components.

<2>Layout graphics: Layout graphics refer to the specific shapes and structures contained in the chip layout, including all the connections between circuit elements and layout graphics. Layout graphics constitute the visual representation of the layout and are usually displayed in the form of geometric figures.

<3>Minimum spacing between graphics: The minimum spacing between graphics refers to the minimum physical distance allowed between two adjacent graphics (such as wires or devices) in the integrated circuit layout. This parameter is crucial to ensure the feasibility of the manufacturing process and circuit performance.

<4> Layout forbidden area: Layout forbidden area refers to certain areas in chip design that are designated as areas where no circuit elements or signal connections can be placed. This is usually to avoid physical interference or improve circuit performance.

<5> Gridding: Gridding is the process of dividing the layout into multiple small grid cells for optimized filling or other design operations. In this way, the structure of the layout can be managed and adjusted more effectively.

<6>Layout density: Layout density refers to the number of circuit components contained in a unit area or the area ratio occupied by the layout pattern. High layout density usually means smaller chip size and improved functional integration.

To facilitate understanding of the embodiment of the present application, a detailed description is first given in conjunction with FIG1. FIG1 shows a schematic flow chart of a layout generation method for optimizing the pattern density distribution in the embodiment of the present application. The layout generation method for optimizing the pattern density distribution in the present embodiment mainly includes the following steps:

Step S11: obtaining an original layout and a minimum spacing between graphics, wherein the original layout includes one or more layout graphics; based on the minimum spacing between graphics and all layout graphics, generating a layout prohibited area corresponding to the original layout.

FIG2 shows the original layout obtained in an embodiment of the present application, which contains 4 layout graphics of different shapes. The original layout refers to the physical structure design of the integrated circuit, which is used to describe the size, shape, position and interconnection method of the components in the circuit. The layout is a blueprint for chip manufacturing, which determines the function, performance and reliability of the chip. The minimum spacing between graphics refers to the minimum distance allowed between two graphics on the layout. This distance is usually determined by the capability of the manufacturing process and is used to ensure that short circuits or other adverse effects do not occur between different graphics in the circuit, thereby ensuring the normal operation of the chip.

In one embodiment of the present application, based on the minimum spacing between graphics and all layout graphics, the process of generating a layout forbidden area corresponding to the original layout includes: generating a minimum area outer frame surrounding the graphic according to the upper, lower, left, and right limit coordinate values of each layout graphic; extending each of the minimum area outer frames away from the center of the corresponding layout graphic by the minimum spacing between graphics as a distance to generate a forbidden area of the corresponding layout graphic; merging the forbidden areas of all layout graphics to generate a layout forbidden area. Figure 3 shows a schematic diagram of generating a minimum area outer frame surrounding the graphic according to the upper, lower, left, and right limit coordinate values of each layout graphic in one embodiment of the present invention.

In one embodiment of the present application, the process of generating a layout prohibited area includes: identifying the layout graphics in the original layout, and obtaining the type and size information of the layout graphics, and generating a minimum matrix area surrounding the layout graphics based on the upper, lower, left and right limit coordinate values of each layout graphic. Obtain the minimum spacing between graphics, wherein the minimum spacing between graphics includes a uniform spacing or generating different minimum spacings for different types of layout graphics. Exemplarily, the minimum spacing between metal layer graphics is set to 10nm, and the minimum distance between the metal layer graphics and other layout graphics is defined as 5nm. Each minimum enclosing area is expanded in a direction away from the center of the corresponding graphic, and the expansion distance is the minimum spacing of the corresponding graphic type to generate the final layout prohibited area.

In an embodiment of the present application, the outer frame of the minimum area includes: one or more of a circle, an ellipse, a polygon, and an irregular shape.

Furthermore, in the mask layout, common graphic shapes include circles, ovals, polygons and irregular shapes. For example, circular leads, circular capacitors and circular vias are surrounded by a circular minimum area outer frame; rectangular leads, elliptical capacitors and elliptical vias are surrounded by an elliptical outer frame; polygonal metal patterns and polygonal isolation areas are surrounded by polygonal outer frames; and text, symbols, complex metal patterns, mixed shapes containing curves and straight lines, etc. require irregular outer frames. For more complex graphics such as rounded rectangles, choose a combination of circles, rectangles or polygons according to the actual situation, or directly use polygons to surround them.

FIG4 shows the forbidden area of the layout in an embodiment of the present application. The solid rectangular frame on the inside is the layout figure, the dotted frame on the outside is the corresponding forbidden area generated by the curved layout, and the distance between the inner border and the outer border is the minimum area outer border. In this embodiment, a rectangular frame is used. The minimum spacing in this embodiment is set to d.

Step S12: square gridding the original layout, traversing each grid, and determining the overlapping relationship between each grid and the forbidden area of the layout, marking the grids that do not overlap with the forbidden area of the layout to generate one or more marked grids.

FIG5 shows a schematic diagram of square gridding of the original layout in one embodiment of the present invention. The process of square gridding the original layout includes: setting the grid size to an integer multiple of DBU (Design Rule Unit). The advantage of such a setting is that it can ensure compliance with the design rules, improve design accuracy, and simplify the design process. DBU is determined by the process node and is used to standardize the minimum size and spacing of various elements in the integrated circuit design, usually in nanometers (nm). When the grid size is an integer multiple of DBU, it can effectively avoid problems such as the component size failing to meet the minimum size requirement or the component spacing failing to meet the minimum spacing requirement due to the mismatch between the grid size and the design rules, thereby ensuring compliance with the design rules, improving design accuracy, simplifying the design process, and ultimately improving the accuracy and efficiency of subsequent filling steps.

In one embodiment of the present application, the process of marking grids that do not overlap with the prohibited area of the layout includes: setting the grids that do not overlap with the prohibited area of the layout to a specific color, or marking the non-overlapping grids as usable; marking the overlapping grids as unusable; or generating a new grid data structure that only contains non-overlapping grid information and marking these grids as usable.

Figure 6 shows a schematic diagram of blank grid marking in an embodiment of the present application. After the curve layout is gridded, the relative positions of the curve layout and the gridded graphics are compared, and the grids that do not overlap with the forbidden area of the layout are marked with red five-pointed stars.

Step S13: Fill each marked grid according to a preset filling rule to generate a filled grid; merge the filled grid with the original layout to generate a graphic density optimized layout.

In one embodiment of the present application, each marked grid is filled according to a preset filling rule to generate a filled grid. The process includes: traversing each marked grid and performing the following operations: taking the current marked grid as the center, looping through a preset direction set, and for each preset direction, searching for a layout graphic that is closest to the direction; overlapping the searched multiple layout graphics in a manner of aligning the center points to generate a to-be-filled graphic corresponding to the current marked grid; scaling the to-be-filled graphic so that the scaled to-be-filled graphic does not exceed the grid boundary of the current marked grid, and filling the scaled to-be-filled graphic into the current marked grid to generate a filled grid.

In one embodiment of the present application, the order of traversing each marked grid includes but is not limited to traversing from left to right and/or from top to bottom. The preset direction set defines the direction of searching the layout graphics. For example, the search directions in the set include but are not limited to: up, down, left, and right. It can also include oblique directions of multiple different preset angles.

In one embodiment of the present application, the process of searching for the closest layout graphic in each preset direction includes: searching each preset direction with the current marked grid as the center. The search target is the layout graphic closest to the center point of the current marked grid. The search method includes but is not limited to distance calculation, such as using Euclidean distance.

In one embodiment of the present application, the multiple layout graphics searched are overlapped in a center-point aligned manner, effectively avoiding the problem of uneven filling due to differences in the shape and size of the layout graphics. For example, if the two layout graphics searched are both circular, but the radii are different, the two circular layouts are overlapped by center alignment to form a larger circle. Figure 7 shows a schematic diagram of a figure to be filled in one embodiment of the present application, and the generation process includes, for the five-pointed star in the lower left corner, the triangle located above and the trapezoid on the right are centrally superimposed to generate the first pattern in Figure 7, and the first pattern in Figure 7 is filled to the marking position in the lower left corner of Figure 6. The marking grid on the upper middle side of Figure 7 is centrally overlapped by the triangle on its left side, the trapezoid on the lower side, and the hexagon on the right to generate the second pattern in Figure 7. Similarly, for the marking grid on the lower right side, the square on the left side of the current marking grid and the hexagon on the upper side are centrally overlapped to generate the third pattern in Figure 7, and the current pattern is filled to the marking grid on the lower right.

It is worth noting that the advantage of the above-mentioned overlapping generation of new graphics by center point alignment is that the generation of new patterns can effectively solve the problems of uneven filling effect and manufacturing defects encountered by the existing technology when processing complex curves and irregular shapes. Through operations such as center overlap, more complex and flexible filling patterns can be generated to meet the filling needs of various shapes, thereby improving the filling effect and optimizing the manufacturing process, reducing material waste and manufacturing defects, and ultimately improving manufacturing efficiency and product quality.

In one embodiment of the present application, the process of scaling the graphic to be filled includes: first obtaining the width and height of the graphic to be filled, and the width and height of the current marked grid. Then, calculating the ratio of the width and height of the graphic to be filled to the width and height of the grid boundary, and selecting the larger ratio as the scaling ratio. Then, using this ratio to scale the graphic to be filled. In order to ensure that the scaled graphic is completely within the grid boundary. Perform a verification operation on the scaled graphic, specifically, compare the scaled graphic width and height with the grid boundary width and height. If it is found that the graphic exceeds the boundary, it is necessary to recalculate the scaling ratio and re-execute the scaling operation until the corresponding size requirement is met.

FIG8 shows a schematic diagram of a filled marking grid in an embodiment of the present application, showing the process of filling the scaled to-be-filled graphic into the current marked grid. The to-be-filled graphic generated in FIG7 is scaled to an appropriate size and filled into the marked blank grid. The filled grid is merged with the original layout to generate a final graphic density optimized layout.

In one embodiment of the present application, a set of preset directions is traversed in a loop, and for each preset direction, a process of searching for a layout graphic closest to the direction also includes: if no layout graphic is found in the current preset direction, skipping the current preset direction and continuing to traverse the next preset direction in the preset direction set.

In this embodiment, in order to effectively search for the nearest layout pattern in a layout containing a corner marking grid, a strategy of looping through a set of preset directions is adopted. The algorithm tries each preset direction in turn and searches for the closest layout pattern in the current direction. If no pattern is found in a certain direction, the algorithm skips that direction and continues to traverse the next direction. This design ensures that the nearest layout pattern can be found even in a corner grid, thereby improving the robustness of the layout generation method for optimizing the pattern density distribution.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b, c can be single or multiple.

Fig. 9 is a schematic block diagram of a layout generation device for optimizing pattern density distribution provided by an embodiment of the present application. As shown in Fig. 9 , the device includes: a restricted area generation module 901 , a grid marking module 902 , and a filling optimization module 903 .

Forbidden zone generation module 901: used to obtain the original layout and the minimum spacing between graphics, wherein the original layout includes one or more layout graphics; based on the minimum spacing between graphics and all layout graphics, generate a layout forbidden area corresponding to the original layout.

Grid marking module 902: used to square grid the original layout, traverse each grid, and determine the overlapping relationship between each grid and the prohibited area of the layout, and mark the grids that do not overlap with the prohibited area of the layout to generate one or more marked grids.

Filling optimization module 903: used to fill each marked grid according to a preset filling rule to generate a filled grid; merge the filled grid with the original layout to generate a graphic density optimized layout.

It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

FIG10 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. As shown in FIG10 , the electronic terminal includes: at least one processor 101, a memory 102, at least one network interface 103 and a user interface 105. The various components in the device are coupled together via a bus system 104. It is understandable that the bus system 104 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 104 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, various buses are marked as bus systems in FIG10 .

The user interface 105 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

It is understood that the memory 102 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present application is intended to include but is not limited to these and any other suitable categories of memory.

The memory 102 in the embodiment of the present application is used to store various categories of data to support the operation of the electronic terminal 100. Examples of these data include: any executable program for operating on the electronic terminal 100, such as an operating system 1021 and an application 1022; the operating system 1021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 1022 may include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The layout generation method for optimizing the graphic density distribution provided in the embodiment of the present application may be included in the application 1022.

The method disclosed in the above embodiment of the present application can be applied to the processor 101, or implemented by the processor 101. The processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 101 or an instruction in the form of software. The above processor 101 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 101 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor 101 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

In an exemplary embodiment, the electronic terminal 100 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes the layout generation method for optimizing graphic density distribution in any of the embodiments shown above.

According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code is run on a computer, the computer executes a layout generation method for optimizing graphic density distribution in any of the embodiments shown above.

The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and/or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and/or an execution thread, and a component may be located on a computer and/or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and/or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and/or a network, such as the Internet interacting with other systems through signals).

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

In summary, the present application provides a layout generation method, device, medium, program product and terminal for optimizing the distribution of graphic density. The present application provides a more flexible and efficient layout generation scheme. The original curve layout is gridded by a balanced grid filling scheme, and blank grids are filled. The surrounding layout graphics are comprehensively considered, and the effective filling of complex curves and irregular shape layouts is successfully achieved. While improving the layout density, the present application greatly improves the density distribution of the layout, ensures the uniformity of the filling, and avoids the problem of poor CMP effect caused by uneven filling. In addition, the present application is applicable to both Manhattan layouts and curved layouts, has fast and convenient operating characteristics, and effectively improves layout utilization, design efficiency and layout performance. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims (10)

1. A layout generation method for optimizing density distribution of a graphic, the method comprising:

Obtaining an original layout and a minimum distance between patterns, wherein the original layout comprises one or more layout patterns; generating a layout forbidden region corresponding to the original layout based on the minimum distance between the figures and all the layout figures;

performing square gridding on the original layout, traversing each grid, judging the overlapping relation between each grid and the layout forbidden area, and marking the grids which are not overlapped with the layout forbidden area to generate one or more marked grids;

Filling each marking grid according to a preset filling rule to generate filling grids; and merging the filling grids with the original layout to generate a graph density optimization layout.

2. The layout generation method for optimizing a density distribution of a graphic according to claim 1, wherein the process of generating a layout exclusion area corresponding to the original layout based on a minimum pitch between the graphics and all the graphics of the layout comprises:

Generating an outer frame of a minimum area surrounding each layout graph according to the limit coordinate values of the upper, lower, left and right of the graph;

expanding the border outside each minimum area in a direction far away from the center of the corresponding layout graph by taking the minimum distance between the graphs as a distance so as to generate a forbidden area of the corresponding layout graph;

Merging the forbidden areas of all the layout graphs to generate a layout forbidden area.

3. The layout generating method for optimizing density distribution of a graphic according to claim 2, comprising: the minimum area outline includes: circular, oval, polygonal, irregular, or any combination thereof.

4. The layout generating method for optimizing density distribution of a graphic according to claim 1, wherein the process of filling each of the marker grids according to a preset filling rule to generate a filling grid comprises:

traversing each marking grid, performing the following operations: circularly traversing a preset direction set by taking the current marking grid as a center, and searching a layout figure closest to each preset direction; overlapping the searched layout graphs in a mode of aligning center points to generate graphs to be filled corresponding to the current marking grids; and scaling the graph to be filled so that the scaled graph to be filled does not exceed the grid boundary of the current marking grid, and filling the scaled graph to be filled into the current marking grid to generate a filling grid.

5. The layout generation method for optimizing a density distribution of a graphic according to claim 4, wherein the preset direction set comprises: upper, lower, left, right.

6. The layout generation method of claim 4, wherein the step of circularly traversing a set of predetermined directions, and searching for a layout pattern closest to the predetermined direction for each direction further comprises: if the layout pattern is not found in the current preset direction, skipping the current preset direction, and continuing to traverse the next preset direction in the preset direction set.

7. A layout generating apparatus for optimizing density distribution of a graphic, comprising:

A forbidden zone generation module: the method is used for obtaining an original layout and a minimum distance between patterns, wherein the original layout comprises one or more layout patterns; generating a layout forbidden region corresponding to the original layout based on the minimum distance between the figures and all the layout figures;

Grid marking module: the method comprises the steps of performing square gridding on the original layout, traversing each grid, judging the overlapping relation between each grid and the layout forbidden area, and marking grids which are not overlapped with the layout forbidden area to generate one or more marked grids;

And a filling optimization module: filling each marking grid according to a preset filling rule to generate filling grids; and merging the filling grids with the original layout to generate a graph density optimization layout.

8. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the layout generation method of optimizing a density distribution of a graphic according to any one of claims 1 to 6.

9. A computer program product comprising computer program code which, when run on a computer, causes the computer to implement a layout generation method of optimizing a density distribution of a graphic according to any of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the layout generation method of optimizing a density distribution of a graphic according to any one of claims 1 to 6.