CN118708529A - Electronic device, signal transmission device and control method - Google Patents

Abstract

The present disclosure provides an electronic device, a signal transmission device, and a control method, the electronic device including: the first interface is electrically connected with external equipment; a first processing unit configured to output a first data signal; and a buffer configured to control the first interface to output a first signal representative of the first data signal in response to receiving the first data signal, wherein if the external device outputs a second signal representative of the second data signal to the first interface, the buffer is capable of maintaining the first signal such that a receiving end of the external device receives information of the first data signal.

Description

Electronic device, signal transmission device and control method

Technical Field

The present disclosure relates to the field of computer technology, and in particular to an electronic device, a signal transmission device, and a control method.

Background Art

In the process of two-way communication between multiple electronic devices, when multiple electronic devices send data outward at the same time, the data sent by a certain electronic device may not arrive in time. If the data with priority is not transmitted to the corresponding receiving device in priority, it may affect the operation of multiple electronic devices.

Summary of the invention

The present disclosure provides an electronic device, a signal transmission device, and a control method.

According to one aspect of the present disclosure, an electronic device is provided, comprising: a first interface electrically connected to an external device; a first processing unit configured to output a first data signal; and a buffer configured to control the first interface to output a first signal representing the first data signal in response to receiving the first data signal, wherein if the external device outputs a second signal representing a second data signal to the first interface, the buffer is capable of maintaining the first signal so that a receiving end of the external device receives information of the first data signal.

According to an embodiment of the present disclosure, the buffer is configured to: in response to receiving a first data signal, control the level of the first signal to be in the same state as the level of the first data signal; and in response to not receiving the first data signal, switch to a high-impedance state to receive a second signal through the first interface.

According to an embodiment of the present disclosure, the buffer includes: a first input terminal, configured to receive an enable signal from a first processing unit; a second input terminal; and a first output terminal; wherein the buffer is configured to, in response to the level of the enable signal being at a first level, control the first output terminal to output a first signal based on a first data signal received at the second input terminal, wherein the level of the first data signal is in the same state as the level of the first signal; and in response to the level of the enable signal being at a second level, control the first output terminal to be in a high-impedance state to receive a second signal through the first interface.

According to an embodiment of the present disclosure, the first processing unit includes: a second output terminal; a third output terminal; and a third input terminal, which is electrically connected to the first interface; wherein the first processing unit is configured to output a first data signal to the buffer through the second output terminal during a data sending phase, and output an enable signal having a first level to the buffer through the third output terminal; and to output a disable signal having a second level to the buffer through the third output terminal during a data receiving phase, and receive a second signal through the third input terminal.

According to an embodiment of the present disclosure, the electronic device further includes: a switching unit configured to perform level switching on the first data signal and level switching on the second signal.

According to an embodiment of the present disclosure, the switching unit is electrically connected to the first interface, and the switching unit is configured to receive the second signal.

According to an embodiment of the present disclosure, the electronic device performs single bus communication with an external device through the first interface.

Another aspect of the present disclosure provides a signal transmission device, including: an external device; and the electronic device provided by an embodiment of the present disclosure, which is connected to the external device via a single bus communication.

According to an embodiment of the present disclosure, the external device includes: a second interface electrically connected to the first interface, the second interface being configured to receive a first signal; a second processing unit; and a control unit, configured to control the second interface to output a second signal representing the second data signal if the second processing unit outputs a second data signal; and to control a receiving end of the second processing unit to receive a third signal if the first interface outputs a first signal, the third signal and the first signal both representing information of the first data signal.

Another aspect of the present disclosure provides a control method, including: a buffer receives a first data signal; outputs a first signal representing the first data signal to an external device through a first interface connected to the buffer; if a second interface of the external device outputs a second signal representing the second data signal to the first interface, the first signal is maintained through the buffer so that the second interface of the external device receives information of the first data signal, and the first interface is connected to the second interface.

It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG1 is a schematic diagram of an application scenario of an electronic device according to an embodiment of the present disclosure;

FIG2 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure;

FIG3 is a schematic structural diagram of an electronic device according to another embodiment of the present disclosure;

FIG4 is a schematic structural diagram of an electronic device according to another embodiment of the present disclosure;

FIG5A is a communication diagram of an electronic device according to an embodiment of the present disclosure;

FIG5B is a schematic diagram of signals at a receiving end and a transmitting end of an electronic device according to an embodiment of the present disclosure.

FIG6 is a structural block diagram of a signal transmission device according to an embodiment of the present disclosure;

FIG7 is a structural block diagram of an external device according to an embodiment of the present disclosure; and

FIG. 8 is a flow chart of a control method for implementing an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure and application of the data involved (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good morals.

FIG. 1 is a schematic diagram of an application scenario of an electronic device according to an embodiment of the present disclosure.

As shown in FIG1 , the application scenario 100 according to this embodiment may include a first device 110 and a second device 120. Bidirectional transmission of signals may be achieved between the first device 110 and the second device 120. For example, the first device 110 includes a transmitting end TX1 and a receiving end RX1, and the second device 120 includes a transmitting end TX2 and a receiving end RX2. The first device 110 may send a signal to the second device 120 via the transmitting end TX1, and the second device 120 may receive the signal via the receiving end RX2. The second device 120 may send a signal to the first device 110 via the transmitting end TX2, and the first device 110 may receive the signal via the receiving end RX1.

For example, the first device 110 may be a tablet computer, a computer host, etc., and the second device 120 may be an external device such as a keyboard, a touch screen, an electronic pen, etc. The first device 110 may be a control terminal, and the second device 120 may be a controlled terminal. The first device 110 may send a control instruction to the second device 120.

The first device 110 and the second device 120 communicate via a single bus. When the first device 110 and the second device 120 transmit data to each other at the same time, the data sent by the first device 110 and the second device 120 may occupy the bus channel at the same time, causing the second device 120, as the controlled end, to be unable to receive data from the first device 110, the controlling end, in a timely manner, thereby causing a delay in receiving control instructions and causing operation errors and other problems.

For example, an Over-the-Air Technology (OTA) upgrade requires the first device 110 to send an installation package for the second device 120 to the second device 120. When a key or touch operation is continuously performed on the second device 120, the second device 120 will continue to send data to the first device 110, causing the process of the first device 110 sending a data packet to be interrupted by the data sent from the second device 120, and the OTA upgrade cannot be performed.

For example, when the second device 120 is continuously pressed or touched, if the first device 110 sends an indicator light adjustment instruction to the second device 120, due to the continuous operation performed by the second device 120, the adjustment instruction cannot be received in time to change the on/off status of the indicator light of the second device 120.

For example, when the second device 120 is continuously operated by a key or touch, if the first device 110 changes its operating state (such as the tablet computer turns off the screen), it sends a sleep instruction to the second device 120. Due to the continuous operation of the second device 120, the sleep instruction cannot be received in time, resulting in increased power consumption.

For example, when a key or touch operation is continuously performed on the second device 120 , if the first device 110 sends a disabling instruction to the second device 120 , the disabling instruction cannot be sent due to the continuous operation performed by the second device 120 .

In view of the above problems, the present disclosure provides an electronic device which, as a control end, can ensure that the sent data is preferentially transmitted to the external device as the controlled end, thereby ensuring that the data sent by the controlled end will not affect the timely transmission of the control end data.

The electronic device provided by the present disclosure is described in detail below in conjunction with FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5A and FIG. 5B .

FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

As shown in FIG. 2 , the electronic device 210 of this embodiment may include a first interface 211 , a first processing unit 212 , and a buffer 213 .

In an embodiment of the present disclosure, the electronic device 210 is electrically connected to an external device via a first interface 211. The first processing unit 212 is configured to output a first data signal. The buffer 213 is configured to control the first interface to output a first signal representing the first data signal in response to receiving the first data signal. If the external device outputs a second signal representing a second data signal to the first interface, the buffer can maintain the first signal so that the receiving end of the external device receives information of the first data signal.

In an embodiment of the present disclosure, the electronic device 210 may be the first device 110 shown in FIG. 1 , and the external device may be the second device 120 shown in FIG. 1 .

In an embodiment of the present disclosure, the first interface 211 is electrically connected to an external device. The first interface 211 is used to send a first signal generated by the electronic device 210 to the external device, and the first interface 211 also receives a second signal sent by the external device.

The first processing unit 212 is used to generate a first data signal capable of controlling an external device, and send the first data signal to the buffer 213. The first processing unit 212 may be a CPU processor such as an application processor (AP), a coprocessor (CP), or a digital signal processing technology (DSP).

The buffer 213 converts the first data signal generated by the first processing unit 212 in the electronic device 210 into a first signal that can be processed by an external device, and the data content represented by the first signal is consistent with that represented by the first data signal. For example, the first data signal can be a logical digital signal, and the first data signal includes information of 0 and 1. When the first data signal represents the instruction "01", the first signal also represents the instruction "01". For example, "0" and "1" can be represented by the low level and high level of the first data signal and the first signal, respectively. The low level and the high level are relative, for example, the level of the first data signal switches between two levels, and the level with a larger voltage value in the two levels is a high level, and the level with a smaller voltage value is a low level. It should be noted that the value of the high level in the first signal and the first data signal can be the same or different. Correspondingly, the value of the low level in the first signal and the first data signal can be the same or different.

When the first interface 211 receives a second signal sent by an external device and the first processing unit 212 of the electronic device 210 sends a first data signal, the buffer 213 is able to maintain the output of the first signal so that the external device can receive the first signal, thereby ensuring that the receiving end of the external device can receive the information conveyed by the first data signal without being interrupted by the second signal.

According to the embodiment of the present disclosure, the electronic device 210 performs single bus communication with an external device through the first interface 211 .

Single bus communication means that data transmission and command control between the electronic device and the external device are completed through one data line. When there is bidirectional data transmission between the electronic device and the external device, the buffer 213 can maintain the output of the first signal through the first interface 211. In this case, the external device can execute the corresponding command in time based on the received first signal without being interrupted by the transmission of the second signal.

In the embodiment of the present disclosure, the first signal output by the first interface 211 is maintained by the buffer 213, so that even when the external device and the electronic device 210 send data at the same time, the external device can receive the first signal in time, thereby achieving the priority output of the first data signal. In addition, at the hardware level, there is no need to add an additional control unit (such as a microcontroller unit (MCU) etc.) to the electronic device 210, which simplifies the hardware structure of the electronic device 210 and reduces the computing consumption of the electronic device 210.

FIG. 3 is a schematic structural diagram of an electronic device according to another embodiment of the present disclosure.

As shown in Fig. 3, the electronic device 310 includes a first interface 311, a first processing unit 312 and a buffer 313. The external device 320 includes a transmitting end TX2 and a receiving end RX2.

In the embodiment of the present disclosure, the first interface 311 , the first processing unit 312 and the buffer 313 are similar in structure to the first interface 211 , the first processing unit 212 and the buffer 213 described above, and are not described again for the sake of brevity.

In an embodiment of the present disclosure, the first data signal data1 generated by the first processing unit 312 is sent to the buffer 313, and the first signal S1 representing the same data information as the first data signal data1 is output via the buffer 313. The first signal S1 is sent to the receiving end RX2 of the external device 320 through the first interface 311. The second signal S2 output by the transmitting end TX2 of the external device 320 is sent to the first processing unit 312 of the electronic device through the first interface 311.

In an embodiment of the present disclosure, the buffer 313 is configured to: in response to receiving the first data signal data1, control the level of the first signal S1 to be in the same state as the level of the first data signal data1; and in response to not receiving the first data signal data1, switch to a high-impedance state to receive the second signal S2 through the first interface 311.

For example, the first signal and the first data signal may both be logic signals consisting of 0 and 1. The levels of the first signal and the first data signal are in the same state at the same time, and the level changes are consistent. For example, the level change of the first data signal is "high-low-high" to represent the data "101", and the level change of the first signal is also "high-low-high" to represent the data "101".

When the buffer 313 receives the first data signal data1 sent by the first processing unit 312, it outputs the first signal S1 consistent with the level state of the first data signal data1. When the buffer 313 does not receive the first data signal data1 sent by the first processing unit 312, the buffer 313 switches to a high-impedance state so that the first interface 311 receives the second signal S2 sent by the external device and transmits it to the first processing unit 312. The high-impedance state means that the buffer 313 has a relatively higher impedance than other nodes in the circuit, and the circuit of the buffer 313 can be regarded as an open circuit state. The fact that the buffer 313 does not receive the first data signal can indicate that the electronic device 210 does not send data to the outside at this time, and the buffer 313 switches to a high-impedance state at this time. The high-impedance state of the buffer 313 will not affect the first interface 311 receiving the second signal S2.

According to an embodiment of the present disclosure, when the first processing unit 312 sends data to the outside, regardless of whether the external device 320 sends the second signal S2 at this time, the buffer 312 maintains the level change of the first signal S1 of the first interface 311, ensuring that the receiving end RX2 of the external device 320 receives the first signal S1. When the first processing unit 312 does not send data to the outside, if the transmitting end TX2 of the external device 320 sends the second signal S2 to the electronic device 310, the buffer 313 can be in a high-impedance state, so that the first interface 311 directly sends the second signal S2 to the first processing unit 312 after receiving it.

The setting of the buffer 312 can separate the signal transmission process of the electronic device 310 from the signal reception process, and by maintaining the level of the first signal S1 of the first interface 311, the signal transmission of the electronic device 310 has a higher priority. When the electronic device 210 does not send data, the first processing unit 312 directly receives the signal from the external device 320 through the first interface 311, thereby realizing the priority control of the electronic device 310 over the external device 320, and avoiding the control function of the electronic device being affected by the data transmission of the external device.

FIG. 4 is a schematic structural diagram of an electronic device according to another embodiment of the present disclosure.

As shown in FIG. 4 , the electronic device 410 includes a first interface 411 , a first processing unit 412 , a buffer 413 , and a switching unit 414 .

In the embodiment of the present disclosure, the first interface 411 , the first processing unit 412 and the buffer 413 are similar in structure to the first interface 211 , the first processing unit 212 and the buffer 213 described above, and are not described again for the sake of brevity.

In an embodiment of the present disclosure, the switching unit 414 is configured to perform level switching on the first data signal and to perform level switching on the second signal.

In the embodiment of the present disclosure, the operating voltage of the electronic device 410 and the external device may be different, and the voltage of the high level in the signal processed by each is also different. For example, the high level of the signal in the electronic device 410 can be 1.8V, and the high level of the signal in the external device can be 3.3V. Therefore, in order to ensure that the data signal transmitted between the electronic device 410 and the external device can be correctly recognized by the other party, the first data signal sent by the first processing unit 412 and the second signal sent by the external device need to be level-switched by the switching unit 414 so that the level of the switched signal is adapted to the receiving party.

For example, when the switching unit 414 receives the first data signal sent by the first processing unit 412, it is necessary to switch the high level in the first data signal from 1.8V to 3.3V, and obtain a first signal with the same level state and different working voltage, that is, 1.8V and 3.3V are both relatively high levels. The switching unit 414 transmits the first signal to the buffer 413, and then sends it to the external device via the first interface 411.

For example, when the switching unit 414 receives the second signal sent by the first interface 411 , it is necessary to switch the high level in the second signal from 3.3V to 1.8V, and send the converted second signal to the first processing unit 412 .

In an embodiment of the present disclosure, the switch unit 414 is electrically connected to the first interface 411 , and the switch unit 414 is configured to receive a second signal.

In the embodiment of the present disclosure, the first data signal generated by the first processing unit 412 is transmitted to the external device via the switching unit 414, the buffer 413 and the first interface 411. When the first interface 411 receives the second signal sent by the external device, the second signal is directly sent to the switching unit 414 through the first interface 411, and is transmitted to the first processing unit 414 after being converted by the switching unit 414.

According to an embodiment of the present disclosure, the introduction of a switching unit can switch the operating voltages of the first data signal and the second signal, and can maintain the separation of the signal sending process and the signal receiving process in the electronic device 410, thereby ensuring the priority sending of signals in the electronic device while simplifying the structure.

FIG. 5A is a schematic diagram of communication of an electronic device according to an embodiment of the present disclosure.

As shown in FIG5 , the electronic device 510 includes a first interface 511 , a first processing unit 512 , a buffer 513 , and a switching unit 514 . The external device 520 includes a second interface 521 , a second processing unit 522 , and a control unit 523 .

In an embodiment of the present disclosure, the electronic device 510 and the external device 520 are communicatively connected via a first interface 511 and a second interface 521. For example, the first interface 511 and the second interface 521 may be connected in the form of pogo pins.

In the embodiment of the present disclosure, the first interface 511 is electrically connected to the buffer 513 and the switching unit 514 respectively, the buffer 513 is electrically connected to the switching unit 514, and the switching unit 514 is electrically connected to the first processing unit 512.

In an embodiment of the present disclosure, the second interface 521 is electrically connected to the control unit 523, and the control unit 523 is electrically connected to the second processing unit 522. The control unit 523 includes a first resistor R1, a second resistor R2, and a third resistor R3. The first end of the first resistor R1 is electrically connected to the second interface 521, the second end of the first resistor R1 is grounded, the first end of the second resistor R2 is electrically connected to the second interface 521, the second end of the second resistor R2 is electrically connected to the transmitting end TX2 of the control unit 522, the first end of the third resistor R3 is electrically connected to the second interface 521, and the second end of the third resistor R3 is electrically connected to the receiving end RX2 of the second processing unit 522.

In the embodiment of the present disclosure, the first processing unit 512 includes: a second output terminal TX1, a third output terminal EN and a third input terminal RX1. The third input terminal RX1 is electrically connected to the first interface 511 through a switching unit 514. For example, the second output terminal TX1 and the third input terminal RX1 can be a universal asynchronous receiver/transmitter (uart) interface.

In the embodiment of the present disclosure, in the data transmission stage, the first processing unit 512 outputs the first data signal data1 to the buffer 513 through the second output terminal TX1, and outputs the enable signal TX-EN with a first level to the buffer 513 through the third output terminal EN. In the data reception stage, the first processing unit 512 outputs a disable signal with a second level to the buffer 513 through the third output terminal RX1, and receives the second signal S2 through the third input terminal RX1.

For example, the enable signal TX-EN with a first level is used to control the enabling of the buffer 513 , and the enable signal with a second level is a disable signal, which is used to control the disabling of the buffer 513 .

For example, in the transmission stage of the first data signal data1, the first data signal data1 is output to the buffer 513 through the second output terminal TX1, and the enable signal TX-EN with a first level is output to the buffer 513 through the third output terminal EN. Under the control of the enable signal TX-EN, the first data signal data1 is converted into the first signal S1 through the switching unit 514 and then sent to the first interface 511 through the buffer 513. In the reception stage of the second signal S2, a disable signal with a second level is output to the buffer 513 through the third output terminal RX1, and the buffer 513 is controlled to be in a high impedance state, so as to obtain the second signal S2 sent from the first interface 511 to the switching unit, and under the action of the switching unit 514, the converted second signal S2 is sent to the receiving terminal RX1 of the first processing unit 512.

According to the embodiment of the present disclosure, the buffer 513 includes: a first input terminal OE, a second input terminal A, and a first output terminal Y. The first input terminal OE receives an enable signal TX-EN from the first processing unit 512 .

In response to the level of the enable signal TX-EN being at the first level, the buffer 513 controls the first output terminal Y to output the first signal S1 based on the first data signal data1 received at the second input terminal A, and the level of the first data signal data1 is in the same state as the level of the first signal S1. In response to the level of the enable signal TX-EN being at the second level, the buffer 513 controls the first output terminal Y to be in a high-impedance state, so as to receive the second signal S2 through the first interface 511.

For example, when the buffer 513 receives the enable signal TX-EN of the first level, based on the first data signal data1 received by the second input terminal A, the first output terminal Y is controlled to output the first signal S1, and the level of the first data signal data1 is in the same state as the level of the first signal S1, for example, both are high level, or both are low level. When the buffer 513 receives the enable signal TX-EN of the second level, the first output terminal Y is controlled to be in a high impedance state. The buffer 513 in the high impedance state does not affect the level of the first interface 511, so that the electronic device 510 can receive the second signal S2 through the first interface 511.

In the embodiments of the present disclosure, data transmission between an electronic device and an external device can be divided into the following three situations. The following is a schematic description of the first resistor R1, the second resistor R2, the third resistor R3, the first data signal data1, the second data signal data2, the first signal S1, the second signal S2 and the third signal S3. For example, the resistance value of the first resistor R1 is 100KΩ, the resistance value of the second resistor R2 is 1KΩ, the resistance value of the third resistor R3 is 100Ω, the high level of the first data signal data1 is 3.3V, the low level is 0V, and the high level of the second data signal data2 is 1.8V, and the low level is 0V.

For example, the electronic device 510 sends a first data signal data1 to the external device 520, and the external device 520 does not send any data. In this case, the second resistor R2 and the third resistor R3 in the control unit 523 can be considered to be in an open circuit state.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 3.3V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 1.8V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 1.8V. The voltages at both ends of the first resistor R1 are 1.8V and 0V respectively. At this time, the level of the third signal S3 received by the receiving terminal RX2 is 1.8V.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 0V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 0V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 0V. The voltages at both ends of the first resistor R1 are 0V and 0V respectively. At this time, the level of the third signal S3 received by the receiving terminal RX2 is 0V.

Therefore, when the electronic device 510 sends the first data signal data1 to the external device 520 and the external device 520 does not send data, the third signal S3 received by the receiving end RX2 of the external device 520 is consistent with the data information represented by the first data signal data1.

For example, the external device 520 sends data to the electronic device 510, but the electronic device 510 does not send data. In this case, the third resistor R3 in the control unit 523 can be regarded as being in an open circuit state.

The third output terminal EN outputs the enable signal TX-EN with a low level, and the buffer 513 is in a high impedance state based on the enable signal TX-EN with a low level received by the first input terminal OE.

The second processing unit 522 sends a second data signal data2 with 1.8V through the transmitting terminal TX2. The first resistor R1 and the second resistor R2 are connected in series and divide the 1.8V voltage. At this time, the second signal S2 of the second interface 521 is 1.78V. The first interface 511 sends the second signal S2 with 1.78V to the switching unit 514, and the switching unit 514 can switch 1.78V to 3.3V. RX1 of the first processing unit 512 receives the second signal S2 with 3.3V.

The second processing unit 522 sends a second data signal data2 with 0V through the transmitting terminal TX2. The first resistor R1 and the second resistor R2 are connected in series and divide the 0V voltage. At this time, the second signal S2 of the second interface 521 is 0V. The first interface 511 sends the second signal S2 with 0V to the switching unit 514, and the switching unit 514 can send the second signal S2 with 0V to the first processing unit 512. RX1 of the first processing unit 512 receives the second signal S2 with 3.3V.

Therefore, when the external device 520 sends data to the electronic device 510 and the electronic device 510 does not send data, the second signal S2 received by the receiving end RX2 of the electronic device 510 is consistent with the data information represented by the second data signal data2.

For example, when the electronic device 510 sends a high level signal, the external device 520 also sends a high level signal.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 3.3V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 1.8V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 1.8V. The second processing unit 522 sends a second data signal data2 with 1.8V through the transmitting terminal TX2. The first resistor R1 and the second resistor R2 are connected in series and divide the 1.8V voltage. At this time, the second signal S2 of the second interface 521 is 1.78V.

The first interface 511 is electrically connected to the second interface 521 , and the voltage levels of the first interface 511 and the second interface 521 are consistent, both of which are 1.8 V. At this time, the voltage level of the third signal S3 received by the receiving end RX2 is 1.8V.

For example, when the electronic device 510 sends a low level signal, the external device 520 also sends a low level signal.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 0V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 0V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 0V. The second processing unit 522 sends a second data signal data2 with 0V through the transmitting terminal TX2. The first resistor R1 and the second resistor R2 are connected in series and divide the 0V voltage. At this time, the second signal S2 of the second interface 521 is 0V.

The first interface 511 is electrically connected to the second interface 521, and the voltage levels of the first interface 511 and the second interface 521 are consistent, both of which are 0V. At this time, the voltage level of the third signal S3 received by the receiving end RX2 is 0V.

For example, when the electronic device 510 sends a high level signal, the external device 520 sends a low level signal.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 3.3V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 1.8V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 1.8V. The second processing unit 522 sends a second data signal data2 with 0V through the transmitting terminal TX2. The first resistor R1 and the second resistor R2 are connected in parallel, and the first end of the first resistor R1 and the first end of the second resistor R2 both receive the first signal S1 with 1.8V from the first interface 511 through the second interface 521. At this time, the level of the third signal S3 received by the receiving terminal RX2 is 1.8V.

For example, when the electronic device 510 sends a low level signal, the external device also sends a low level signal.

The third output terminal EN outputs an enable signal TX-EN with a high level, and the second output terminal TX1 outputs a first data signal data1 with 0V. The first data signal data1 is provided to the second input terminal A through the switching unit 514. The buffer 513 controls the voltage of the second input terminal A to be 0V based on the high level enable signal TX-EN received by the first input terminal OE. At this time, the voltage of the first signal S1 output by the first output terminal Y is also 0V, and the first interface 511 is in a grounded state. The second processing unit 522 sends a second data signal data2 with 1.8V through the transmitting terminal TX2. The first resistor R1 and the second resistor R are connected in series and divide the 1.8V voltage. At this time, the second signal S2 of the second interface 521 is 1.78V.

The first interface 511 is electrically connected to the second interface 521. Since the first interface 511 is in a grounded state, the level of the second interface 521 is pulled down to 0V. At this time, the level of the third signal S3 received by the receiving end RX2 is 0V.

Therefore, when the electronic device 510 sends the first data signal data1 to the external device 520 and the external device 520 sends data to the electronic device 510 , the third signal S3 received by the receiving end RX2 of the external device 520 is consistent with the data information represented by the first data signal data1 .

FIG5B is a schematic diagram of signals at a receiving end and a transmitting end of an electronic device according to an embodiment of the present disclosure.

As shown in Figure 5B, KP-TX represents the level change of the second data signal of the transmitting end of the external device, POGO-DAT represents the level change of the first interface, AP-RX represents the level change of the receiving end of the electronic device, and AP-TX represents the level change of the first data signal sent by the transmitting end of the electronic device.

When the first data signal sent by the transmitting end of the electronic device sends a data signal, no matter the level of the second data signal of the transmitting end of the external device is high or low, the state clock of the level of the first interface is consistent with the level state of the first data signal. For example, when AP-TX is high, POGO-DAT is high. When AP-TX is low, POGO-DAT is low.

FIG. 6 is a structural block diagram of a signal transmission device according to an embodiment of the present disclosure.

As shown in Fig. 6, the signal transmission device 600 includes an electronic device 610 and an external device 620. The electronic device 610 and the external device 620 are connected to each other by a single bus.

The structures of the electronic device 610 and the external device 620 are similar to those of the electronic device 510 and the external device 520 described above, and are not described again for the sake of brevity.

FIG. 7 is a structural block diagram of an external device according to an embodiment of the present disclosure.

As shown in FIG. 7 , the external device 720 includes a second interface 721 , a second processing unit 722 , and a control unit 723 .

According to an embodiment of the present disclosure, the second interface 721 is electrically connected to the first interface of the electronic device, and the second interface 721 is configured to receive a first signal sent by the electronic device. The control unit 723 is configured to control the second interface 721 to output a second signal representing the second data signal if the second processing unit 722 outputs a second data signal. If the first interface outputs a first signal, the receiving end of the second processing unit 722 is controlled to receive a third signal, and the third signal and the first signal both represent information of the first data signal. The level change of the third signal is consistent with that of the first signal, and the voltage of the high level of the third signal is different from that of the first signal.

The second interface 721 , the second processing unit 722 and the control unit 723 are similar in structure to the second interface 521 , the second processing unit 522 and the control unit 523 described above, and are not described again for the sake of brevity.

FIG. 8 is a flow chart of a control method for implementing an embodiment of the present disclosure.

As shown in FIG. 8 , the control method of this embodiment includes operations S801 - S803 .

In operation S801 , a buffer receives a first data signal.

In operation S802, a first signal representing a first data signal is output to an external device through a first interface connected to a buffer.

In operation S803, if the second interface of the external device outputs a second signal representing a second data signal to the first interface, the first signal is maintained by the buffer so that the second interface of the external device receives information of the first data signal, and the first interface is connected to the second interface.

It should be noted that the collection, storage, use, processing, transmission, provision, disclosure and application of user personal information involved in the technical solution of this disclosure are in compliance with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals. In the technical solution of this disclosure, the user's authorization or consent is obtained before obtaining or collecting user personal information.

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and/or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions/operations specified in the flow chart and/or block diagram. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. Among them, the server may be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or "VPS" for short). The server may also be a server of a distributed system, or a server combined with a blockchain.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims (10)

1. An electronic device, comprising:

the first interface is electrically connected with external equipment;

a first processing unit configured to output a first data signal;

And a buffer configured to control the first interface to output a first signal representative of the first data signal in response to receiving the first data signal, wherein the buffer is capable of maintaining the first signal if the external device outputs a second signal representative of a second data signal to the first interface so that a receiving end of the external device receives information of the first data signal.

2. The electronic device of claim 1, the buffer configured to:

Controlling a level of the first signal to be in a same state as a level of the first data signal in response to receiving the first data signal; and

And switching to a high-impedance state to receive the second signal through the first interface in response to not receiving the first data signal.

3. The electronic device of claim 1, the buffer comprising:

a first input configured to receive an enable signal from the first processing unit;

A second input terminal; and

A first output terminal;

wherein the buffer is configured to control the first output terminal to output the first signal based on the first data signal received by the second input terminal in response to the level of the enable signal being a first level, the level of the first data signal being in the same state as the level of the first signal; and responding to the level of the enabling signal to be a second level, and controlling the first output end to be in a high-resistance state so as to receive the second signal through the first interface.

4. The electronic device of claim 1, the first processing unit comprising:

a second output terminal;

A third output; and

The third input end is electrically connected with the first interface;

Wherein the first processing unit is configured to output the first data signal to the buffer through the second output terminal and output an enable signal having a first level to the buffer through the third output terminal in a data transmission stage; in the data receiving stage, a disable signal with a second level is output to the buffer through the third output terminal, and the second signal is received through the third input terminal.

5. The electronic device of claim 1, further comprising:

And a switching unit configured to level-switch the first data signal and level-switch the second signal.

6. The electronic device of claim 5, the switching unit electrically connected with the first interface, the switching unit configured to receive the second signal.

7. The electronic device of any of claims 1-6, the electronic device in single bus communication with the external device through the first interface.

8. A signal transmission apparatus comprising:

An external device; and

The electronic device of any of claims 1-7, communicatively coupled to the external device single bus.

9. The signal transmission device of claim 8, the external device comprising:

a second interface electrically connected to the first interface, the second interface configured to receive the first signal;

A second processing unit; and

A control unit configured to control the second interface to output a second signal representative of the second data signal if the second processing unit outputs the second data signal; and if the first interface outputs the first signal, controlling a receiving end of the second processing unit to receive a third signal, wherein the third signal and the first signal both represent information of the first data signal.

10. A control method, comprising:

the buffer receives a first data signal;

Outputting a first signal representing the first data signal to an external device through a first interface connected to the buffer;

And if the second interface of the external device outputs a second signal representing a second data signal to the first interface, maintaining the first signal through the buffer so that the second interface of the external device receives the information of the first data signal, wherein the first interface is connected with the second interface.