CN118695588A - Semiconductor devices - Google Patents

Abstract

A semiconductor device includes a substrate, a bit line extending in a first horizontal direction on the substrate, a first mold layer on the bit line, a channel layer on the bit line, one or more word lines on the sidewall of the channel layer and extending in a second horizontal direction, and a gate insulating layer between the word line and the channel layer, wherein the first mold layer defines a mold opening that exposes a portion of an upper surface of the bit line and extends in a second horizontal direction intersecting the first horizontal direction, wherein the channel layer includes a first oxide semiconductor layer, a second oxide semiconductor layer, and an auxiliary channel layer between the first oxide semiconductor layer and the second oxide semiconductor layer.

Description

Semiconductor devices

Technical Field

The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a channel structure.

Background Art

Due to the development of electronic technology, scaling of semiconductor devices (ie, reduction in size of semiconductor devices) is rapidly progressing, and thus, transistors configured with a channel layer using an oxide semiconductor material to reduce leakage current through a channel region have been proposed.

Summary of the invention

The present disclosure provides a semiconductor device including a channel layer, the channel layer including a first oxide semiconductor layer, a second oxide semiconductor layer, and an auxiliary channel layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer.

Furthermore, the present disclosure provides a semiconductor device including an auxiliary channel layer having a thickness less than 1 nm.

Furthermore, the present disclosure provides a semiconductor device including a first mold layer forming an oxygen tunneling structure in which silicon oxide and silicon nitride are sequentially stacked.

According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line extending in a first horizontal direction on the substrate; a first mold layer on the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line, and wherein the first mold layer extends in a second horizontal direction intersecting the first horizontal direction; a channel layer on the bit line; one or more word lines on sidewalls of the channel layer and extending in a second horizontal direction; and a gate insulating layer between the one or more word lines and the channel layer, wherein the channel layer includes a first oxide semiconductor layer, a second oxide semiconductor layer, and an auxiliary channel layer between the first oxide semiconductor layer and the second oxide semiconductor layer.

According to another aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line extending in a first horizontal direction on the substrate; a first mold layer on the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line; a channel layer on an inner wall of the mold opening, wherein the channel layer includes a first oxide semiconductor layer on the inner wall of the mold opening or on the bit line, an auxiliary channel layer on the first oxide semiconductor layer, and a second oxide semiconductor layer on the auxiliary channel layer; a word line on a sidewall of the channel layer, wherein the word line extends in a second horizontal direction intersecting the first horizontal direction; and a gate insulating layer between the word line and the channel layer, wherein the auxiliary channel layer includes at least one of a two-dimensional (2D) material or indium oxide (In ₂ O ₃ ).

According to another aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line extending in a first horizontal direction on the substrate; a first mold layer on the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line, wherein the first mold layer includes a lower first insulating layer, a second insulating layer on the lower first insulating layer, and an upper first insulating layer on the second insulating layer; a channel layer on an inner wall of the mold opening, wherein the channel layer includes a first oxide semiconductor layer on the inner wall of the mold opening or on the bit line, an auxiliary channel layer on the first oxide semiconductor layer, and a second oxide semiconductor layer on the auxiliary channel layer; a word line on a sidewall of the channel layer, wherein the word line extends in a second horizontal direction intersecting the first horizontal direction; a gate insulating layer between the word line and the channel layer; a capacitor structure on the first mold layer; and a contact layer between the channel layer and the capacitor structure, wherein each of the lower first insulating layer and the upper first insulating layer includes silicon nitride, wherein the second insulating layer _includes silicon oxide, and wherein the auxiliary channel layer includes at least one of a two-dimensional (2D) material or indium oxide ( _In2O3 ).

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a layout diagram of a semiconductor device according to an example embodiment of the present disclosure;

FIG2 is an enlarged layout diagram of the cell array region in FIG1;

FIG3 is a cross-sectional view taken along line A1-A1' in FIG2;

FIG4 is an enlarged view of the area CX1 in FIG3; and

5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 14 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are represented by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively displayed for better understanding and ease of description.

It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on another element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms such as "below", "below", "lower", "above", "upper", etc. can be used herein to describe the relationship between an element or feature as shown in the figure and another one or more elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below" can cover both upper and lower orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

In addition, unless explicitly described to the contrary, the word "comprises" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. As used herein, the phrase "at least one of A, B, and C" means a logical (A or B or C), using a non-exclusive logical OR, and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C." As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when used herein, the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, and/or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and/or groups thereof. The term "and/or" includes any and all combinations of one or more of the associated listed items. As used herein, "element A is at the same level as element B" means that at least one surface of element A is coplanar with at least one surface of element B. The term "connected" may be used herein to refer to physical and/or electrical connections, and may refer to direct or indirect physical and/or electrical connections. The phrase "element A fills element B" may mean that element A is at least partially within the space defined by element B.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof are omitted.

FIG. 1 is a layout diagram of a semiconductor device 100 according to an embodiment of the present disclosure.

1 , a semiconductor device 100 may include a substrate 110 including a cell array area MCA and a peripheral circuit area PCA. In some embodiments, the cell array area MCA may include a memory cell area of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may include a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA may include a peripheral circuit transistor (not shown) for transmitting signals and/or power to a memory cell array included in the cell array area MCA. In an embodiment, the peripheral circuit transistor (not shown) may constitute various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input/output circuit.

FIG. 2 is an enlarged layout diagram of the cell array area MCA in FIG. 1 .

2 , a plurality of bit lines BL extending in a first horizontal direction (X direction) and a plurality of word lines WL extending in a second horizontal direction (Y direction) may be arranged on a cell array area MCA of a substrate 110. A plurality of cell transistors CTR may be arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. A plurality of cell capacitors CAP may be arranged on the plurality of cell transistors CTR, respectively.

The plurality of word lines WL may include a first word line WL1 and a second word line WL2 arranged in a first horizontal direction (X direction), and the plurality of cell transistors CTR may include a first cell transistor CTR1 and a second cell transistor CTR2 arranged in the first horizontal direction (X direction). The first cell transistor CTR1 may be arranged on the first word line WL1, and the second cell transistor CTR2 may be arranged on the second word line WL2.

The first cell transistor CTR1 and the second cell transistor CTR2 may have a symmetrical structure with respect to each other. For example, the first cell transistor CTR1 and the second cell transistor CTR2 may have a symmetrical structure with respect to a center line between the first cell transistor CTR1 and the second cell transistor CTR2, which extends in the second horizontal direction (Y direction).

In some embodiments, the width of the plurality of word lines WL and the bit lines BL may be 1F, the pitch (i.e., the sum of the width and the interval) of the plurality of word lines WL and the bit lines BL may be 2F, and the unit area for forming one cell transistor CTR may be 4F ^2. Therefore, since the cell transistor CTR may be a cross-point type having a relatively small unit area, the cell transistor CTR may be useful for improving the integration of the semiconductor device 100.

FIG. 3 is a cross-sectional view taken along line A1 - A1 ′ in FIG. 2 .

FIG. 4 is an enlarged view of the region CX1 in FIG. 3 .

As shown in FIG3 , the lower insulating layer 112 may be disposed on the substrate 110. The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one of germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphate (InP). In some embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. The lower insulating layer 112 may include an oxide layer, a nitride layer, or a combination thereof.

The bit line BL extending in the first horizontal direction (X direction) may be arranged on the lower insulating layer 112. In some embodiments, the bit line BL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. For example, the bit line BL may further include a conductive layer (not shown) and a conductive barrier layer (not shown) arranged on the upper and lower surfaces of the conductive layer. The bit line insulating layer (not shown) extending in the first horizontal direction (X direction) may be arranged on the sidewalls of the bit line BL. For example, the bit line insulating layer may be formed to have the same height as the bit line BL while filling the space between two adjacent bit lines BL.

The first mold layer 130 (shown in FIG. 6 ) may be arranged on the bit line BL and the bit line insulating layer. The first mold layer 130 may include a plurality of mold openings 130H (shown in FIG. 6 ). The plurality of mold openings 130H may include first sidewalls 130H1 and second sidewalls 130H2 opposite to each other. The upper surface of the bit line BL may be exposed to a bottom portion of each of the plurality of mold openings 130H.

The first mold layer 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. According to an embodiment, the first mold layer 130 may be formed into a multilayer structure. For example, the first mold layer 130 may include a lower first insulating layer 131A and an upper first insulating layer 131B and a second insulating layer 132. The lower first insulating layer 131A may be arranged on the bit line BL. The second insulating layer 132 may be arranged on the lower first insulating layer 131A. The upper first insulating layer 131B may be arranged on the second insulating layer 132.

In this case, the lower first insulating layer 131A and the upper first insulating layer 131B may include silicon nitride, and the second insulating layer 132 may include silicon oxide. In addition, the thickness of the second insulating layer 132 in the vertical direction (Z direction) may be greater than the thickness of the lower first insulating layer 131A in the vertical direction (Z direction) and the thickness of the upper first insulating layer 131B in the vertical direction (Z direction), but is not limited thereto.

The first mold layer 130 may be formed in a multi-layer structure in which silicon nitride, silicon oxide, and silicon nitride are sequentially stacked. The first mold layer 130 may have a multi-layer structure including silicon nitride and silicon oxide, and may form an oxygen tunneling structure.

By forming the first mold layer 130 into a multilayer structure (oxygen tunneling structure) including silicon oxide between silicon nitrides, the channel layer 140 can be passivated. Therefore, there can be an effect of shifting (e.g., increasing) the threshold voltage _Vth in the positive direction without reducing the resistance of the channel layer 140. In addition, by adjusting the annealing temperature, gas, or time of the first mold layer 130, the threshold voltage _Vth can be adjusted in the positive direction (e.g., the threshold voltage _Vth can be increased).

A plurality of channel layers 140 may be arranged on the inner wall of the plurality of mold openings 130H. Each of the plurality of channel layers 140 may include a first portion extending from the bottom of the plurality of mold openings 130H in a first horizontal direction (X direction), and a second portion connected to the first portion and arranged on the first sidewall 130H1 and the second sidewall 130H2 of the plurality of mold openings 130H. For example, each of the plurality of channel layers 140 may have a vertical cross section of a nonlinear shape (e.g., a U-shape).

The second portion of the plurality of channel layers 140 may include a first sidewall and a second sidewall opposite to each other. The first sidewall may be in contact with the gate insulating layer 150, and the second sidewall may be in contact with the first mold layer 130. In addition, each of the plurality of channel layers 140 may have an upper surface arranged at a level lower than that of the upper surface of the first mold layer 130 (for example, a distance between the upper surface of the first mold layer 130 and the substrate 110 in a vertical direction (Z direction) is greater than a distance between the upper surface of the channel layer 140 and the substrate 110 in a vertical direction (Z direction)).

In some embodiments, each of the plurality of channel layers 140 may include a first oxide semiconductor layer 141A, a second oxide semiconductor layer 141B, and an auxiliary channel layer 142. The channel layer 140 may be formed in a sandwich structure. For example, the auxiliary channel layer 142 may be arranged between the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B. For example, the first oxide semiconductor layer 141A may contact the upper surface of the bit line BL and the sidewalls 130H1 and 130H2 of the mold opening 130H. The auxiliary channel layer 142 may be formed on the first oxide semiconductor layer 141A, and the second oxide semiconductor layer 141B may be formed on the auxiliary channel layer 142.

In the present embodiment, each of the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B may include indium gallium zinc oxide (IGZO). The auxiliary channel layer 142 may include a two-dimensional (2D) material or indium oxide (In ₂ O ₃ ).

In this embodiment, the thickness of the auxiliary channel layer 142 may be less than 1 nm. The thickness of the channel layer 140 may be less than 10 nm. In addition, the thickness of the first oxide semiconductor layer 141A and the thickness of the second oxide semiconductor layer 141B may each be greater than the thickness of the auxiliary channel layer 142 .

As the thickness of the auxiliary channel layer 142 decreases, the threshold voltage _Vth of the transistor may increase. According to an embodiment, when the thickness of _the auxiliary channel layer 142 including indium oxide _In2O3 is less than 1 nm, the threshold voltage _Vth of the transistor may exceed 0 V. Therefore, by forming the auxiliary channel layer 142 between the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B, the semiconductor device 100 of the present disclosure may have an effect of adjusting the threshold voltage Vth to exceed 0 V.

In addition, by forming the auxiliary channel layer 142 between the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B, the semiconductor device 100 can have an effect of improving the on-current ( _Ion ). By forming the auxiliary channel layer 142 between the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B, the mobility of electrons can be improved and the on-current ( _Ion ) can be improved.

The gate insulating layer 150 and the word line WL may be sequentially arranged on the first sidewalls of the plurality of channel layers 140. For example, the gate insulating layer 150 may be conformally arranged on the upper surface of the first portion of the plurality of channel layers 140. In addition, the gate insulating layer 150 may be conformally arranged on the first sidewall of the second portion. The word line WL may be arranged on the first sidewall of the second portion of the plurality of channel layers 140. The gate insulating layer 150 may be between the word line WL and the channel layer 140.

The channel layer 140 having a U-shaped vertical cross section may be arranged in one mold opening 130H. Two word lines WL may be spaced apart from each other on the channel layer 140 in the first horizontal direction (X direction) inside the one mold opening 130H. The word lines WL may include a first word line WL1 and a second word line WL2 spaced apart from the first word line WL1 in the first horizontal direction (X direction). For example, the first word line WL1 may be arranged to face one second portion of the channel layer 140, and the second word line WL2 may be arranged to face another second portion of the channel layer 140.

For example, the first word line WL1, one second portion of the channel layer 140, and the gate insulating layer 150 therebetween may constitute a first cell transistor CTR1. The second word line WL2, another second portion of the channel layer 140, and the gate insulating layer 150 therebetween may constitute a second cell transistor CTR2. Therefore, the first cell transistor CTR1 and the second cell transistor CTR2 may be arranged to have a symmetrical shape in one mold opening 130H.

In some embodiments, the gate insulating layer 150 may include at least one of a high-k dielectric material and a ferroelectric material having a dielectric constant greater than that of silicon oxide. In some embodiments, the gate insulating layer 150 may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium tantalum oxide bismuth (STB), bismuth ferrous oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

In some embodiments, the word line WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

The insulating pad 182 and the first insulating layer 184 may be arranged between two word lines WL in each of the plurality of mold openings 130H. Each of the plurality of insulating pads 182 may be arranged on one word line WL and may have an L-shaped vertical cross section. The first insulating layer 184 may be arranged between the plurality of insulating pads 182 and may have a columnar cross section. However, the shapes of the insulating pad 182 and the first insulating layer 184 are not limited thereto, and in other embodiments, the shapes may vary.

The contact layer 170 may be formed on the channel layer 140. For example, the contact layer 170 may be connected to the upper surface of the channel layer 140. In some embodiments, the lowermost end of the contact layer 170 may be at a lower vertical level than the upper surface of the word line WL (for example, the distance between the lowermost end of the contact layer 170 and the substrate 110 in the vertical direction (Z direction) is less than the distance between the upper surface of the word line WL and the substrate 110 in the vertical direction (Z direction)). The contact layer 170 may connect the channel layer 140 to the capacitor structure 190. The contact layer 170 may include at least one of a conductive material (for example, a metal, a conductive metal nitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, a conductive metal oxide, and a 2D material), but is not limited thereto.

The second insulating layer 186 may be disposed on both side walls of the contact layer 170. Although the upper surface of the second insulating layer 186 is shown to be at the same level as the upper surfaces of the plurality of contact layers 170, the embodiment is not limited thereto. For example, the upper surface of the second insulating layer 186 may be at a higher level than the upper surfaces of the plurality of contact layers 170 (e.g., the distance between the upper surface of the second insulating layer 186 and the substrate 110 in the vertical direction (Z direction) is greater than the distance between the upper surfaces of the plurality of contact layers 170 and the substrate 110 in the vertical direction (Z direction)).

The insulating liner 182 may include silicon nitride, and the first insulating layer 184 may include silicon oxide. The second insulating layer 184 may include silicon nitride.

The etch stop layer 188 may be disposed on the contact layer 170 and the second insulating layer 186. The etch stop layer 188 may include an opening 188H, and an upper surface of the contact layer 170 may be exposed at a bottom portion of the opening 188H.

The capacitor structure 190 may be disposed on the etch stop layer 188. The capacitor structure 190 may include a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196. The sidewall of the bottom of the lower electrode 192 may be disposed in the opening 188H of the etch stop layer 188, and the lower electrode 192 may extend in the vertical direction (Z direction). The capacitor dielectric layer 194 may be disposed on the sidewall of the lower electrode 192, and the upper electrode 196 may cover or overlap the lower electrode 192 on the capacitor dielectric layer 194.

As the integration density of DRAM devices increases, the size of unit transistors may also decrease, and a vertical channel transistor (VCT) including a channel layer including IGZO may have a problem of reduced on-current ( _Ion ) when the thickness of the channel layer is equal to or less than 10 nm and an operating voltage is applied.

According to some embodiments, the threshold voltage V _th may be adjusted by forming the auxiliary channel layer 142 having a thickness less than 1 nm disposed between the first oxide semiconductor layer 141A and the second oxide semiconductor layer 141B. In addition, by forming the auxiliary channel layer 142 , the on-current (I _on ) may be increased.

Furthermore, by forming the first mold layer 130 in an oxygen tunneling structure having a multi-layer structure, the threshold voltage _Vth may be shifted in a positive direction (eg, the threshold voltage _Vth may be increased) without reducing the resistance of the channel layer 140. Therefore, the semiconductor device 100 may have improved electrical characteristics and improved reliability.

5 to 14 are cross-sectional views illustrating a method of manufacturing the semiconductor device 100 according to an embodiment of the present disclosure.

5 , a lower insulating layer 112 may be formed on a substrate 110. Next, a plurality of bit lines BL extending in a first horizontal direction (X direction) and a bit line insulating layer (not shown) filling spaces between the plurality of bit lines BL may be formed on the lower insulating layer 112. In some embodiments, each of the plurality of bit lines BL may include a conductive barrier layer, a conductive layer, and a conductive barrier layer sequentially arranged on the lower insulating layer 112.

6, a first mold layer 130 (MD1) may be formed on a plurality of bit lines BL and a plurality of bit line insulating layers. In some embodiments, the first mold layer 130 may be formed in a stacked structure. The first mold layer 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be formed to have a relatively large height in a vertical direction (Z direction).

In some embodiments, the first mold layer 130 may include lower and upper first insulating layers 131A and 131B and a second insulating layer 132. The second insulating layer 132 may be disposed between the lower and upper first insulating layers 131A and 131B. The first insulating layers 131A and 131B may include silicon nitride, and the second insulating layer 132 may include silicon oxide.

The first mold layer 130 may be formed as a multilayer structure in which silicon nitride, silicon oxide, and silicon nitride are sequentially stacked. The first mold layer 130 may have a multilayer structure including silicon nitride and silicon oxide, and may form an oxygen tunneling structure. By forming the first mold layer 130 as a multilayer structure including silicon oxide between silicon nitrides (e.g., an oxygen tunneling structure), as described above, the threshold voltage _Vth may be shifted in a positive direction without reducing the resistance of the channel layer 140.

The plurality of first mold layers 130 may extend in the second horizontal direction (Y direction) and may be formed to be spaced apart from each other at equal intervals in the first horizontal direction (X direction). A mold opening 130H extending in the second horizontal direction (Y direction) may be formed between the plurality of first mold layers 130.

The mold opening 130H may be formed by forming a mask pattern (not shown) on the first mold layer 130 and using the mask pattern as an etching mask. The upper surface of the bit line BL may be exposed to a bottom portion of each of the plurality of mold openings 130H. The plurality of mold openings 130H may include a first sidewall 130H1 and a second sidewall 130H2 opposite to each other.

7 , a preliminary channel layer 140P may be formed to conformally cover or overlap an inner wall of the mold opening 130H on the first mold layer 130 .

In some embodiments, the preliminary channel layer 140P may include a preliminary first oxide semiconductor layer 141AP, a preliminary second oxide semiconductor layer 141BP, and a preliminary auxiliary channel layer 142P. In this case, each of the preliminary first oxide semiconductor layer 141AP and the preliminary second oxide semiconductor layer 141BP may include IGZO. The preliminary auxiliary channel layer 142P may include a 2D material or In ₂ O ₃ .

The preliminary channel layer 140P may be formed in a sandwich structure. The preliminary first oxide semiconductor layer 141AP, the preliminary auxiliary channel layer 142P, and the preliminary second oxide semiconductor layer 141BP may be formed by sequentially stacking on the bit line BL. The preliminary first oxide semiconductor layer 141AP conformally covers or overlaps the inner wall of the mold opening 130H. The preliminary auxiliary channel layer 142P may be conformally formed on the preliminary first oxide semiconductor layer 141AP. The preliminary second oxide semiconductor layer 141BP may be conformally formed on the preliminary auxiliary channel layer 142P.

In some embodiments, the preliminary first oxide semiconductor layer 141AP, the preliminary second oxide semiconductor layer 141BP, and the preliminary auxiliary channel layer 142P may be formed by using at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition (ALD) process.

8 , a second mold layer MD2 covering or overlapping the preliminary channel layer 140P and filling a portion of the mold opening 130H may be formed. A plurality of second mold layers MD2 may extend in the first horizontal direction (X direction).

9, a plurality of channel layers 140 may be formed by etching back the second mold layer MD2. When the second mold layer MD2 is removed, a portion of the preliminary channel layer 140P may be removed together. A portion of the preliminary channel layer 140P covering or overlapping the upper surface of the first mold layer 130 may be removed to form a plurality of channel layers 140.

The preliminary channel layer 140P may be removed by using an etch-back process or a planarization process to leave the channel layer 140 in the mold opening 130H.

The channel layer 140 having a U-shaped vertical cross-section may be formed inside the mold opening 130H by using an etch-back process or a planarization process. In addition, when the preliminary channel layer 140P disposed on the upper surface of the first mold layer 130 is removed, the upper surface of the first mold layer 130 may be exposed. In this case, the upper surface of the channel layer 140 may be disposed at the same level as the upper surface of the first mold layer 130.

Each of the plurality of channel layers 140 may cover or overlap the inner side surface and the bottom surface of the mold opening 130H. Each of the plurality of channel layers 140 may be formed to have a U-shaped vertical cross-section. In this case, the vertical direction (Z direction) level of the channel layer 140 may be the same as the vertical direction (Z direction) level of the first mold layer 130.

10 , a preliminary gate insulating layer 150P and a preliminary gate electrode layer 160P covering or overlapping the channel layer 140 and the first mold layer 130 may be sequentially formed, respectively. The preliminary gate insulating layer 150P may cover or overlap the side surface and the upper surface of the channel layer 140. The preliminary gate insulating layer 150P may cover or overlap the upper surface of the upper first insulating layer 131B. The preliminary gate electrode layer 160P may conformally cover or overlap the side surface and the upper surface of the preliminary gate insulating layer 150P. Each of the preliminary gate insulating layer 150P and the preliminary gate electrode layer 160P may be formed to have a U-shaped vertical cross-section.

In some embodiments, the channel layer 140 may include a first portion extending in a first horizontal direction (X direction) and a second portion connected to both ends of the first portion and extending in a vertical direction (Z direction). The second portion of the channel layer 140 may include a first sidewall and a second sidewall. The first sidewall of the second portion of the channel layer 140 may be surrounded by the preliminary gate insulating layer 150P, and the second sidewall of the second portion of the channel layer 140 may be surrounded by the first mold layer 130.

The preliminary gate insulating layer 150P may include at least one of a high-k dielectric material and a ferroelectric material having a dielectric constant greater than that of silicon oxide. In some embodiments, the preliminary gate insulating layer 150P may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium tantalum oxide bismuth (STB), bismuth ferrous oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO) and lead scandium tantalum oxide (PbScTaO).

In some embodiments, the preliminary gate electrode layer 160P may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

11 , portions of the preliminary gate insulating layer 150P and the preliminary gate electrode layer 160P covering or overlapping at least portions of upper surfaces of the plurality of first mold layers 130 and at least portions of upper surfaces of the plurality of channel layers 140 may be removed to form a gate insulating layer 150 and word lines WL, respectively.

Portions of the preliminary gate insulating layer 150P and the preliminary gate electrode layer 160P disposed on the bottom portion of the channel layer 140 may be removed by performing an etching process to expose the upper surface of the channel layer 140. Portions of the preliminary gate insulating layer 150P and the preliminary gate electrode layer 160P may remain on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H. On the other hand, portions of the preliminary gate insulating layer 150P and the preliminary gate electrode layer 160P disposed on the upper surface of the first mold layer 130 may also be removed by the etching process.

The gate insulating layer 150 may be formed to cover or overlap the side surface of the channel layer 140 inside the mold opening 130H and extend in the vertical direction (Z direction). A plurality of gate insulating layers 150 may be arranged on the first sidewalls 130H1 and the second sidewalls 130H2 of the plurality of mold openings 130H, respectively. The gate insulating layer 150 may cover a portion of the first portion of the channel layer 140 and may have a nonlinear shape (e.g., an L-shape).

The preliminary gate electrode layer 160P may be divided into two word lines WL respectively arranged on the first sidewalls 130H1 and the second sidewalls 130H2 of the plurality of mold openings 130H. The plurality of word lines WL may be formed to cover or overlap the gate insulating layer 150 inside the mold openings 130H and extend in a vertical direction (Z direction).

In some embodiments, the gate electrode layers 160 may be formed to face each other inside one mold opening 130H. The plurality of gate electrode layers 160 may be separated from each other in a first horizontal direction (X direction), and may each extend in a second horizontal direction (Y direction).

In this case, a portion of the upper side of the word line WL in the vertical direction (Z direction) may also be removed by the etching process. Therefore, the vertical level of the uppermost end of the word line WL may be lower than that of the uppermost end of the channel layer 140 .

12 , an insulating liner 182 and a first insulating layer 184 may be formed inside the mold opening 130H. The insulating liner 182 and the first insulating layer 184 may be disposed between two adjacent word lines WL, and the insulating liner 182 may be disposed on an upper surface of the channel layer 140. The insulating liner 182 and the first insulating layer 184 may be formed by using an etch-back process or a planarization process.

In this manner, the first and second cell transistors CTR1 and CTR2 may be formed inside the mold opening 130H. The first and second cell transistors CTR1 and CTR2 may be spaced apart from each other in the first horizontal direction (X direction) and may be arranged to have symmetrical shapes with respect to each other (refer to FIG. 3 ).

13 , a recess process may be performed to remove a portion of the upper side of the channel layer 140. By removing a portion of the upper side of the channel layer 140, the uppermost end of the channel layer 140 may be disposed at a lower level than the uppermost end of the word line WL. In addition, a portion of the sidewall of the upper first insulating layer 131B may be exposed.

14 , a contact layer 170 and a second insulating layer 186 may be formed.

A mask pattern (not shown) may be formed on the contact conductive layer (not shown), a portion of the contact conductive layer may be removed by using the mask pattern to form the contact layer 170, and a second insulating layer 186 may be formed in a region where the contact conductive layer has been removed. In some embodiments, the contact layer 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

In some embodiments, the second insulating layer 186 may be formed by using silicon nitride. In addition, the sidewalls of the contact layer 170 may be surrounded by the second insulating layer 186, and the bottom surface of the contact layer 170 may cover or overlap a portion of the first mold layer 130, the channel layer 140, the gate insulating layer 150, or the insulating liner 182.

3 again, an etch stop layer 188 may be formed on the contact layer 170 and the second insulating layer 186. The etch stop layer 188 may include an opening 188H, and the upper surface of the contact layer 170 may be exposed on a bottom portion of the opening 188H. Thereafter, a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196 may be sequentially formed on the etch stop layer 188.

A plurality of lower electrodes 192 may be formed to extend in a vertical direction (Z direction) from an upper surface of the contact layer 170 exposed on a bottom surface of the opening 188H of the etch stop layer 188. Thereafter, capacitor dielectric layers 194 and upper electrodes 196 may be separately and sequentially formed on the plurality of lower electrodes 192 to form a semiconductor device 100 including a plurality of capacitor structures 190.

In this case, the lower electrode 192 may have a columnar shape extending from the upper surface of the contact layer 170 in the vertical direction (Z direction), but is not limited thereto, and the lower electrode 192 may be formed to have a cylindrical shape extending from the upper surface of the contact layer 170 in the vertical direction (Z direction). The capacitor dielectric layer 194 may be formed to conformally extend along the contours of the side surfaces and the upper surface of the plurality of lower electrodes 192 and along the upper surface of the etch stop layer 188. The upper electrode 196 may be formed to cover or overlap the capacitor dielectric layer 194.

While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0039260 filed on March 24, 2023 and Korean Patent Application No. 10-2023-0059961 filed on May 9, 2023, the disclosures of which are incorporated herein by reference in their entirety.

Claims (20)

1. A semiconductor device, comprising:

a substrate;

A bit line extending in a first horizontal direction on the substrate;

A first mold layer on the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line, and wherein the first mold layer extends in a second horizontal direction intersecting the first horizontal direction;

a channel layer on the bit line;

one or more word lines on sidewalls of the channel layer and extending in the second horizontal direction; and

A gate insulating layer between the one or more word lines and the channel layer,

Wherein the channel layer includes a first oxide semiconductor layer, a second oxide semiconductor layer, and an auxiliary channel layer between the first oxide semiconductor layer and the second oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises Indium Gallium Zinc Oxide (IGZO).

3. The semiconductor device of claim 1, wherein the auxiliary channel layer comprises at least one of a two-dimensional (2D) material and indium oxide.

4. The semiconductor device of claim 1, wherein a thickness of the auxiliary channel layer is less than 1nm.

5. The semiconductor device of claim 1, wherein the first mold layer comprises a lower first insulating layer over the bit line, a second insulating layer over the lower first insulating layer, and an upper first insulating layer over the second insulating layer.

6. The semiconductor device according to claim 5, wherein the lower first insulating layer and the upper first insulating layer comprise silicon nitride, and wherein the second insulating layer comprises silicon oxide.

7. The semiconductor device according to claim 5, wherein a thickness of the second insulating layer is larger than a thickness of the lower first insulating layer and a thickness of the upper first insulating layer in a vertical direction.

8. The semiconductor device according to claim 1, wherein a thickness of the first oxide semiconductor layer and a thickness of the second oxide semiconductor layer are greater than a thickness of the auxiliary channel layer.

9. The semiconductor device of claim 1, wherein the channel layer is on an inner wall of the die opening or on the upper surface of the bit line.

10. The semiconductor device of claim 1, wherein the channel layer extends on opposing first and second inner walls of the die opening and on an upper surface of the bit line between the first and second inner walls.

11. The semiconductor device of claim 1, wherein the one or more word lines comprise a first word line and a second word line spaced apart from each other in the first horizontal direction in the die opening,

Wherein the semiconductor device further comprises an insulating liner and a first insulating layer between the first word line and the second word line.

12. A semiconductor device, comprising:

a substrate;

A bit line extending in a first horizontal direction on the substrate;

a first mold layer over the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line;

a channel layer on an inner wall of the mold opening, wherein the channel layer includes a first oxide semiconductor layer on the inner wall of the mold opening or on the bit line, an auxiliary channel layer on the first oxide semiconductor layer, and a second oxide semiconductor layer on the auxiliary channel layer;

a word line on a sidewall of the channel layer, wherein the word line extends in a second horizontal direction intersecting the first horizontal direction; and

A gate insulating layer between the word line and the channel layer,

Wherein the auxiliary channel layer comprises at least one of a two-dimensional (2D) material and indium oxide.

13. The semiconductor device according to claim 12, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises Indium Gallium Zinc Oxide (IGZO).

14. The semiconductor device of claim 12, wherein a thickness of the auxiliary channel layer is less than 1nm.

15. The semiconductor device of claim 12, wherein the first mold layer comprises:

a lower first insulating layer on the bit line and including silicon nitride;

A second insulating layer on the lower first insulating layer and including silicon oxide; and

An upper first insulating layer on the second insulating layer and including silicon nitride.

16. The semiconductor device according to claim 15, wherein a thickness of the second insulating layer is larger than a thickness of the lower first insulating layer and a thickness of the upper first insulating layer in a vertical direction.

17. The semiconductor device according to claim 12, wherein a thickness of the first oxide semiconductor layer and a thickness of the second oxide semiconductor layer are greater than a thickness of the auxiliary channel layer.

18. A semiconductor device, comprising:

a substrate;

A bit line extending in a first horizontal direction on the substrate;

A first mold layer over the bit line, wherein the first mold layer defines a mold opening exposing a portion of an upper surface of the bit line, wherein the first mold layer comprises a lower first insulating layer, a second insulating layer over the lower first insulating layer, and an upper first insulating layer over the second insulating layer;

a channel layer on an inner wall of the mold opening, wherein the channel layer includes a first oxide semiconductor layer on the inner wall of the mold opening or on the bit line, an auxiliary channel layer on the first oxide semiconductor layer, and a second oxide semiconductor layer on the auxiliary channel layer;

A word line on a sidewall of the channel layer, wherein the word line extends in a second horizontal direction intersecting the first horizontal direction;

a gate insulating layer between the word line and the channel layer;

A capacitor structure on the first mold layer; and

A contact layer between the channel layer and the capacitor structure,

Wherein each of the lower first insulating layer and the upper first insulating layer comprises silicon nitride,

Wherein the second insulating layer comprises silicon oxide,

Wherein the auxiliary channel layer comprises at least one of a two-dimensional (2D) material and indium oxide.

19. The semiconductor device according to claim 18, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises Indium Gallium Zinc Oxide (IGZO).

20. The semiconductor device of claim 18, wherein a thickness of the auxiliary channel layer is less than 1nm.