CN118694359A - A digital phase detector and a digital delay locked loop - Google Patents

Abstract

A digital phase detector and a digital delay phase-locked loop. The digital phase detector samples input and output clocks mutually to generate two initial phase relationship signals; then the two initial phase relationship signals are counted independently, and when the counting time lasts for multiple counting cycles, the two counting results are compared to generate two phase relationship flag signals; the two phase relationship flag signals are counted again to generate two counting results, and when one of the two counting results reaches N first, the value of the 1-bit global phase discrimination result to be output is determined; thus, when in a metastable interval, the uncertain values after the decision time of a D flip-flop are counted multiple times, and a result with a greater probability is output, which can significantly reduce the phenomenon of early or late phase locking caused by the metastable phenomenon of the device in the traditional phase detector solution, and also avoid the problem of unclear phase relationship caused by the burrs that may be generated by the output clock, thereby increasing the accuracy of phase discrimination.

Description

A digital phase detector and a digital delay locked loop

Technical Field

The invention relates to the field of phase-locked loops, and in particular to a digital phase detector and a digital delay phase-locked loop.

Background Art

The phase-locked loop can automatically track the frequency and phase of the input signal through the feedback circuit. Phase-locked loop technology is divided into DLL (Delay Locked Loop) and PLL (Phase Locked Loop). DLL mainly replaces the voltage-controlled oscillator of PLL with a digitally controlled variable delay line, which can quickly change the delay path and significantly reduce circuit noise and clock jitter. PLL is mainly used in analog circuits and can be used for frequency synthesis and phase alignment, while DLL is mainly used for clock phase shift in digital circuits. The phase detector is an important part of the phase-locked loop. The existing phase detector has a method of realizing simple phase detection through an XOR gate, but it will be affected by glitches and the error is too large. Another type of timing phase detector composed of D flip-flops is also called a frequency phase detector. The structure is that the inputs of two D flip-flops are connected to a high level, and the outputs are connected to the AND gate and fed back to the reset end of the D flip-flop to generate a phase relationship between the two clocks. In the PLL and analog DLL, the charge pump can be controlled to charge and discharge the filter capacitor. However, this structure will be affected by the delay of the AND gate and reset, as well as the influence of device process and temperature, and will inevitably enter the metastable window, resulting in the result cannot be stabilized at 1 or 0, and thus cannot be accurately phase-locked, limiting the application scenarios in high-frequency and multi-phase scenarios.

Summary of the invention

The technical problem to be solved by the present invention is to provide a digital phase detector and a digital delay locked loop to address the defect of insufficient phase locking accuracy in the prior art.

The technical solution adopted by the present invention to solve the technical problem is:

On the one hand, a digital phase detector is constructed, which includes:

A phase relationship generating unit, configured to receive an input clock and an output clock output by a digitally controlled delay chain, sample the input clock and the output clock, and generate a first initial phase relationship signal representing whether the output clock is ahead of the input clock and a second initial phase relationship signal representing whether the output clock is behind the input clock;

a phase relationship counting unit, configured to count the first initial phase relationship signal to generate a first counting result, and to count the second initial phase relationship signal to generate a second counting result;

a phase result generating unit, configured to compare the first counting result and the second counting result when the counting time lasts for a plurality of counting cycles, and generate a first phase relationship flag signal representing whether the output clock is ahead of the input clock and a second phase relationship flag signal representing whether the output clock is behind the input clock;

a phase result counting unit, configured to count the first phase relationship flag signal to generate a third counting result, and to count the second phase relationship flag signal to generate a fourth counting result;

The phase result output unit is used to determine the value of the 1-bit global phase discrimination result to be output according to whether the third counting result or the fourth counting result reaches N first, where N is a positive integer.

Furthermore, in the digital phase detector described in the present invention, the phase relationship generating unit is implemented based on a trigger, and the value of N must satisfy: the delay of the N delay units in the digitally controlled delay chain is greater than the metastable duration of the trigger.

Furthermore, in the digital phase detector described in the present invention, the input clock is a system clock that has passed through a fixed delay, and the output clock is a system clock that has passed through a digitally controlled delay chain.

Furthermore, in the digital phase detector described in the present invention, the phase result output unit specifically sets the global phase detection result to a first level when the third counting result reaches N first, and sets the global phase detection result to a second level when the fourth counting result reaches N first, and the first level is opposite to the second level.

Furthermore, in the digital phase detector of the present invention, the phase relationship counting unit specifically includes:

An advance counting module, configured to count the first initial phase relationship signal to generate a first counting result, and to maintain the first counting result when the received first sampling flag signal is valid, and to clear the first counting result to zero when the received sampling reset signal is valid;

a hysteresis counting module, configured to count the second initial phase relationship signal to generate a second counting result, and to maintain the second counting result when a second sampling flag signal is received, and to clear the second counting result to zero when the received sampling reset signal is valid;

The synchronization module is used to synchronize the first sampling mark signal to the time domain of the output clock as the second sampling mark signal, and synchronize the second counting result output by the hysteresis counting module to the time domain of the input clock and then output it.

Furthermore, in the digital phase detector of the present invention,

The synchronization module is specifically used to generate the second sampling flag signal by the first sampling flag signal connected to the M D flip-flops under the output clock when the response signal is invalid, and synchronize the second sampling flag signal to the clock domain of the input clock through the M D flip-flops under the input clock as a data request signal; the hysteresis counting module synchronizes the maintained second counting result to the synchronization module for output only when the request signal is valid;

The synchronization module is also used to generate a response signal after the data request signal passes through the M D flip-flops under the output clock, and when the response signal is valid, the second sampling flag signal is set to invalid, otherwise the first sampling flag signal is connected.

Furthermore, the digital phase detector of the present invention further comprises:

The sampling control unit is used to receive the count value of the input clock, and when the count value reaches Y, the first sampling flag signal and the sampling reset signal are successively enabled.

Furthermore, in the digital phase detector described in the present invention, the phase relationship generating unit includes a first trigger and a second trigger; the clock end of the first trigger is connected to the input clock, the D end of the first trigger is connected to the output clock, and the Q end of the first trigger outputs the first initial phase relationship signal; the clock end of the second trigger is connected to the output clock, the D end of the second trigger is connected to the input clock, and the Q end of the second trigger outputs the second initial phase relationship signal.

In the second aspect, a digital delay locked loop is constructed, which includes a digital phase detector, a controller and a digitally controlled delay chain as described in any of the preceding items; the controller is used to receive the global phase detection result and adjust the number of delay units enabled in the digitally controlled delay chain according to the global phase detection result.

Furthermore, in the digital delay locked loop of the present invention, the controller comprises:

A frequency division counting circuit is used for performing Y-frequency division on the input clock to generate a frequency division clock signal, outputting the frequency division clock signal to the state machine module to drive the state transfer, and at the same time counting the input clock and outputting the count value to the digital phase detector to generate a first sampling flag signal and a sampling reset signal;

The state machine module includes four states: IDLE, LF1, INC, and DEC. IDLE is an idle state. The LF1 state is an output clock with a phase difference of 0°-180° relative to the input clock. The INC state is an output clock with a phase difference of 180°-360° relative to the input clock. The DEC state represents phase lock completion, wherein: when the frequency division count is turned on and the LF1 state is entered, the target count value is self-incremented; the condition for the LF1 state to jump to the INC state is that the global phase detection result is a first level; the condition for the INC state to jump to the DEC state is that the global phase detection result changes to a second level; when entering the DEC state, the target count value minus N is used as the number of delay units that need to be enabled in the digital control delay chain, and the phase lock completion flag bit is set to represent the completion of phase lock.

The digital phase detector and the digital delay locked loop of the present invention have the following beneficial effects: the present invention samples the input clock and the output clock mutually, generates a first initial phase relationship signal representing whether the output clock is ahead of the input clock and a second initial phase relationship signal representing whether the output clock is behind; then counts the first initial phase relationship signal to generate a first counting result, and counts the second initial phase relationship signal to generate a second counting result; compares the first counting result and the second counting result when the counting time lasts for a plurality of counting cycles, generates a first phase relationship flag signal representing whether the output clock is ahead of the input clock and a second phase relationship flag signal representing whether the output clock is behind; then compares the first phase The relationship flag signal is counted to generate a third counting result, and the second phase relationship flag signal is counted to generate a fourth counting result, and when the third counting result or the fourth counting result reaches N first, the value of the 1-bit global phase detection result to be output is determined; in this way, when in the metastable interval, by repeatedly counting the uncertain values after the D flip-flop decision time, a result with a larger probability is output, which can significantly reduce the phenomenon of device metastable phenomenon in traditional phase detector schemes causing premature or late phase locking. In addition, it also avoids the problem of unclear phase relationship caused by glitches that may be generated by the output clock, ensures the safety of timing, increases the accuracy of phase detection, is conducive to digital integration, and can meet the needs of high-precision phase selection at different temperatures.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work:

FIG1 is a schematic diagram of the structure of a digital delay locked loop according to the present invention;

FIG2 is a schematic diagram of the structure of a digital phase detector of the present invention;

FIG3 is a schematic diagram of the structure of a phase relationship generating unit;

FIG4 is a schematic diagram of the structure of the controller.

DETAILED DESCRIPTION

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

1 , the digital delay locked loop (DLL) of the present invention includes a digital phase detector, a controller and a digital controlled delay chain (DCDL).

The controller is used for receiving a global phase detection result pd_out output by the digital phase detector and adjusting the number of enabled delay units in the digital controlled delay chain according to the global phase detection result pd_out.

In this embodiment, the digital control delay chain uses 256 levels of delay units to be selected, each level is about 135ps (affected by temperature), and the number of delay units corresponding to phase locking can be output according to different input clock clk_in frequencies, and the input clock clk_in is not less than 30Mhz.

The digital phase detector has two inputs, namely, input clock clk_in and output clock clk_out. The output clock clk_out is the output of the system clock after passing through the digital control delay chain, as shown in FIG1 , where Clk_in(system) represents the system clock. The input clock clk_in can directly select the system clock Clk_in(system), but in this embodiment, considering that the output clock clk_out will be delayed after passing through the digital control delay chain (the delay caused by the multiplexer of the digital control delay chain), the input clock clk_in also passes through a delay chain of the same length, for example, the system clock Clk_in(system) is passed through a delay chain for a fixed delay before the input clock clk_in is output to the digital phase detector. In this way, both inputs of the digital phase detector (input clock clk_in and output clock clk_out) pass through the delay chain structure, so the error caused by the multiplexer in the delay chain structure will have an effect on both inputs of the digital phase detector, thereby achieving the effect of offsetting the delay error. The digital phase detector outputs a global phase detection result pd_out, and the global phase detection result pd_out is output to the controller.

The digital phase detector is explained in detail below.

Referring to FIG2 , the digital phase detector of the present invention has inputs of clk_in (input clock after fixed delay) and clk_out (output clock after controllable delay chain delay), and outputs a 1-bit global phase detection result pd_out. The digital phase detector mainly includes: a phase relationship generating unit 1, a phase relationship counting unit 2, a phase result generating unit 3, a phase result counting unit 4, a phase result output unit 5, and a sampling control unit 6.

The phase relationship generating unit 1 is used to receive the input clock clk_in and the output clock clk_out output by the digital control delay chain, sample the input clock clk_in and the output clock clk_out, and generate a first initial phase relationship signal clk_out_leading representing whether the output clock clk_out is ahead of the input clock clk_in and a second initial phase relationship signal clk_out_lagging representing whether the output clock clk_out is lagging. With reference to FIG3 , the phase relationship generating unit 1 is implemented based on a trigger, including a first trigger and a second trigger, and two D triggers generate two signals representing the phase relationship between clk_in and clk_out. The clock end of the first trigger is connected to the input clock clk_in, the D end of the first trigger is connected to the output clock clk_out, and the Q end of the first trigger outputs the first initial phase relationship signal clk_out_leading. The high value of the Q end clk_out_leading indicates that clk_out is ahead of clk_in. The clock terminal of the second flip-flop is connected to the output clock clk_out, the D terminal of the second flip-flop is connected to the input clock clk_in, the Q terminal of the second flip-flop outputs the second initial phase relationship signal clk_out_lagging, and the Q terminal clk_out_lagging is high, indicating that clk_out lags clk_in.

The phase relationship counting unit 2 is used for counting the first initial phase relationship signal clk_out_leading to generate a first counting result cnt_sampl_lead, and for counting the second initial phase relationship signal clk_out_lagging to generate a second counting result cnt_sampl_lagg.

Specifically, the phase relationship counting unit 2 specifically includes an advance counting module 21, a lag counting module 22 and a synchronization module 23. The advance counting module 21 is used to count the first initial phase relationship signal clk_out_leading to generate a first counting result cnt_sampl_lead, and to maintain the first counting result cnt_sampl_lead when the received first sampling flag signal sampl_flag is valid, and to clear the first counting result cnt_sampl_lead when the received sampling reset signal reset_sampl is valid. The synchronization module 23 is used to receive the first sampling flag signal sampl_flag and convert it to the time domain of the output clock clk_out as the second sampling flag signal sampl_flag_clkout. The hysteresis counting module 22 is used to count the second initial phase relationship signal clk_out_lagging to generate a second counting result cnt_sampl_lagg, and to maintain the second counting result cnt_sampl_lagg when the received second sampling flag signal sampl_flag_clkout is valid, and to clear the second counting result cnt_sampl_lagg when the received sampling reset signal reset_sampl is valid. The synchronization module 23 is also used to synchronize the first sampling flag signal sampl_flag to the time domain of the output clock clk_out as the second sampling flag signal sampl_flag_clkout, and to synchronize the second counting result cnt_sampl_lagg output by the hysteresis counting module 22 to the time domain of the input clock clk_in and then output it.

That is, the leading counting module 21 and the lagging counting module 22 are two clock domains that independently and periodically count the two Q-end levels in FIG2. Assuming that the counting cycle is Y clk_in cycles, the phase relationship between clk_in and clk_out is kept unchanged within Y clk_in cycles (that is, the number of delay units in the delay chain remains unchanged), and clk_out_leading and clk_out_lagging are counted in each clk_in cycle. If clk_out_leading is high, cnt_sampl_lead is increased by 1, otherwise cnt_sampl_lead remains unchanged. Similarly, if clk_out_lagging is high, clk_out_lagging is increased by 1, otherwise clk_out_lagging remains unchanged. When Y clk_in cycles arrive, the sampling flag sampl_flag is valid, and the counting result is kept unchanged at this time, so that the data is stable and sampled and compared. After sampl_flag is set valid, reset_sampl is also set valid immediately. The validity of reset_sampl resets the count values of the two counting units (cnt_sampl_lead, cnt_sampl_lagg) to 0, so that the leading counting module 21 and the lagging counting module 22 restart counting after the next phase shift.

In addition, because clk_out and clk_in are in an asynchronous relationship, in order to maintain synchronous timing design, the signal in the clk_out clock domain is synchronized to the clk_in clock domain, so the synchronization module 23 is required to synchronize the counting result cnt_sampl_lagg in the clk_out clock domain to the input clock clk_in domain. This embodiment uses handshake processing to synchronize the counting result:

1) When the response signal (ack, not shown in the figure, the generation of ack will be explained in the subsequent part 3)) is invalid, the synchronization module 23 generates the second sampling flag signal sampl_flag_clkout by using the M D flip-flops (such as 2 D flip-flops) under the output clock clk_out, and the hysteresis counting module 22 maintains the second counting result cnt_sampl_lagg when the received second sampling flag signal sampl_flag_clkout is valid (in this embodiment, sampl_flag_clkout is 1 valid);

2) After generating the second sampling flag signal sampl_flag_clkout, the synchronization module 23 also synchronizes the second sampling flag signal sampl_flag_clkout to the clock domain of the input clock clk_in through M D flip-flops (such as 2 D flip-flops) under the input clock clk_in as a data request signal (req_d, not shown in the figure); the hysteresis counting module 22 synchronizes the maintained second counting result cnt_sampl_lagg to the synchronization module 23 for output only when the request signal req_d is valid, and the synchronization output is recorded as cnt_sampl_lagg_clkin; at this time, the data synchronization is completed. It can be understood that when the request signal req_d is invalid, the second counting result cnt_sampl_lagg is only maintained, but will not be synchronized to the synchronization module 23 for output.

3) After generating the data request signal req_d, the synchronization module 23 further generates a response signal ack after passing the data request signal req_d through M D flip-flops (for example, 2 D flip-flops) under the output clock clk_out. When the response signal ack is valid, the second sampling flag signal sampl_flag_clkout is set to invalid (in this embodiment, sampl_flag_clkout is set to 0), otherwise the first sampling flag signal sampl_flag is connected.

It can be seen from the above that the sampling and resetting of the entire phase relationship generating unit 1 depends on the external first sampling flag signal sampl_flag and the sampling reset signal reset_sampl, which are output by the sampling control unit 6. Specifically, the sampling control unit 6 is used to receive the count value cnt_div of the input clock clk_in, and the count value cnt_div will be described in detail in the controller part later. When the count value cnt_div reaches Y, the first sampling flag signal sampl_flag and the sampling reset signal reset_sampl are successively set to be valid. The selection of Y can be customized according to the needs, but it must be ensured that after Y subtracts the necessary synchronization and reset cycles in the phase relationship counting unit 2, there are still several cycles for counting cnt_sampl_lead and cnt_sampl_lagg. For example, in this embodiment, the specific value of Y is 16, the first sampling flag signal sampl_flag is set to be valid specifically to 1, and the sampling reset signal reset_sampl is set to be valid specifically to 0, which means that when cnt_div is recorded to 16, sampl_flag is pulled high and reset_sampl is pulled low.

Among them, the phase result generating unit 3 is used to compare the counting result generated by the phase relationship generating unit 1 after the first sampling flag signal sampl_flag arrives and before the sampling reset signal reset_sampl, that is, to compare the first counting result cnt_sampl_lead and the second counting result cnt_sampl_lagg when the counting time lasts for Y counting cycles (one counting cycle is specifically a clk_in cycle), and generate the first phase relationship flag signal result_lead representing whether the output clock clk_out is ahead of the input clock clk_in and the second phase relationship flag signal result_lagg representing whether it is lagging behind according to the comparison result. Specifically, when cnt_sampl_lead is less than cnt_sampl_lagg_clkin, it is determined that the clk_out generated by the current DCDL lags behind clk_in (the phase difference is between 0 and 180°), and result_lagg is pulled high at this time; when cnt_sampl_lead is greater than cnt_sampl_lagg_clkin, it is determined that the clk_out generated by the current DCDL leads clk_in (the phase difference is between 180 and 360°), and result_lead is pulled high at this time.

The phase result counting unit 4 is used to count the first phase relationship flag signal result_lead to generate a third counting result cnt_result_lead, and to count the second phase relationship flag signal result_lagg to generate a fourth counting result cnt_result_lagg. Because the counting cycle of the phase result generating unit 3 of the previous stage is Y=16, it means that one of result_lead and result_lagg will be valid once every 16 clk_in, representing the phase relationship between clk_out and clk_in under the number of delay units at this time, so counting result_lead and result_lagg is actually counting once every 16 clk_in.

The phase result output unit 5 is used to determine the value of the 1-bit global phase discrimination result pd_out to be output according to whether the third counting result cnt_result_lead or the fourth counting result cnt_result_lagg reaches N first.

That is, the level change of the global phase detection result pd_out depends on the counting result of the phase result counting unit 4. Specifically, when the third counting result cnt_result_lead reaches N first, the global phase detection result pd_out is set to the first level; when the fourth counting result cnt_result_lagg reaches N first, the global phase detection result pd_out is set to the second level. The first level is opposite to the second level, for example, the first level is 1 and the second level is 0.

The default initial value of the global phase detection result pd_out is the second level. When pd_out changes from the second level to the first level and then from the first level to the second level, it means that the phase lock is successful. At this time, the number of delay units minus N is the number of delay units when the phase lock is successful. The DLL can output this value as the input of other related circuits.

Here, N is a positive integer, and the value of N must satisfy: the delay of the N delay units in the digital control delay chain is greater than the metastable duration of the trigger. For example, in this embodiment, N is determined to be 3 based on the metastable window size of the trigger (depending on the device process) combined with the delay time of a single delay unit. This design can ensure that the phase relationship will not be erroneously changed in advance due to the metastable state when phase locking is performed, thereby improving the accuracy of delay unit selection.

Due to the adoption of a fully digital circuit design, compared to the traditional phase detector, this design generates a unique phase relationship by sampling the input clock clk_in (system clock after a fixed delay) and the output clock clk_out (system clock after a digitally controlled delay chain), counting independently, and comparing the counting results, that is, the output clock clk_out is ahead of or behind the input clock clk_in. When in the metastable interval, the phase detector of the present invention can output a result with a greater probability by repeatedly counting the uncertain values after the D flip-flop decision time, which can significantly reduce the phenomenon of premature or late phase locking caused by the metastable phenomenon of the traditional D flip-flop, and also avoid the problem of unclear phase relationship caused by the burrs that may be generated by the output clock clk_out. The invention ensures the safety of the timing, increases the accuracy of the phase detector, is conducive to digital integration, and can meet the needs of high-precision phase selection at different temperatures.

The controller is briefly introduced below. Referring to Figure 4, the controller mainly includes a state machine module and a frequency division counting circuit. The state machine has four state transfer logics, namely the front 180 degrees, the back 180 degrees, the phase lock completion and the idle state. It outputs an 8-bit phase selection signal and a phase lock completion flag signal. The phase selection signal is an increasing value from 0 to 255, which is output to DCDL to select the number of delay units. DCDL is a delay unit composed of buffers and connected in series as a delay chain. The selection of the number of delay units is completed by 255 multiplexers. At the same time, DCDL integrates a fixed delay chain to access the system clock and output the input clock clk_in, thereby matching the additional delay generated by the output clock clk_out through the multiplexer.

The frequency division counting circuit is used to perform Y-division on the input clock clk_in to generate a divided clock signal clk_div (cnt_div is required to count when generating clk_div), output the divided clock signal clk_div to the state machine module to drive the state transfer, and at the same time count the input clock clk_in and output the count value cnt_div to the digital phase detector to generate a first sampling flag signal sampl_flag and a sampling reset signal reset_sampl.

The state machine module includes four states: IDLE, LF1, INC, and DEC. IDLE is an idle state. The LF1 state is a state in which the phase difference between the output clock clk_out and the input clock clk_in is 0°-180°. The INC state is a state in which the phase difference between the output clock clk_out and the input clock clk_in is 180°-360°. The DEC state represents phase lock completion, wherein: when the frequency division count is turned on (i.e., each time cnt_div=1), the LF1 state is entered, and the target count value cnt_inc is self-incremented; the condition for the LF1 state to jump to the INC state is that the global phase detection result pd_out is the first level, which is 1 in this embodiment; the condition for the INC state to jump to the DEC state is that the global phase detection result pd_out changes to the second level, which is 0 in this embodiment. When entering the DEC state, cnt_inc has been added to the three delay units that exceed the phase lock requirement according to the logic of the phase detector, so the target count value cnt_inc minus N is used as the number of delay units that need to be enabled in the digital control delay chain, and the phase lock completion flag Result_valid will be set to represent the completion of the phase lock. It should be noted here that the number of delay units that need to be enabled is a decimal value and needs to be converted into an 8-bit binary number, which is the phase selection signal Cnt_inc[7:0]. The signal Cnt_inc[7:0] corresponds to controlling 255 multiplexers to indirectly select 256 different delays.

Through the above design, this embodiment greatly ensures the safety of digital circuit timing, eliminates the glitches caused by asynchronous circuits in the DLL, and significantly reduces the impact of metastable states on phase results, which is of great significance for the design of DLLs with high precision and multi-phase requirements.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

Terms including ordinal numbers such as "first" and "second" used in this specification may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named as the second component, and similarly, the second component may also be named as the first component.

The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims (10)

1. A digital phase detector, comprising: A phase relationship generating unit (1) is used for receiving an input clock (clk_in) and an output clock (clk_out) output by a digitally controlled delay chain, sampling the input clock (clk_in) and the output clock (clk_out) to generate a first initial phase relationship signal (clk_out_leading) indicating whether the output clock (clk_out) is leading relative to the input clock (clk_in) and a second initial phase relationship signal (clk_out_lagging) indicating whether the output clock (clk_out) is lagging relative to the input clock (clk_in); A phase relationship counting unit (2), used for counting the first initial phase relationship signal (clk_out_leading) to generate a first counting result (cnt_sampl_lead), and for counting the second initial phase relationship signal (clk_out_lagging) to generate a second counting result (cnt_sampl_lagg); A phase result generating unit (3) is used to compare the first counting result (cnt_sampl_lead) and the second counting result (cnt_sampl_lagg) when the counting time lasts for a plurality of counting cycles, and to generate a first phase relationship flag signal (result_lead) indicating whether the output clock (clk_out) is ahead of the input clock (clk_in) and a second phase relationship flag signal (result_lagg) indicating whether the output clock (clk_out) is behind; A phase result counting unit (4), used for counting the first phase relationship flag signal (result_lead) to generate a third counting result (cnt_result_lead), and for counting the second phase relationship flag signal (result_lagg) to generate a fourth counting result (cnt_result_lagg); The phase result output unit (5) is used to determine the value of the 1-bit global phase discrimination result (pd_out) to be output according to whether the third counting result (cnt_result_lead) or the fourth counting result (cnt_result_lagg) reaches N first, where N is a positive integer. 2. The digital phase detector according to claim 1 is characterized in that the phase relationship generating unit (1) is implemented based on a trigger, and the value of N must satisfy: the delay of the N delay units in the digitally controlled delay chain is greater than the metastable duration of the trigger. 3. The digital phase detector according to claim 1, characterized in that the input clock (clk_in) is a system clock that has passed a fixed delay, and the output clock (clk_out) is a system clock that has passed a digitally controlled delay chain. 4. The digital phase detector according to claim 1 is characterized in that the phase result output unit (5) specifically sets the global phase detection result (pd_out) to a first level when the third counting result (cnt_result_lead) first reaches N, and sets the global phase detection result (pd_out) to a second level when the fourth counting result (cnt_result_lagg) first reaches N, and the first level is opposite to the second level. 5. The digital phase detector according to claim 1, characterized in that the phase relationship counting unit (2) specifically comprises: A leading counting module (21) is used for counting the first initial phase relationship signal (clk_out_leading) to generate a first counting result (cnt_sampl_lead), and maintaining the first counting result (cnt_sampl_lead) when the received first sampling flag signal (sampl_flag) is valid, and clearing the first counting result (cnt_sampl_lead) to zero when the received sampling reset signal (reset_sampl) is valid; A hysteresis counting module (22), configured to count the second initial phase relationship signal (clk_out_lagging) to generate a second counting result (cnt_sampl_lagg), maintain the second counting result (cnt_sampl_lagg) when a second sampling flag signal (sampl_flag_clkout) is received, and clear the second counting result (cnt_sampl_lagg) when the received sampling reset signal (reset_sampl) is valid; The synchronization module (23) is used to synchronize the first sampling flag signal (sampl_flag) to the time domain of the output clock (clk_out) as the second sampling flag signal (sampl_flag_clkout), and synchronize the second counting result (cnt_sampl_lagg) output by the lag counting module (22) to the time domain of the input clock (clk_in) and then output it. 6. The digital phase detector according to claim 5, characterized in that: The synchronization module (23) is specifically used for generating the second sampling flag signal (sampl_flag_clkout) from the first sampling flag signal (sampl_flag) received through the M D flip-flops under the output clock (clk_out) when the response signal is invalid, and synchronizing the second sampling flag signal (sampl_flag_clkout) to the clock domain of the input clock (clk_in) as a data request signal through the M D flip-flops under the input clock (clk_in); the lag counting module (22) synchronizes the maintained second counting result (cnt_sampl_lagg) to the synchronization module (23) for output only when the request signal is valid; The synchronization module (23) is also used for generating a response signal after the data request signal passes through the M D flip-flops under the output clock (clk_out); when the response signal is valid, the second sampling flag signal (sampl_flag_clkout) is set to be invalid; otherwise, the first sampling flag signal (sampl_flag) is connected. 7. The digital phase detector according to claim 5, further comprising: The sampling control unit (6) is used to receive the count value (cnt_div) of the input clock (clk_in), and when the count value (cnt_div) reaches Y, the first sampling flag signal (sampl_flag) and the sampling reset signal (reset_sampl) are successively enabled. 8. The digital phase detector according to claim 1 is characterized in that the phase relationship generating unit (1) comprises a first trigger and a second trigger; the clock end of the first trigger is connected to the input clock (clk_in), the D end of the first trigger is connected to the output clock (clk_out), and the Q end of the first trigger outputs the first initial phase relationship signal (clk_out_leading); the clock end of the second trigger is connected to the output clock (clk_out), the D end of the second trigger is connected to the input clock (clk_in), and the Q end of the second trigger outputs the second initial phase relationship signal (clk_out_lagging). 9. A digital delay locked loop, characterized in that it comprises a digital phase detector, a controller and a digital controlled delay chain as described in any one of claims 1 to 8; the controller is used to receive the global phase detection result (pd_out) and adjust the number of delay units enabled in the digital controlled delay chain according to the global phase detection result (pd_out). 10. The digital delay locked loop according to claim 9, wherein the controller comprises: A frequency division counting circuit, used for performing Y-frequency division on the input clock (clk_in) to generate a frequency division clock signal (clk_div), outputting the frequency division clock signal (clk_div) to the state machine module to drive the state transfer, and at the same time counting the input clock (clk_in) and outputting the count value (cnt_div) to the digital phase detector to generate a first sampling flag signal (sampl_flag) and a sampling reset signal (reset_sampl); The state machine module includes four states: IDLE, LF1, INC, and DEC. IDLE is an idle state. The LF1 state is a phase difference of 0°-180° between the output clock (clk_out) and the input clock (clk_in). The INC state is a phase difference of 180°-360° between the output clock (clk_out) and the input clock (clk_in). The DEC state represents phase lock completion, wherein: when the frequency division count is turned on and the LF1 state is entered, the target count value (cnt_inc) is self-incremented; the condition for the LF1 state to jump to the INC state is that the global phase detection result (pd_out) is the first level; the condition for the INC state to jump to the DEC state is that the global phase detection result (pd_out) changes to the second level; when entering the DEC state, the target count value (cnt_inc) minus N is used as the number of delay units that need to be enabled in the digital control delay chain, and the phase lock completion flag (Result_valid) is set to represent the completion of phase lock.