CN118694335A

CN118694335A - A phase shifter and control module thereof

Info

Publication number: CN118694335A
Application number: CN202410693723.8A
Authority: CN
Inventors: 李健雄; 李南
Original assignee: Shanghai Archiwave Electronic Technology Co ltd
Current assignee: Shanghai Archiwave Electronic Technology Co ltd
Priority date: 2024-05-30
Filing date: 2024-05-30
Publication date: 2024-09-24

Abstract

The embodiment of the present disclosure provides a phase shifter and a control module thereof, wherein the phase shifter includes: an orthogonal signal generator, used to generate orthogonal I-path signal and Q-path signal based on a differential input signal; a gain amplification module, including an I branch and a Q branch; the I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I-path signal based on a received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on a received second gain control signal; the Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q-path signal based on a received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-path signal based on a received fourth gain control signal; and a vector synthesizer, used to perform vector summation on the signal output by the gain amplification module to obtain a differential output signal.

Description

Phase shifter and control module thereof

Technical Field

The present disclosure relates to the field of communications, and in particular, to a phase shifter and a control module thereof.

Background

Phased array technology has wide application in millimeter wave communication, radar, etc. Phased array systems contain a large number of transceiver components, and the performance of the transceiver components can directly impact the performance of the phased array system. The transceiver component of the phased array system is mainly used for realizing functions of amplifying signals, controlling phase and amplitude changes of signals and the like, so that the traditional transceiver component generally comprises a power amplifier, a low noise amplifier, a phase shifter and a variable gain amplifier. In the conventional transceiver component, the phase shifter and the variable gain amplifier are discrete, i.e., the phase control and the amplitude control need to be implemented by at least two devices, resulting in defects of large device size and area and large power consumption.

Disclosure of Invention

The embodiment of the disclosure provides a phase shifter and a control module thereof.

In a first aspect, embodiments of the present disclosure provide a phase shifter, comprising: a quadrature signal generator for generating quadrature I-path signals and Q-path signals based on the differential input signals; the gain amplifying module comprises an I branch and a Q branch; the I branch comprises a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weight of the I-path signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on the received second gain control signal; the Q branch comprises a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weight of the Q-way signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-channel signal based on the received fourth gain control signal; and the vector synthesizer is used for carrying out vector summation on the signals output by the gain amplification module to obtain differential output signals.

In a second aspect, embodiments of the present disclosure provide a control module for outputting a first gain control signal to a fourth gain control signal to the phase shifter of any one of the first aspects; the control module is configured to: determining the phase and the amplitude of a target output signal based on the target signal, wherein the phase and the amplitude of the target signal have a corresponding relation with each other; and determining the first gain control signal to the fourth gain control signal based on the phase and the amplitude of the target output signal, wherein the phase of the target output signal has a corresponding relation with the first gain control signal and the third gain control signal, and the amplitude of the target output signal has a corresponding relation with the second gain control signal and the fourth gain control signal.

In the phase shifter of the embodiment of the disclosure, the phase shifter comprises a quadrature signal generator, a gain amplification module and a vector synthesizer, wherein the gain amplification module comprises an I branch and a Q branch which are respectively used for controlling phase weighting and amplitude weighting of the I-path signal and phase weighting and amplitude weighting of the Q-path signal; the I branch comprises a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weight of the I-path signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on the received second gain control signal; the Q branch comprises a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weight of the Q-way signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-channel signal based on the received fourth gain control signal; the signals output by the gain amplification module are input to a vector synthesizer, and the differential output signals are synthesized after vector summation of the vector synthesizer. The phase and amplitude of the differential output signal are modulated relative to the input signal of the quadrature signal generator, wherein the phase can be modulated by 360 degrees and the amplitude can be modulated by more than two gears.

In the scheme of the disclosure, the gain amplification module in the phase shifter can realize the modulation of the phase and the amplitude, and an additional gain amplifier is not required to be arranged outside the phase shifter for amplitude modulation; the phase shifter is used as a single module for modulating the phase and the amplitude at the same time, a matching circuit is not required to be arranged between every two units in the phase shifter, for example, a matching circuit is not required to be arranged between a first variable gain unit and a second variable gain unit, and a matching circuit is not required to be arranged between a third variable gain unit and a fourth variable gain unit, so that the matching circuit between a phase modulation part and an amplitude modulation part can be omitted, the chip area can be saved, and the power consumption can be saved.

Further, the second variable gain unit further includes a plurality of pairs of fixed gain transistors, the plurality of pairs of fixed gain transistors are used for providing fixed gain, the plurality of pairs of fixed gain transistors can compensate gain instability caused by different transistor sizes, and it is ensured that the second variable gain unit can achieve required gain.

Further, the gain ratio of the first variable gain unit to the third variable gain unit and the gain ratio of the second variable gain unit to the fourth variable gain unit are the same, that is, the ratio of the phase of the target I-path signal to the phase of the target Q-path signal is the same as the ratio of the amplitude of the target I-path signal to the amplitude of the target Q-path signal, which is advantageous for realizing that the second variable gain unit and the fourth variable gain unit perform amplitude weighting on the premise of unchanged phase.

Drawings

Fig. 1 is a schematic diagram showing a structure of a transceiver module in the related art;

Fig. 2 shows a schematic structural diagram of a phase shifter provided in an embodiment of the present disclosure;

fig. 3 is a schematic diagram illustrating a signal synthesis process of a phase shifter according to an embodiment of the present disclosure;

fig. 4A shows a schematic structural diagram of an I branch provided by an embodiment of the present disclosure;

fig. 4B illustrates a schematic structural diagram of a Q branch provided by an embodiment of the present disclosure;

fig. 5 shows a schematic structural diagram of a first variable gain unit provided by an embodiment of the present disclosure;

fig. 6 shows a schematic diagram of a second variable gain unit according to an embodiment of the present disclosure;

fig. 7 shows a schematic structural diagram of a gain amplifying module provided by an embodiment of the present disclosure;

fig. 8 shows a second schematic structural diagram of a second variable gain unit provided by an embodiment of the present disclosure;

FIG. 9 illustrates a control module block diagram provided by an embodiment of the present disclosure;

Fig. 10 shows a flowchart of a control method provided by an embodiment of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

The rapid development of phased array technology places increasing demands on the miniaturization of transceiver components. In the transceiver component, the integration of the rf front-end transceiver circuit is one of the most challenging designs. In general, the radio frequency front-end transceiver circuit not only requires performance indexes such as broadband, low insertion loss, high isolation, etc., but also requires a smaller size to achieve high integration.

In the related art, each antenna unit in a phased array circuit is provided with a transceiver component, and a plurality of transceiver components are combined to obtain a phased array. Fig. 1 is a schematic diagram showing the structure of a transceiver module in the related art. As shown in fig. 1, the transceiver component includes a transmit link and a receive link; the transmit and receive links are switched by the transmit and receive channel switches 101 and 108. The transmit chain comprises a power amplifier 102, a phase shifter 103 and a variable gain amplifier 104; the receive chain includes a low noise amplifier 105, a phase shifter 106, and a variable gain amplifier 107. The phase shifters 103 and 106 are used for realizing phase control of a transmitting link and a receiving link respectively, the variable gain amplifiers 104 and 107 are used for realizing amplitude control of the transmitting link and the receiving link respectively, the power amplifier 102 is used for realizing signal amplification of the transmitting link, and the low noise amplifier 105 is used for realizing signal amplification of the receiving link. In practical applications, the positions of the phase shifter and the variable gain amplifier may be interchanged. Also, a matching circuit is generally provided between the phase shifter and the variable gain amplifier, and the matching circuit is used for matching a transmission signal between the phase shifter and the variable gain amplifier.

Fig. 2 shows a schematic structural diagram of a phase shifter according to an embodiment of the present disclosure. As shown in fig. 2, an embodiment of the present disclosure provides a phase shifter including:

a quadrature signal generator 210 for generating quadrature I-path signals and Q-path signals based on the differential input signals;

A gain amplification module 220 comprising an I branch and a Q branch;

The I branch includes a first variable gain unit 221 and a second variable gain unit 222; the first variable gain unit 221 changes the phase weight of the I-path signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on the received second gain control signal;

The Q branch includes a third variable gain unit 223 and a fourth variable gain unit 224; the third variable gain unit changes the phase weight of the Q-way signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-channel signal based on the received fourth gain control signal;

the vector synthesizer 230 is configured to vector sum the signals output by the gain amplifying module 220 to obtain differential output signals.

It should be noted that, the first variable gain unit 221 to the fourth variable gain unit 224 in the gain amplifying module 220 illustrated in fig. 2 are only for illustrating the inclusion relationship, and are not used for defining the connection relationship between the first variable gain unit 221 to the fourth variable gain unit 224, and the specific connection relationship will be described in detail later.

It should be further noted that, in the embodiments of the present disclosure, the "amplitude weighting" may be an adjustment performed on the basis of the "phase weighting", that is, the "amplitude weighting" is performed first and then the "phase weighting"; or "phase weighting" may be an adjustment based on "amplitude weighting", that is, "amplitude weighting" followed by "phase weighting"; or "amplitude weighting" and "phase weighting" are performed in parallel.

Here, "phase weighting" means that by adjusting the amplitude of the orthogonal signal in the I direction and the Q direction, when the I-path signal and the Q-path signal are synthesized into a synthesized signal, the phase of the synthesized signal is adjusted, and the amplitude of the synthesized signal is unchanged, in other words, the phase of the synthesized signal is adjusted; by "amplitude weighting" is meant that by adjusting the amplitude in the I-direction and the Q-direction in the quadrature signal, the amplitude of the synthesized signal is adjusted when the I-way signal and the Q-way signal are synthesized into the synthesized signal, and the phase of the synthesized signal is unchanged, in other words, the amplitude of the synthesized signal is adjusted. In the embodiment of the disclosure, the phase weight of the I-path signal is changed by the first variable gain unit, and the phase weight of the Q-path signal is changed by the third variable gain unit, so as to realize the phase adjustment of the synthesized signal of the I-path signal and the Q-path signal; the amplitude weighting of the I-path signal is changed through the second variable gain unit, and the amplitude weighting of the Q-path signal is changed through the fourth variable gain unit, so that the amplitude adjustment of the combined signal of the I-path signal and the Q-path signal is realized.

The phase shifter comprises a quadrature signal generator, a gain amplification module and a vector synthesizer, wherein the gain amplification module comprises an I branch and a Q branch which are respectively used for controlling phase weighting and amplitude weighting of the I signal and phase weighting and amplitude weighting of the Q signal; the signals output by the gain amplification module are input to a vector synthesizer, and the differential output signals are synthesized after vector summation of the vector synthesizer. The differential output signal is modulated in both phase and amplitude with respect to the input signal of the quadrature signal generator.

Here, "vector summation" is to perform signal synthesis on the I-path signal and the Q-path signal to obtain a synthesized signal.

Further, in the scheme of the disclosure, the gain amplification module in the phase shifter can realize the modulation of the phase and the amplitude, and an additional gain amplifier is not required to be arranged outside the phase shifter for amplitude modulation; when the phase shifter is used as a single module to modulate the phase and the amplitude at the same time, a matching circuit is not required to be arranged between each unit in the phase shifter, for example, a matching circuit is not required to be arranged between the first variable gain unit and the second variable gain unit, and a matching circuit is not required to be arranged between the third variable gain unit and the fourth variable gain unit, so that the matching circuit between the phase modulation part and the amplitude modulation part can be omitted, the chip area can be saved, and the power consumption can be saved.

In an embodiment of the present disclosure, the phase shifter further includes: an input balun 240 and an output balun 250; wherein the input balun 240 is configured to convert a single-ended input signal into the differential input signal; the output balun 250 is used to convert the differential output signal to a single ended output signal.

In some embodiments, input balun 240 and output balun 250 are three-port devices that enable switching of single-ended signals (including single-ended input signals and single-ended output signals) and differential signals (including differential input signals and differential output signals). The single-ended input signal entering the phase shifter 200 is divided into two paths of in+ and In-differential input signals by the input balun 240, and four paths of quadrature signals (I-path signals and Q-path signals) of differential output are generated by the quadrature signal generator 210, namely, i+, I-, q+, Q-. The output terminals of the quadrature signal generator 210 include an i+ signal terminal, an I-signal terminal, a q+ signal terminal, and a Q-signal terminal.

In an embodiment of the present disclosure, the first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series.

In the case where the first variable gain unit and the second variable gain unit are connected in series and the third variable gain unit and the fourth variable gain unit are connected in series, the positions of the series connection of the first variable gain unit 221 and the second variable gain unit 222 may be interchanged, and the positions of the series connection of the third variable gain unit 223 and the fourth variable gain unit 224 may be interchanged. Fig. 2 illustrates only one positional relationship of the series connection.

In some embodiments, two input terminals of the first variable gain unit 221 are connected to the i+ signal terminal and the I-signal terminal of the quadrature signal generator, respectively, two input terminals of the second variable gain unit 222 are connected to two output terminals of the first variable gain unit 221, respectively, and two output terminals of the second variable gain unit 222 output the first quadrature signal and the second quadrature signal; two input terminals of the third variable gain unit 223 are connected to the q+ signal terminal and the Q-signal terminal of the quadrature signal generator 210, respectively, and two input terminals of the fourth variable gain unit 224 are connected to two output terminals of the third variable gain unit 223, respectively, and two output terminals of the fourth variable gain unit 224 output a third quadrature signal and a fourth quadrature signal.

In an embodiment of the disclosure, the second variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the first variable gain unit based on the second gain control signal; the fourth variable gain unit is configured to perform amplitude weighted adjustment of the signal output by the third variable gain unit based on the fourth gain control signal.

In some embodiments, the first variable gain unit 221 performs phase weight adjustment on the I-path signal to generate a first phase-shifted signal and a second phase-shifted signal; the second variable gain unit 222 performs amplitude weighting adjustment on the first phase-shifted signal and the second phase-shifted signal to generate a first quadrature signal and a second quadrature signal; the third variable gain unit 223 performs phase weight adjustment on the Q-path signal to generate a third phase-shifted signal and a fourth phase-shifted signal; the fourth variable gain unit 224 performs amplitude weighted adjustment on the Q-path phase-shifted signal to generate a third quadrature signal and a fourth quadrature signal; the I branch outputs a first orthogonal signal and a second orthogonal signal, and the Q branch outputs a third orthogonal signal and a fourth orthogonal signal.

In some embodiments, fig. 3 shows a schematic diagram of a signal synthesis process of a phase shifter according to an embodiment of the disclosure. In fig. 3, the "phase weighting" and then the "amplitude weighting" are taken as an example, and as shown in fig. 3, the gains of the first variable gain unit 221, the second variable gain unit 222, the third variable gain unit 223, and the fourth variable gain unit 224 are G1, G2, G3, and G4, respectively. Two input ends of the first variable gain unit 221 are respectively connected with an i+ signal end and an I-signal end, and a first phase-shifting signal and a second phase-shifting signal output by the first variable gain unit 221 are respectively g1×i+, g1×i-; two input ends of the second variable gain unit 222 are respectively connected with two output ends of the first variable gain unit 221, and the second variable gain unit 222 outputs a first orthogonal signal g2×g1×i+ and a second orthogonal signal g2×g1×i-; two input ends of the third variable gain unit 223 are respectively connected with a Q+ signal end and a Q-signal end, and a third phase-shifting signal and a fourth phase-shifting signal output by the third variable gain unit 223 are respectively G3×Q+, G3×Q-; two input terminals of the fourth variable gain unit 224 are connected to two output terminals of the third variable gain unit 223, respectively, and the fourth variable gain unit 224 outputs a third quadrature signal g4×g3×q+ and a fourth quadrature signal g4×g3×q-.

The vector synthesizer 230 performs I/Q vector synthesis on the first orthogonal signal g2×g1×i+ and the third orthogonal signal g4×g3×q+ to output a vector-synthesized differential output signal out+, and performs I/Q vector synthesis on the second orthogonal signal g2×g1×i-and the fourth orthogonal signal g4×g3×q-to output a vector-synthesized differential output signal Out-. The phase weight of the I-path signal is changed through the first variable gain unit, the phase weight of the Q-path signal is changed through the third variable gain unit, the amplitude weight of the I-path signal is changed through the second variable gain unit, and the amplitude weight of the Q-path signal is changed through the fourth variable gain unit on the basis of the phase weight, so that the common adjustment of the phase and the amplitude of the synthesized signal of the I-path signal and the Q-path signal obtained after vector summation is realized.

In the embodiment of the present disclosure, the first variable gain unit and the second variable gain unit may be further connected in parallel, and the third variable gain unit and the fourth variable gain unit may be further connected in parallel.

In some embodiments, the first variable gain unit performs phase weight adjustment on the I-path signal to generate a first phase-shifted signal and a second phase-shifted signal; the second variable gain unit performs amplitude weighted adjustment on the I-path signal to generate a first amplified signal and a second amplified signal; the first amplified signal and the second amplified signal have the same phase as the first phase-shifting signal and the second phase-shifting signal; the third variable gain unit performs phase weighting adjustment on the Q paths of signals to generate a third phase-shifting signal and a fourth phase-shifting signal; the fourth variable gain unit carries out amplitude weighted adjustment on the Q paths of signals to generate a third amplified signal and a fourth amplified signal; the third amplified signal and the fourth amplified signal have the same phase as the third phase-shifting signal and the fourth phase-shifting signal; the I branch outputs a first quadrature signal and a second quadrature signal which are obtained by superposing the gains of the first phase-shifting signal, the second phase-shifting signal, the first amplifying signal and the second amplifying signal, and the Q branch outputs a third quadrature signal and a fourth quadrature signal which are obtained by superposing the gains of the third phase-shifting signal, the fourth phase-shifting signal, the third amplifying signal and the fourth amplifying signal.

Fig. 4A shows a schematic structural diagram of an I branch provided by an embodiment of the present disclosure, and fig. 4B shows a schematic structural diagram of a Q branch provided by an embodiment of the present disclosure. As shown in fig. 4A and 4B, two input ends of the first variable gain unit 421 are connected to an i+ signal end and an I-signal end, respectively, two input ends of the second variable gain unit 422 are connected to an i+ signal end and an I-signal end, respectively, and two output ends of the first variable gain unit 421 are connected to two output ends of the second variable gain unit 422, respectively, to output a first quadrature signal and a second quadrature signal; two input ends of the third variable gain unit 423 are connected to the q+ signal end and the Q-signal end, respectively, and two input ends of the fourth variable gain unit 424 are connected to the q+ signal end and the Q-signal end, respectively, and after two output ends of the third variable gain unit 423 are connected to two output ends of the fourth variable gain unit 424, respectively, a third quadrature signal and a fourth quadrature signal are output.

In some embodiments, the gains of the first, second, third, and fourth variable gain units 421, 422, 423, and 424 are G1, G2, G3, and G4, respectively. Two input ends of the first variable gain unit 421 are respectively connected with an I+ signal end and an I-signal end, two input ends of the second variable gain unit 422 are respectively connected with the I+ signal end and the I-signal end, and a first phase-shifting signal and a second phase-shifting signal output by two output ends of the first variable gain unit 421 are respectively G1×I+, G1×I-; the first amplified signal and the second amplified signal output from the two output terminals of the second variable gain unit 422 are g2×i+, g2×i-, and the I branch outputs a first orthogonal signal (g2+g1) ×i+, and a second orthogonal signal (g2+g1) ×i-; two input ends of the third variable gain unit 423 are respectively connected with a Q+ signal end and a Q-signal end, two input ends of the fourth variable gain unit 424 are respectively connected with the Q+ signal end and the Q-signal end, and a third phase-shifting signal and a fourth phase-shifting signal output by two output ends of the third variable gain unit 423 are respectively G3×Q+, G3×Q-; the third amplified signal and the fourth amplified signal output from the two output terminals of the fourth variable gain unit 424 are g4×q+, g4×q-, and the third quadrature signal output from the Q branch is (g4+g3) ×q+ and the fourth quadrature signal (g4+g3) ×q-, respectively.

The vector synthesizer performs I/Q vector synthesis on the first quadrature signal (G2+G1) xI+ and the third quadrature signal (G4+G3) xQ+ to output a differential output signal Vout+ after vector synthesis, performs I/Q vector synthesis on the second quadrature signal (G2+G1) xI-and the fourth quadrature signal (G4+G3) xQ-, and outputs a differential output signal Vout-after vector synthesis.

In some embodiments, the first, second, third, and fourth Variable gain units may be Variable Gain Amplifiers (VGAs), GAIN AMPLIFIER.

Fig. 5 shows a schematic structural diagram of a first variable gain unit provided in an embodiment of the present disclosure, where, as shown in fig. 5, the first variable gain unit includes N first transistor units 310, and the N first transistor units 310 operate in parallel; the first variable gain unit implements phase weight control via one or more first transistor units 310 of the plurality of first transistor units 310; n is an integer greater than or equal to 2.

The first gain control signal includes N first control signals Va0-VaN-1 (only Va0 is shown in fig. 5 for clarity), each of which controls one first transistor cell. For example, the first control signal Va0 controls the first transistor cell, and the first control signal VaN-1 controls the Nth first transistor cell. Here, the first control signal may specifically be a voltage signal.

The first gain control signal includes N first control signals, and the first variable gain unit implements phase weight control via one or more of the plurality of first transistor units, so that the first variable gain unit can implement 2 ^N different gain states.

It should be noted that, fig. 5 illustrates a first transistor unit of the N first transistor units as an example, and the first transistor unit 310 includes a pair of first main transistors M1 and M4 and a pair of first cross-coupled transistors M2 and M3; the first main transistors M1 and M4 are connected to the first control signal Va0, and the first cross-coupled transistors M2 and M3 are connected to the inverted signal of the first control signal Va 0. Signals accessed by the first main transistors M1 and M4 and the first cross-coupled transistors M2 and M3 are respectively inverted by the inverter INV1 and the inverter INV 2. Wherein each of the N first transistor cells has the same structure.

In the embodiment of the disclosure, the transistors in the first transistor unit 310 may be connected in a common source manner, so that the gain may be improved and the parasitic phase shift may be reduced. Further, the first transistor unit 310 further includes a pair of first cross-coupled transistors M2 and M3, which can greatly reduce parasitic phase shift.

The gates of the first main transistor M1 and the first cross-coupling transistor M2 are connected to the i+ signal terminal, the gates of the first main transistor M4 and the first cross-coupling transistor M3 are connected to the I-signal terminal, the sources of the first main transistors M1, M4 and the first cross-coupling transistors M2, M3 are grounded, the drains of the first main transistor M1 and the first cross-coupling transistor M3 serve as the i+ output terminal of the first variable gain unit, and the drains of the first main transistor M4 and the first cross-coupling transistor M2 serve as the I-output terminal of the first variable gain unit.

The first transistor unit 310 further includes capacitors C1-C4 and resistors R1-R4, wherein the capacitors C1-C4 are filter capacitors and the resistors R1-R4 are filter resistors. The capacitances C1-C4 and the resistances R1-R4 form a filter network of the first transistor unit 310.

Fig. 6 shows a schematic diagram of a second variable gain unit according to an embodiment of the present disclosure, and as shown in fig. 6, the second variable gain unit includes M second transistor units 410.

The second gain control signal includes 2M second control signals Vb0-Vb2M-1 (only Vb0 and Vb1 are shown in fig. 6 for clarity), and each two of the 2M second control signals Vb0-Vb2M-1 controls one second transistor unit 410. For example, the second control signals Vb0 and Vb1 control the first second transistor unit, and the second control signals Vb2M-2 and Vb2M-1 control the Mth second transistor unit. Here, the second control signal may specifically be a voltage signal.

The second gain control signal includes 2M second control signals, and the second variable gain unit implements amplitude weighted adjustment in response to a difference between the two second control signals, so that the second variable gain unit can implement 2 ^M different gain states.

It should be noted that, fig. 6 illustrates a first one of the M second transistor units as an example, the first second transistor unit 410 includes a pair of second main transistors M5 and M8 and a pair of second cross-coupled transistors M6 and M7, and the first second variable gain unit 410 implements amplitude weighted adjustment in response to a difference between the second control signals Vb0 and Vb 1. Specifically, the second main transistors M5, M8 are coupled to the second control signal Vb0, the second cross-coupled transistors M6, M7 are coupled to the second control signal Vb1, and the first second variable gain unit 410 is responsive to (Vb 0-Vb 1) to effect amplitude weighted adjustment.

In the embodiment of the disclosure, the transistors in the second transistor unit 410 are connected in a common source manner, so that the gain can be improved and the parasitic phase shift can be reduced. Further, the second transistor unit 410 further includes a pair of second cross-coupled transistors M6, M7, which can greatly reduce parasitic phase shift.

The second transistor unit 410 may further include capacitors C5-C8 and resistors R5-R8, wherein the capacitors C5-C8 are filter capacitors and the resistors R5-R8 are filter resistors. The capacitances C5-C8 and the resistances R5-R8 form a filter network of the second transistor unit 410.

In the case that the first variable gain unit and the second variable gain unit are connected in parallel, the gates of the second main transistor M5 and the second cross-coupling transistor M6 are connected to the i+ signal terminal, the gates of the second main transistor M8 and the second cross-coupling transistor M7 are connected to the I-signal terminal, the sources of the second main transistors M5, M8 and the second cross-coupling transistors M6, M7 are grounded, the drains of the second main transistor M5 and the second cross-coupling transistor M7 serve as the i+ output terminal of the second variable gain unit, and the drains of the second main transistor M8 and the second cross-coupling transistor M6 serve as the I-output terminal of the second variable gain unit. The I+ output end of the first variable gain unit is connected with the I+ output end of the second variable gain unit, and then outputs a first orthogonal signal; the I-output end of the first variable gain unit is connected with the I-output end of the second variable gain unit, and then outputs a second orthogonal signal.

And under the condition that the first variable gain unit and the second variable gain unit are connected in series, a first current multiplexing circuit is arranged between the first variable gain unit and the second variable gain unit and is used for multiplexing the current of the first variable gain unit to the second variable gain unit, two input ends of the first current multiplexing circuit are connected with two output ends of the first variable gain unit, and two input ends of the second variable gain unit are connected with the output end of the first current multiplexing circuit. And under the condition that the third variable gain unit and the fourth variable gain unit are connected in series, a second current multiplexing circuit is arranged between the third variable gain unit and the fourth variable gain unit and is used for multiplexing the current of the third variable gain unit to the fourth variable gain unit, two input ends of the second current multiplexing circuit are connected with two output ends of the third variable gain unit, and two input ends of the fourth variable gain unit are connected with the output end of the second current multiplexing circuit. . Fig. 7 illustrates a schematic structural diagram of a gain amplifying module provided in an embodiment of the present disclosure, and as illustrated in fig. 7, a first current multiplexing circuit includes a first multiplexing unit 510 and a second multiplexing unit 520; an input terminal of the first multiplexing unit 510 is connected to an i+ output terminal of the first variable gain unit, and an input terminal of the second multiplexing unit 520 is connected to an I-output terminal of the first variable gain unit.

Specifically, the first multiplexing unit 510 includes a first ac branch and a first dc branch, and the second multiplexing unit 520 includes a second ac branch and a second dc branch; one end of the first alternating current branch is connected with the I+ output end of the first variable gain unit, and the other end of the first alternating current branch is connected with the gates of the second main transistor M5 'and the second cross coupling transistor M6'; one end of the second alternating current branch is connected with the I-output end of the first variable gain unit, and the other end of the second alternating current branch is connected with the gates of the second main transistor M8 'and the second cross coupling transistor M7'; one end of the first direct current branch is connected with the I+ output end of the first variable gain unit, and the other end of the first direct current branch is connected with sources of the second main transistor M5 'and the second cross coupling transistor M6'; one end of the second direct current branch is connected with the I-output end of the first variable gain unit, and the other end of the second direct current branch is connected with sources of the second main transistor M8 'and the second cross coupling transistor M7'.

In some embodiments, the first ac branch includes an inductance L1 and an inductance L5; the first dc branch comprises an inductance L3 and a capacitance C9. The second alternating current branch comprises an inductor L2 and an inductor L6; the second dc branch comprises an inductance L4 and a capacitance C10. The capacitance values of the capacitor C9 and the capacitor C10 are larger, so that the effects of isolating direct current signals and allowing alternating current signals to pass through are achieved. And the inductances L1, L3, L5 in the first multiplexing unit 510 and the inductances L2, L4, L6 in the second multiplexing unit 520 are also used to achieve input/output matching between the first variable gain unit and the second variable gain unit.

In the embodiment of the disclosure, the voltage division effect of the VDD power supply voltage can be realized by using the first current multiplexing circuit and the second current multiplexing circuit, thereby meeting the application of the high power supply voltage. For example, the drain electrode of the transistor in the first variable gain unit can be connected with the VDD power supply voltage, the source electrode of the transistor in the second variable gain unit is grounded, the transistors in the first variable gain unit and the second variable gain unit realize voltage division, and the high voltage resistance of the whole circuit is improved.

In some embodiments, the impedance of the first ac branch is less than the impedance of the first dc branch; the impedance of the second ac branch is smaller than that of the second dc branch, so that the radio frequency signal can be fed from the gate of the transistor in the second variable gain unit, so as to realize the common-source connection relationship of the transistors in the second variable gain unit and realize high gain.

In the embodiment of the disclosure, the signal output by the first variable gain unit is fed from the gates of the second main transistors M5', M8' and the second cross-coupling transistors M6', M7' through the ac branches (the first ac branch and the second ac branch), so as to realize the common-source connection structure of the second main transistors M5', M8' and the second cross-coupling transistors M6', M7' in the second variable gain unit, so that parasitic phase shift can be reduced, and high gain can be realized.

In an embodiment of the disclosure, the first current multiplexing circuit divides a drain voltage of a transistor in the first variable gain unit to a source of a transistor in the second variable gain unit, thereby multiplexing a current of the first variable gain unit to the second variable gain unit.

It should be noted that the structures of the second current multiplexing circuit and the first current multiplexing circuit are the same, and the connection relationship between the second current multiplexing circuit and the third variable gain unit and the fourth variable gain unit can be understood by referring to the connection relationship between the first current multiplexing circuit and the first variable gain unit and the second variable gain unit, which are not described herein again.

As shown in fig. 7, the second variable gain unit includes N second transistor units 610, and the N second transistor units 610 operate in parallel; the second variable gain unit implements phase weight control via one or more second transistor units 610 of the plurality of second transistor units 610; n is an integer greater than or equal to 2.

The second gain control signal includes N second control signals Vb0-VbN-1, each of which controls one second transistor unit. For example, the second control signal Vb0 controls the first second transistor unit, and the second control signal VbN-1 controls the nth second transistor unit. Here, the second control signal may specifically be a voltage signal.

The second gain control signal includes N second control signals, and the second variable gain unit implements phase weight control via one or more second transistor units of the plurality of second transistor units, so that the second variable gain unit can implement 2 ^N different gain states.

It should be noted that, fig. 7 illustrates a first one of the N second transistor units as an example, the first second transistor unit 610 includes a pair of second main transistors M5', M8' and a pair of second cross-coupled transistors M6', M7'; the second main transistors M5', M8' are connected to the second control signal Vb0, and the second cross-coupled transistors M6', M7' are connected to the inverse signal of the second control signal Vb 0. Signals accessed by the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' are inverted by the inverter INV3 and the inverter INV4, respectively. Wherein each of the N second transistor units has the same structure.

The gates of the second main transistor M5 'and the second cross-coupling transistor M6' are connected to the output terminal of the first multiplexing unit 510, the gates of the second main transistor M8 'and the second cross-coupling transistor M7' are connected to the output terminal of the second multiplexing unit 520, the drains of the second main transistor M5 'and the second cross-coupling transistor M7' serve as the i+ output terminal of the second variable gain unit to output the first quadrature signal, and the drains of the second main transistor M8 'and the second cross-coupling transistor M6' serve as the I-output terminal of the second variable gain unit to output the second quadrature signal.

In the embodiment of the disclosure, the transistors in the second transistor unit 610 are connected in a common source manner, so that the gain can be improved and the parasitic phase shift can be reduced. Further, the second transistor unit 610 further includes a pair of second cross-coupled transistors M6', M7', which can greatly reduce parasitic phase shift.

The second transistor unit 610 further includes a capacitor C5'-C8', and a resistor R5'-R8', wherein the capacitor C5'-C8' is a filter capacitor, and the resistor R5'-R8' is a filter resistor. The capacitor C5'-C8' and the resistor R5'-R8' form a filter network of the second transistor unit 610.

In an embodiment of the present disclosure, the first variable gain unit includes M first transistor units; the first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; the first gain control signals comprise 2M first control signals, each two first control signals in the 2M first control signals control one first transistor unit, and the first main transistor and the first cross-coupling transistor are respectively connected with two different first control signals; the first variable gain unit is responsive to a difference between the two first control signals to effect an amplitude weighted adjustment; m is an integer greater than or equal to 1.

In the embodiment of the disclosure, the transistors in the first transistor unit are connected in a common source manner, so that the gain can be improved, and the parasitic phase shift can be reduced. Further, the first transistor unit further includes a pair of first cross-coupled transistors, which can greatly reduce parasitic phase shift.

In other embodiments, the first variable gain unit and the second variable gain unit are identical in structure. Specifically, the first variable gain unit and the second variable gain unit shown in fig. 6 have the same structure. In this manner, in the case where the structures of the first variable gain unit and the second variable gain unit are the same, the specific circuit structure of the first variable gain unit may be understood with reference to the structure of the second variable gain unit shown in fig. 6, and the description thereof will not be repeated.

In an embodiment of the present disclosure, the second variable gain unit further includes a plurality of pairs of fixed gain transistors; the grid electrode of the fixed gain transistor is connected with a fixed voltage, and the source electrode and the drain electrode of each pair of fixed gain transistors are respectively connected with the source electrode and the drain electrode of the second main transistor.

Fig. 8 shows a second schematic structural diagram of a second variable gain unit according to an embodiment of the present disclosure, where, as shown in fig. 8, the second variable gain unit includes N second transistor units 610, and the N second transistor units 610 operate in parallel; the second variable gain unit implements phase weight control via one or more second transistor units 610 of the plurality of second transistor units 610; n is an integer greater than or equal to 2.

It should be noted that, fig. 8 illustrates a first one of the N second transistor units as an example, the first second transistor unit 610 includes a pair of second main transistors M5', M8' and a pair of second cross-coupled transistors M6', M7'; the second main transistors M5', M8' are connected to the second control signal Vb0, and the second cross-coupled transistors M6', M7' are connected to the inverse signal of the second control signal Vb 0. Signals accessed by the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' are inverted by the inverter INV3 and the inverter INV4, respectively. Wherein each of the N second transistor units has the same structure.

The second variable gain unit 610 further includes a plurality of pairs of fixed gain transistors, for example, a pair of fixed gain transistors M9 and M10 are illustrated, the gates of the fixed gain transistors M9 and M10 are connected to a fixed voltage Vc, and the sources of the fixed gain transistors M9 and M10 are connected to the sources of the second main transistors M5', M8' and the second cross-coupled transistors M6', M7', so as to form a common source connection structure. The drain electrode of the fixed gain transistor M9 is connected with the drain electrodes of the second main transistor M5 'and the second cross coupling transistor M7', and is used as an I+ output end of the second variable gain unit together to output a first quadrature signal; the drain of the fixed gain transistor M10 is connected to the drains of the second main transistor M8 'and the second cross-coupled transistor M6', and together serves as an I-output of the second variable gain unit, outputting a second quadrature signal.

In embodiments of the present disclosure, multiple pairs of fixed gain transistors are used to provide a fixed gain. In a specific example, by selectively setting the number of pairs of fixed gain transistors and the transistor parameters, the gain variation of the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' can be made to be 1/2 of the gain step of the first variable gain unit.

In other embodiments, the structure of the second variable gain unit may be the same as that of the second variable gain unit shown in fig. 6. As such, in the case where the second variable gain unit further includes a plurality of pairs of fixed gain transistors, the specific circuit structure of the second variable gain unit may be understood in conjunction with the structures shown in fig. 6 and 8, and will not be described herein.

In some embodiments, the I and Q branches are identical in structure.

In the embodiment of the present disclosure, the third variable gain unit and the first variable gain unit have the same structure and the same connection manner.

Specifically, the third variable gain unit has the same structure as the first variable gain unit shown in fig. 5. In this way, in the case where the structures of the third variable gain unit and the first variable gain unit are the same, the specific circuit structure and connection manner of the third variable gain unit may be understood with reference to the structure of the first variable gain unit shown in fig. 5, and will not be described herein.

In the embodiment of the present disclosure, the fourth variable gain unit and the second variable gain unit are identical in structure and identical in connection.

Specifically, the fourth variable gain unit has the same structure as the second variable gain unit shown in fig. 6 or 8. In this way, in the case where the structures of the fourth variable gain unit and the second variable gain unit are the same, the specific circuit structure and connection manner of the fourth variable gain unit may be understood with reference to the structure of the second variable gain unit shown in fig. 6 or fig. 8, and will not be described herein.

In some embodiments, the ratio of the control bits of the first gain control signal to the control bits of the third gain control signal and the ratio of the control bits of the second gain control signal to the control bits of the fourth gain control signal are the same. In this way, the second variable gain unit and the fourth variable gain unit in the embodiments of the present disclosure may perform amplitude weighting on the premise that the phase is unchanged.

In the embodiment of the present disclosure, the gain ratio of the first variable gain unit to the third variable gain unit and the gain ratio of the second variable gain unit to the fourth variable gain unit are the same.

In some embodiments, the ratio of the phase of the I signal to the phase of the Q signal is the same as the ratio of the amplitude of the I signal to the amplitude of the Q signal. In other words, the second variable gain unit and the fourth variable gain unit in the embodiments of the present disclosure perform amplitude weighting on the premise that the phase is unchanged.

For "phase weighting", the phase of the combined signal of the first and second phase-shifted signals generated by the first variable gain unit and the third and fourth phase-shifted signals generated by the third variable gain unit isAmplitude isWhere G1 is the gain of the first variable gain unit of the I branch and G3 is the gain of the third variable gain unit of the Q branch.

The phase of the differential output signal Out+, out-obtained by I/Q vector synthesis via the vector synthesizer isWhere G1 is the gain of the first variable gain unit of the I branch and G3 is the gain of the third variable gain unit of the Q branch. The differential output signal Vout+, vout-obtained by I/Q vector synthesis via the vector synthesizer has an amplitude ofWhere G2 is the gain of the second variable gain unit of the I branch and G4 is the gain of the fourth variable gain unit of the Q branch. The differential output signal out+, out-obtained after I/Q vector synthesis via the vector synthesizer also needs to satisfy the relation: 20lg ((r2+r1)/R1) = deltaG, wherein deltaG represents the difference in dB coordinate system between different gain states minus the initial gain state. In order for the gain control to meet the dB linear relationship, for one Xbit-demanded gain control requirement, deltaG =k1×a should be made, where K1 is the minimum gain step required for gain control and K1 is a constant. a=0, 1,2,..2 ^X.

The gains of the first to fourth variable gain units in the phase shifter depend on the first to fourth gain control signals. In a physical sense, the phase shifter has only one state at the same time, and can be controlled to form different control states by different first gain control signals to fourth gain control signals, and the phase shifter is shifted to any specific phase shifting quantity based on a stepping value in a phase shifting range. For Xbit's phase shifter, the step value of its phase shift is 360/(2 ^X). In a specific example, the 6Bit phase shifter has a 64 Bit state with a step value of 5.625 ° phase shift, a phase shift amount corresponding to the 1 st state of 5.625 °, and a phase shift amount corresponding to the 31 st state of 174.375 °.

It should be noted that the above description of the structures of the first to fourth variable gain units is only an exemplary description of the present disclosure, and the structures of the first to fourth variable gain units of the present disclosure are not limited to the above structures, and other devices that can realize variable gains may be applied to the present disclosure.

In an embodiment of the present disclosure, there is further provided a control module configured to output the first gain control signal to the fourth gain control signal to the phase shifter in the above embodiment; the control module is configured to:

Determining the phase and the amplitude of a target output signal based on the target signal, wherein the phase and the amplitude of the target signal have a corresponding relation with each other; the target signal is a preset value, and is a preset value under different phases and/or different amplitudes of the target output signal. For example, when the phase of the target output signal is a first phase value and the amplitude is a first amplitude value, the target signal is a first target signal; when the phase of the target output signal is a second phase value, the amplitude is a second amplitude value, the target signal is a second target signal, and so on. The target signal is used to indicate the phase and amplitude of the target output signal, which may be obtained based on the phase and/or amplitude of the phased array beam, e.g., the phase and amplitude of the signal in each transmit or receive chain, to obtain the target signal. The target signal may be a code-decoder (codec) sent to the control module, where the codec may determine a phase and an amplitude of a link signal where the phase shifter is located, so as to obtain a target signal corresponding to the phase shifter. The target signal may be a digital signal, where the target signal directly includes a phase value and an amplitude value of the target output signal, for example, phase value 0101 indicates that the phase of the target output signal is 45 °, phase value 0111 indicates that the phase of the target output signal is 60 °, amplitude value 0011 indicates that the amplitude of the target output signal is f2, and so on; or the target signal contains code values, different code values corresponding to different phase values and amplitude values, e.g. code value 0001 indicates that the phase of the target output signal is 0 °, the amplitude is f3, code value 0010 indicates that the phase of the target output signal is 10 °, the amplitude is f4, etc. The target output signal is the target of the differential output signal adjustment, and the phase and/or amplitude of the differential output signal is the same or substantially the same as the phase and/or amplitude of the target output signal.

Determining first to fourth gain control signals based on a phase and an amplitude of a target output signal, the phase of the target output signal having a correspondence with the first and third gain control signals for adjusting phase weights of the first and third variable gain units; the amplitude of the target output signal has a correspondence with the second gain control signal and the fourth gain control signal for adjusting the amplitude weights of the second variable gain unit and the fourth variable gain unit.

The target signal is a signal output by the phase shifter under the control of the control module, the target output signal is a signal output by a vector synthesizer in the phase shifter under the control of the control module, and the target output signal is a differential output signal. In other words, under the control of the control module, the phase and amplitude of the signal output by the phase shifter are the same as the phase and amplitude of the target signal, and the phase and amplitude of the differential output signal output by the vector synthesizer in the phase shifter are the same as the phase and amplitude of the target output signal.

In the embodiment of the disclosure, the control logic is split into the control logic for controlling the phase and the control logic for controlling the amplitude by arranging the phase shifter with the phase and the amplitude modulation functions. The larger the number of bits of the control logic, the larger the parasitic capacitance, the larger the matching loss, and the lower the gain. Thus, by means of this control logic splitting, a high gain can be achieved.

In an embodiment of the present disclosure, fig. 9 shows a control module block diagram provided by an embodiment of the present disclosure, and as shown in fig. 9, a control module 700 includes a phase control module 710 and an amplitude control module 720; wherein the phase control module 710 is configured to: determining phase weighting of a target I path signal and phase weighting of a target Q path signal according to the phase of a target output signal; determining a first gain control signal and a third gain control signal based on the phase weighting of the target I signal and the phase weighting of the target Q signal; the amplitude control module 720 is configured to: determining the amplitude weighting of the target I path signal and the amplitude weighting of the target Q path signal according to the amplitude of the target output signal under the phase and the amplitude under the phase; the second gain control signal and the fourth gain control signal are determined based on the amplitude weighting of the target I signal and the amplitude weighting of the target Q signal.

Fig. 10 shows a flowchart of a control method provided by an embodiment of the present disclosure, where, as shown in fig. 10, the control method includes:

Step 801: determining the phase and the amplitude of a target output signal based on the target signal, wherein the phase and the amplitude of the target signal have a corresponding relation with each other;

Step 802: determining phase weighting of a target I path signal and phase weighting of a target Q path signal according to the phase of a target output signal; determining a first gain control signal and a third gain control signal based on the phase weighting of the target I signal and the phase weighting of the target Q signal;

Step 803: determining the amplitude weighting of the target I path signal and the amplitude weighting of the target Q path signal according to the amplitude of the target output signal under the phase and the amplitude under the phase; the second gain control signal and the fourth gain control signal are determined based on the amplitude weighting of the target I signal and the amplitude weighting of the target Q signal.

It should be noted that, step 802 is performed by the phase control module 710, step 803 is performed by the amplitude control module 720, there is no explicit sequence relationship between step 802 and step 803, and step 802 and step 803 may be performed in parallel.

In some embodiments, the first gain control signal is configured to control a phase of a target I signal output by the first variable gain unit, and the third gain control signal is configured to control a phase of a target Q signal output by the third variable gain unit, so that a phase of a differential output signal obtained by performing I/Q vector synthesis based on the target I signal and the target Q signal is the same as a phase of the target output signal. The second gain control signal is used for controlling the amplitude of the target I path signal output by the second variable gain unit, and the fourth gain control signal is used for controlling the amplitude of the target Q path signal output by the fourth variable gain unit, so that the amplitude of the differential output signal obtained after the I/Q vector synthesis based on the target I path signal and the target Q path signal is the same as the amplitude of the target output signal.

In the embodiment of the disclosure, the ratio of the control bit of the first gain control signal to the control bit of the third gain control signal is the same as the ratio of the control bit of the second gain control signal to the control bit of the fourth gain control signal.

In a specific example, the control bit of the first gain control signal is w, the control bit of the second gain control signal is x, the control bit of the third gain control signal is y, the control bit of the fourth gain control signal is z, and the control bits of the first gain control signal to the fourth gain control signal need to satisfy w/x=y/z.

Since the gain of the VGA is proportional to its control bit, the gains of the first, second, third and fourth variable gain units at this time can be expressed as g1=kw, g2=kx, g3=ky, g4=kz, respectively. Where k is a constant. For a 6bit resolution phase shifter having 64 bit states, the corresponding gains for states 1 through 32 can be expressed as g1=kw, g2=kx, g3=ky, g4=kz, where w, x, y, z=0, 1,2,; the gains corresponding to states 33-64 may be expressed as g1=k (x-32), g2=k (n-32), g3=k (y-32), g4=k (m-32), where x, n, y, m=32, 33, 34,..63, respectively.

In some embodiments, since the gain of the VGA is proportional to its control bit, the gain ratio of the first variable gain unit to the third variable gain unit and the gain ratio of the second variable gain unit to the fourth variable gain unit are the same. In other words, the ratio of the phase of the target I-way signal to the phase of the target Q-way signal is the same as the ratio of the amplitude of the target I-way signal to the amplitude of the target Q-way signal. In the embodiment of the disclosure, the second variable gain unit and the fourth variable gain unit perform amplitude weighting on the premise of unchanged phase.

In the embodiment of the disclosure, as shown in fig. 9, the control module 700 further includes a numerical control module 730 and a DAC module 740, the numerical control module 730 provides a digital signal to the DAC module, the DAC module 740 converts the digital signal into a corresponding control signal, and the DAC module 740 outputs the control signal to the gain amplifying module. In a specific example, the DAC module 740 outputs the first gain control signal to the first variable gain unit, outputs the second gain control signal to the second variable gain unit, outputs the third gain control signal to the third variable gain unit, and outputs the fourth gain control signal to the fourth variable gain unit; wherein the first gain control signal comprises N first control signals, the second gain control signal comprises 2M second control signals, the third gain control signal comprises N third control signals, and the fourth gain control signal comprises 2M fourth control signals. Each of the first control signal to the fourth control signal corresponds to a control voltage for controlling on and off of the corresponding transistor. Here, each of the first control signal and the third control signal corresponds to one control bit, each of the second control signal and the fourth control signal corresponds to one control bit, in other words, each control bit corresponds to one control voltage, when the control bit is low, the corresponding control voltage is an off voltage, the off voltage turns off the transistor, and when the control bit is high, the corresponding control voltage is an on voltage of the transistor, the on voltage turns on the transistor. The number of transistors which are turned off and on in the first to fourth variable gain units is controlled by a digital signal, so that the gains of the first to fourth variable gain units are changed.

With the increase of control bits, the parasitic capacitance of the gain amplification module is exponentially increased, the loss of output matching is large, and the gain of the whole circuit is reduced. In the case where the first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series, the digital signal/control signal of the gain amplification module may be split into multiple stages, for example, for the I branch, into two stages, which are the digital signal/control signal of the first variable gain unit and the digital signal/control signal of the second variable gain unit, respectively. Therefore, parasitic capacitance of the gain amplifying module can be reduced, and high gain is realized.

In the phase shifter of the embodiment of the disclosure, the phase shifter comprises a quadrature signal generator, a gain amplification module and a vector synthesizer, wherein the gain amplification module comprises an I branch and a Q branch which are respectively used for controlling phase weighting and amplitude weighting of the I-path signal and phase weighting and amplitude weighting of the Q-path signal; the I branch comprises a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weight of the I-path signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on the received second gain control signal; the Q branch comprises a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weight of the Q-way signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-channel signal based on the received fourth gain control signal; the signals output by the gain amplification module are input to a vector synthesizer, and the differential output signals are synthesized after vector summation of the vector synthesizer. The differential output signal is modulated in both phase and amplitude with respect to the input signal of the quadrature signal generator.

In the scheme of the application, the gain amplification module in the phase shifter can realize the modulation of the phase and the amplitude, and an additional gain amplifier is not required to be arranged outside the phase shifter for amplitude modulation; the phase shifter is used as a single module for modulating the phase and the amplitude at the same time, a matching circuit is not required to be arranged between every two units in the phase shifter, for example, a matching circuit is not required to be arranged between a first variable gain unit and a second variable gain unit, and a matching circuit is not required to be arranged between a third variable gain unit and a fourth variable gain unit, so that the matching circuit between a phase modulation part and an amplitude modulation part can be omitted, the chip area can be saved, and the power consumption can be saved.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims

1. A phase shifter, comprising:

An orthogonal signal generator, used for generating an orthogonal I-channel signal and a Q-channel signal based on a differential input signal;

A gain amplifier module, including an I branch and a Q branch;

The I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I signal based on the received second gain control signal;

The Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q branch signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q branch signal based on the received fourth gain control signal;

The vector synthesizer is used to perform vector summation on the signals output by the gain amplification module to obtain a differential output signal.

2. The phase shifter according to claim 1, characterized in that:

The first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series.

3. The phase shifter according to claim 2, characterized in that:

The second variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the first variable gain unit based on the second gain control signal;

The fourth variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the third variable gain unit based on the fourth gain control signal.

4. The phase shifter according to claim 2, characterized in that:

The I branch further includes a first current multiplexing circuit, configured to multiplex the current of the first variable gain unit to the second variable gain unit;

The Q branch further includes a second current multiplexing circuit for multiplexing the current of the third variable gain unit to the fourth variable gain unit.

5. The phase shifter according to claim 1, characterized in that:

The first variable gain unit and the second variable gain unit are connected in parallel, and the third variable gain unit and the fourth variable gain unit are connected in parallel.

6. The phase shifter according to claim 1, characterized in that:

The first variable gain unit includes N first transistor units, and the N first transistor units work in parallel; the first variable gain unit implements phase weighted control via one or more first transistor units among the plurality of the first transistor units; N is an integer greater than or equal to 2;

The first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; wherein the first gain control signal includes N first control signals, each first control signal controls one of the first transistor units; one of the first main transistor and the first cross-coupled transistor is connected to the first control signal, and the other is connected to the inverted first control signal.

7. The phase shifter according to claim 1, characterized in that:

The first variable gain unit includes M first transistor units; the first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; wherein the first gain control signal includes 2M first control signals, each two first control signals of the 2M first control signals control one first transistor unit, and the first main transistor and the first cross-coupled transistor are respectively connected to two different first control signals; the first variable gain unit realizes amplitude weighted adjustment in response to the difference between the two first control signals; M is an integer greater than or equal to 1.

8. The phase shifter according to claim 1, characterized in that

The second variable gain unit includes M second transistor units; the second transistor unit includes a pair of second main transistors and a pair of second cross-coupled transistors; wherein the second gain control signal includes 2M second control signals, every two second control signals of the 2M second control signals control one second transistor unit, and the second main transistor and the second cross-coupled transistor are respectively connected to two different second control signals; the second variable gain unit realizes amplitude weighted adjustment in response to the difference between the two second control signals; M is an integer greater than or equal to 1.

9. The phase shifter according to claim 1, characterized in that:

The second variable gain unit includes N second transistor units, and the N second transistor units work in parallel; the second variable gain unit implements phase weighted control via one or more second transistor units among the plurality of the second transistor units; N is an integer greater than or equal to 2;

The second transistor unit includes a pair of second main transistors and a pair of second cross-coupled transistors; wherein the second gain control signal includes N second control signals, each second control signal controls one second transistor unit; one of the second main transistor and the second cross-coupled transistor is connected to the second control signal, and the other is connected to the inverted second control signal.

10. The phase shifter according to claim 8 or 9, characterized in that the second variable gain unit further comprises a plurality of pairs of fixed gain transistors; the gates of the fixed gain transistors are connected to a fixed voltage, and the source and drain of each pair of the fixed gain transistors are respectively connected to the source and drain of the second main transistor.

11. The phase shifter according to claim 6 or 7, characterized in that:

The third variable gain unit has the same structure as the first variable gain unit.

12. The phase shifter according to any one of claims 1 to 9, characterized in that:

The fourth variable gain unit has the same structure as the second variable gain unit.

13. The phase shifter according to any one of claims 1 to 5, further comprising: an input balun and an output balun; wherein:

The input balun is used to convert the single-ended input signal into the differential input signal;

The output balun is used to convert the differential output signal into a single-ended output signal.

14 . The phase shifter according to claim 1 , wherein a gain ratio between the first variable gain unit and the third variable gain unit is the same as a gain ratio between the second variable gain unit and the fourth variable gain unit.

15. A control module, characterized in that it is used to output the first gain control signal to the fourth gain control signal to the phase shifter according to any one of claims 1 to 14; the control module is configured to:

Based on the target signal, determining the phase and amplitude of the target output signal, wherein the target signal has a corresponding relationship with the phase and amplitude of the target output signal;

Based on the phase and amplitude of the target output signal, the first gain control signal to the fourth gain control signal are determined, the phase of the target output signal has a corresponding relationship with the first gain control signal and the third gain control signal, and the amplitude of the target output signal has a corresponding relationship with the second gain control signal and the fourth gain control signal.

16. The control module according to claim 15, characterized in that it comprises a phase control module and an amplitude control module; wherein:

The phase control module is used to: determine the phase weighting of the target I-path signal and the phase weighting of the target Q-path signal according to the phase of the target output signal; determine the first gain control signal and the third gain control signal based on the phase weighting of the target I-path signal and the phase weighting of the target Q-path signal;

The amplitude control module is used to: determine the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal according to the amplitude of the target output signal at the phase and the amplitude at the phase; determine the second gain control signal and the fourth gain control signal based on the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal.

17 . The control module according to claim 15 , wherein a ratio of a control bit of the first gain control signal to a control bit of the third gain control signal is the same as a ratio of a control bit of the second gain control signal to a control bit of the fourth gain control signal.