CN118693771A - Electrostatic discharge protection circuit and electronic device including the same - Google Patents

Abstract

An electrostatic discharge protection circuit and an electronic device including the electrostatic discharge protection circuit are disclosed. The electrostatic discharge protection circuit includes: an NMOS transistor connected to a power supply voltage pin through a first node and to a ground pin through a second node; an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor; and a clamp circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamp circuit to a gate node of the NMOS transistor, wherein the number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor and a sub-RC circuit, the PMOS transistor connecting the gate node of the NMOS transistor to the clamp circuit, the sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

Description

Electrostatic discharge protection circuit and electronic device including the same

This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0038950 filed on March 24, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0054968 filed on April 26, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference.

Technical Field

The disclosure relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to a high voltage ESD protection circuit and an electronic device including the ESD protection circuit.

Background Art

ESD, a type of electrical overstress (EOS, or simply referred to as overstress), refers to a phenomenon in which static charge accumulated between two objects having an electric charge is transferred due to the triboelectric effect. ESD events in semiconductors at very small scales can involve high current and high voltage characteristics in a very short period of time, which can lead to malfunction and destruction of circuits.

Various devices such as silicon controlled rectifiers (SCRs), gate grounded n-type metal oxide semiconductors (GGNMOSs), and gate coupled NMOSs (GCNMOSs) have been used as ESD protection devices to prevent ESD events in advance. Although SCRs have high current driving capability and excellent tolerance characteristics per unit area, SCRs can be difficult to use when the internal circuit operates at a low voltage, and undesired conduction occurs. Although GGNMOSs are easy to manufacture and control, they can be susceptible to thermal degradation.

Summary of the invention

An electrostatic discharge (ESD) protection circuit and an electronic device including the ESD protection circuit are disclosed, which can control the number of diodes of a clamp circuit so that a trigger voltage of an NMOS transistor is between an operating voltage of a peripheral circuit and a breakdown voltage of the peripheral circuit.

The disclosure also provides an ESD protection circuit and an electronic device including the ESD protection circuit, which are capable of preventing degradation of ESD performance by adding a gate-coupled GCPMOS switch in series to a clamping circuit.

According to one aspect of an example embodiment, an ESD protection circuit is provided, which may include: an n-type metal oxide semiconductor (NMOS) transistor connected to a power supply voltage pin through a first node and to a ground pin through a second node; a resistor-capacitor (RC) circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor; and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein the number of the plurality of diodes is determined based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and wherein the switch includes: a p-type metal oxide semiconductor (PMOS) transistor connecting the gate node of the NMOS transistor to the clamping circuit; and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

According to one aspect of an example embodiment, an electronic device is provided, the electronic device may include: an internal circuit connected to a power supply voltage pin through a first node, connected to a ground pin through a second node, and configured to send or receive data through a plurality of input/output (I/O) pins; a first ESD protection circuit connected between the first node and the second node; and a plurality of second ESD protection circuits connected to each of the plurality of I/O pins, wherein the first ESD protection circuit includes: a first n-type metal oxide semiconductor (NMOS) transistor including a drain terminal connected to the first node and a source terminal connected to the second node; a first RC circuit, A first clamp circuit connected in parallel with the first NMOS transistor and including a capacitor and a resistor; a first clamp circuit connected in parallel with the resistor of the first RC circuit and including a plurality of first diodes; and a switch connected in series with the first clamp circuit and connected to a third node corresponding to the gate terminal of the NMOS transistor, wherein the switch includes a p-type metal oxide semiconductor (PMOS) transistor and a sub-RC circuit, the PMOS transistor connecting the third node to the clamp circuit, the sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor, and wherein the number of the plurality of first diodes is determined based on a breakdown voltage and an operating voltage of the internal circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an integrated circuit (IC) chip including an electrostatic discharge (ESD) protection circuit according to an embodiment;

FIG. 2 shows an ESD protection circuit according to an embodiment;

3 is a graph showing IV curves of drain voltage and drain current of an ESD protection circuit according to an embodiment;

FIG4 is a graph showing an ESD design window according to an embodiment;

FIG5 shows an ESD protection circuit according to an embodiment;

6 is a graph showing a relationship between a gate voltage and a trigger voltage of an NMOS transistor NT of an ESD protection circuit 500 according to an embodiment;

FIG. 7 illustrates an example of determining the number of diodes of a clamp circuit according to an embodiment;

FIG8 illustrates an ESD protection circuit according to one or more embodiments;

9 is a graph showing a voltage level of each node in each of an ESD event and a normal operation event according to an embodiment;

10 is a graph showing improvement in margin in each of an ESD event and a normal operation event according to an embodiment; and

FIG. 11 illustrates an example of an electronic device according to an embodiment.

DETAILED DESCRIPTION

Hereinafter, embodiments are described in detail with reference to the accompanying drawings. It should be understood that the embodiments described herein are example embodiments, and therefore, the disclosure may not be limited thereto.

It will be understood that although the terms first, second, third, fourth, etc. may be used herein to describe various circuit elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, a first element described in the specification section may be referred to as a second element in the claims section.

FIG. 1 illustrates an integrated circuit (IC) chip 100 including an electrostatic discharge (ESD) protection circuit according to an embodiment.

1 , an IC chip 100 may include an input/output (I/O) pin 110 , a power pin 120 , an internal circuit 130 , and a plurality of ESD protection circuits 111 , 112 , and 121 .

The I/O pins 110 may include an input pin for receiving input data to be received by the IC chip 100 and an output pin for sending output data to the outside of the IC chip 100. The I/O pins 110 may be connected to the internal circuit 130. According to an embodiment, the ESD protection circuits 111 and 112 may be connected to the I/O pins 110, respectively. For example, the ESD protection circuit 111 may be connected to an input data path that connects the input pin to the internal circuit 130. The ESD protection circuit 111 provided on the input data path may be a circuit for discharging the ESD applied to the input pin to the ground. As another example, the ESD protection circuit 112 may be connected to an output data path that connects the output pin to the internal circuit 130. The ESD protection circuit 112 provided on the output data path may be a circuit for discharging the ESD applied to the output pin to the ground.

The power pin 120 may be a pin for supplying power required to drive the internal circuit 130. For example, the power pin 120 may include a VDD pin and a VSS pin. The VDD pin may be a pin to which a power supply voltage is applied. The VSS pin may be a pin connected to the ground. The VDD pin may be connected to the VSS pin via an ESD protection circuit 121. The ESD protection circuit 121 connected between the power pins 120 may be a circuit for discharging the ESD applied to the VDD pin via the VSS pin. The voltage applied to the I/O pin 110 may be relatively lower than the voltage applied to the power pin 120. The internal circuit 130 may discharge the ESD applied to the IC chip 100 to the ground via the ESD protection circuits 111 and 121 provided for each I/O pin 110 and the ESD protection circuit 121 connected between the power pins 120, thereby preventing the failure and destruction of the IC chip 100 in advance.

FIG. 2 shows an ESD protection circuit 200 according to an embodiment.

2 , an ESD protection circuit 200 according to an embodiment may include an NMOS transistor NT and an RC circuit connected in parallel to the NMOS transistor NT.

The ESD protection circuit 200 according to the embodiment may correspond to the ESD protection circuit 121 connected between the power pins 120 of FIG. 1 .

The drain terminal of the NMOS transistor NT may be connected to the first node N1. The first node N1 may be connected to the VPP pin, and the voltage level of the first node N1 may be the same as the power supply voltage. For example, when an ESD event occurs, an impulse voltage may be applied to the VPP pin. Therefore, the voltage level of the first node N1 may increase rapidly.

The gate terminal of the NMOS transistor NT may be connected to the second node N2. The second node N2 may be a node between the resistor R and the capacitor C of the RC circuit. One end of the capacitor C may be connected to the first node N1, and the other end of the capacitor C may be connected to the second node N2. One end of the resistor R may be connected to the second node N2, and the other end of the resistor R may be connected to the third node N3.

When an ESD event occurs and a surge voltage is applied through the VPP pin, the surge voltage may be coupled to the capacitor C. That is, when the surge voltage is instantaneously applied to the VPP pin, the capacitor C may be operated as a short circuit, so that the voltage level of the second node N2 may be boosted by the magnitude of the surge. The voltage level of the second node N2 by the magnitude of the boosted surge may decrease exponentially based on a time constant τ, which is the product of the resistance of the resistor R and the capacitance of the capacitor C.

According to an embodiment, when an ESD event occurs, the voltage level of the second node N2 may increase based on the coupling of the capacitor C, and therefore, the trigger voltage of the NMOS transistor NT may decrease. The trigger voltage refers to a voltage at which avalanche breakdown occurs in a reverse bias between the body and drain terminals of the NMOS transistor NT. That is, when a voltage equal to or higher than the trigger voltage is applied to the drain terminal of the NMOS transistor NT, avalanche breakdown may occur. Here, as the voltage level of the second node N2 of the gate terminal increases, the trigger voltage may decrease, and avalanche breakdown may occur at a lower voltage.

FIG. 3 is a graph showing IV curves of drain voltage and drain current of the ESD protection circuit 200 according to an embodiment.

2 and 3, based on the occurrence of an ESD event, the voltage level of the first node N1 of the drain terminal may increase rapidly. As described above, at the moment when the voltage level of the first node N1 reaches the first trigger voltage, avalanche breakdown may occur. When avalanche breakdown occurs, a base current may be formed. The base current is the base current of the parasitic bipolar junction transistor (BJT) of the NMOS transistor NT. The parasitic BJT may be an NPN-type parasitic BJT, in which the drain terminal of the NMOS transistor NT is "N", the substrate of the NMOS transistor NT is "P", and the source terminal of the NMOS transistor NT is "N". The body voltage may increase due to the base current to form a forward bias, and therefore, the ESD current of the drain terminal may flow to the ground pin through the source terminal.

When the ESD current flows to the ground pin through the source terminal, the voltage of the first node N1 of the drain terminal may gradually decrease, and at this time, the lowest voltage level may correspond to the holding voltage (V _HD ).

After the voltage of the first node N1 of the drain terminal is reduced to the holding voltage, a large current may flow in the snapback period even if the voltage is lower than the first trigger voltage. This is because the avalanche breakdown has triggered the current flow between the collector and the emitter. Thereafter, when the voltage level of the first node N1 increases again to reach the second trigger voltage, a thermal failure may occur. That is, if the voltage of the first node N1 increases in the snapback period and the drain current becomes too large, the temperature of the ESD protection circuit 200 may increase and the ESD protection circuit 200 may be destroyed. In one embodiment, referring to FIGS. 3 and 4, the drain current may be I _t1 when the drain voltage of the ESD protection circuit 200 reaches the first trigger voltage V _t1 , and the drain current may be I _t2 when the drain voltage of the ESD protection circuit 200 reaches the second trigger voltage V _t2 .

FIG. 4 illustrates a graph of an ESD design window according to an embodiment.

4, the breakdown voltage may be greater than the first trigger voltage _Vt1 and the second trigger voltage _Vt2 . The breakdown voltage refers to a voltage level at which the internal circuit 130 of FIG. 1 fails or is destroyed. The first trigger voltage _Vt1 and the second trigger voltage _Vt2 must be less than the breakdown voltage. If the first trigger voltage _Vt1 and the second trigger voltage _Vt2 are greater than the breakdown voltage, the internal circuit 130 may have reached the breakdown voltage and be destroyed before the NMOS transistor NT is turned on to release the ESD current.

According to an embodiment, the operating voltage may be less than the holding voltage V _HD . The operating voltage refers to a voltage level required for normal operation of the internal circuit 130 . The holding voltage V _{HD should be greater than the operating voltage . This is because, if the holding voltage V HD is} lower than the operating voltage, a large ESD current flows in the snapback operation region after avalanche breakdown occurs due to the first trigger voltage V _t1 , and therefore, even if the ESD event is terminated and the internal circuit 130 operates at the operating voltage, the ESD current cannot be resolved.

FIG. 5 shows an ESD protection circuit 500 according to an embodiment.

5 , in view of the ESD protection circuit 200 of FIG. 2 , an ESD protection circuit 500 according to an embodiment may include a clamp circuit 510 connected in parallel with a resistor R of an RC circuit connected in parallel with an NMOS transistor NT.

The drain terminal of the NMOS transistor NT may be connected to the first node N1. The first node N1 may be connected to the VPP pin, and the voltage level of the first node N1 may be the same as the power supply voltage. For example, when an ESD event occurs, a surge voltage may be applied to the VPP pin. Therefore, the voltage level of the first node N1 may increase rapidly.

A gate terminal of the NMOS transistor NT may be connected to a second node N2. The second node N2 may be provided between the resistor R and the capacitor C of the RC circuit. One end of the capacitor C may be connected to the first node N1, and the other end of the capacitor C may be connected to the second node N2. One end of the resistor R may be connected to the second node N2, and the other end of the resistor R may be connected to a third node N3.

When an ESD event occurs and a surge voltage is applied through the VPP pin, the surge voltage may be coupled to the capacitor C. That is, when the surge voltage is instantaneously applied to the VPP pin, the capacitor C may be operated as a short circuit, so that the voltage level of the second node N2 may be boosted by the magnitude of the surge. The voltage level of the second node N2 by the magnitude of the boosted surge may decrease exponentially based on a time constant τ, which is the product of the resistance of the resistor R and the capacitance of the capacitor C.

The source terminal of the NMOS transistor NT may be connected to the third node N3. The third node N3 may be connected to the VSS pin. The clamp circuit 510 may be connected between the second node N2 and the third node N3. That is, the clamp circuit 510 may be connected in parallel with the resistor R of the RC circuit. The clamp circuit 510 may include a plurality of diodes. The voltage level of the second node N2 may be determined according to the number of diodes. For example, when an ESD event occurs, the maximum value of the voltage level of the second node N2 may be proportional to the number of diodes. For example, when the number of diodes of the clamp circuit 510 is N (N is an integer greater than 0), the maximum value of the voltage level of the second node N2 may be 0.7 [V] × N.

The maximum value of the voltage level of the second node N2 may be determined according to the number of diodes included in the clamp circuit 510, and the first trigger voltage _Vt1 may vary based on the maximum value. For example, when the number of diodes increases, the maximum value may also increase, and thus, the first trigger voltage _Vt1 may decrease. This is because the first trigger voltage _Vt1 is inversely proportional to the voltage level of the second node N2, which is the gate terminal of the NMOS transistor NT.

FIG. 6 is a graph showing a relationship between a gate voltage of an NMOS transistor NT and a trigger voltage of an ESD protection circuit 500 according to an embodiment.

6, there is shown a graph showing the relationship between the voltage level (GC_G) applied to the gate terminal of the NMOS transistor NT and the voltage level of the first trigger voltage _Vt1 according to the present embodiment. The X-axis may be the voltage level of the gate terminal of the NMOS transistor NT (i.e., the voltage level of the second node N2). The Y-axis may be the voltage level of the first trigger voltage _Vt1 of FIG. 3 or the first trigger voltage _Vt1 of FIG. 4.

According to the present embodiment, as the voltage applied to the gate terminal of the NMOS transistor NT increases, the reverse bias between the body and the drain terminal of the NMOS transistor NT can be significantly increased, so even if the voltage applied to the drain terminal is low, avalanche breakdown can easily occur. Therefore, the voltage level applied to the gate terminal can be inversely proportional to the voltage level of the first trigger voltage _Vt1 .

According to the present embodiment, the number of diodes included in the clamp circuit 510 may be determined. First, the voltage level of the first trigger voltage V _t1 on the Y axis may be considered. For example, as described above, because the first trigger voltage V _t1 must be less than the breakdown voltage of the internal circuit 130, the first trigger voltage V _t1 must be included in a range less than the first threshold voltage V _th1 . As another example, because the first trigger voltage V _t1 must not operate in a non-ESD event, the first trigger voltage V _t1 must be greater than the operating voltage. Therefore, the first trigger voltage V _t1 must be included in a range greater than the second threshold voltage V _th2 . When the range of the first trigger voltage V _t1 is determined, the number of diodes of the clamp circuit 510 may be determined based on the range. For example, the number of diodes may be greater than the first value VALUE 1 required for the first trigger voltage V _t1 not to exceed the first threshold voltage (the first value VALUE 1 is the minimum value). As another example, the number of diodes may be less than the second value VALUE 2 required to set the first trigger voltage V _t1 to be higher than the second threshold voltage (the second value VALUE 2 is the maximum value).

FIG. 7 illustrates an example of determining the number of diodes of the clamp circuit 510 according to an embodiment.

7 , there is shown a graph showing the relationship between the voltage level of the gate terminal and the first trigger voltage V _t1 according to the number of diodes included in the clamp circuit 510. Since the diodes included in the clamp circuit 510 are connected in series, it can be seen that the maximum value to which the voltage level of the second node N2 of the gate terminal is limited gradually increases as the number of diodes increases. In addition, as described above, since the first trigger voltage V _t1 is inversely proportional to the voltage level of the gate terminal, it can be seen that the first trigger voltage V _t1 decreases as the number of diodes increases.

According to the present embodiment, the voltage level of the breakdown voltage PeBV may be 25 [V]. For example, the breakdown voltage PeBV refers to a voltage that causes the peripheral circuit to be broken down. In order to protect the internal circuit 130 from ESD events, the first trigger voltage _Vt1 cannot exceed 25 [V]. Therefore, it can be seen that the number of diodes that meet the conditions related to the breakdown voltage PeBV is at least two.

According to the present embodiment, the voltage level of the operating voltage VOP may be 20 [V]. The operating voltage VOP refers to a voltage required for normal operation of the internal circuit 130. In order not to trigger the NMOS transistor NT of the ESD protection circuit 500 under normal operation conditions except for an ESD event, the first trigger voltage _Vt1 cannot be less than 20 [V]. Therefore, it can be seen that the maximum number of diodes that meet the conditions associated with the operating voltage VOP is four (4) or less.

In summary, in the case where the electronic device includes an internal circuit 130 having a high operating voltage VOP of 20 [V] and a breakdown voltage PeBV of 25 [V], the number of diodes included in the clamping circuit 510 can be determined to be two (2) to four (4) without incurring additional process costs, thereby protecting the device from ESD events while ensuring high voltage operation.

According to the present embodiment, it is confirmed that the ESD protection circuit 500 further includes the clamp circuit 510, and the number of diodes included in the clamp circuit 510 can be set to appropriately reduce the first trigger voltage _Vt1 , thereby controlling the NMOS transistor NT to be turned on at a voltage less than the breakdown voltage PeBV and greater than the high-level operation voltage. However, since the clamp circuit 510 still performs a clamping operation even during an ESD event, the first trigger voltage _Vt1 may be boosted to cause degradation of ESD performance. Therefore, an additional configuration is required for selectively inactivating the clamp circuit 510 in the event of an ESD event and selectively activating the clamp circuit 510 only during normal operation.

FIG. 8 shows an ESD protection circuit 800 according to an embodiment.

8, the ESD protection circuit 800 according to the embodiment may further include a switch 810 for selectively connecting the clamp circuit 510 to the second node N2 in view of the ESD protection circuit 500 according to the ESD event or the normal operation. The switch 810 may be a sub-gate coupled PMOS (GCPMOS). For example, the switch 810 may connect the second node N2 to the clamp circuit 510. The switch 810 may include a PMOS transistor PT connecting the second node N2 to the clamp circuit 510 and a sub-RC circuit connected in parallel with the PMOS transistor PT. The sub-RC circuit may include a sub-resistor R _sub and a sub-capacitor C _sub , the sub-resistor R _sub connecting the fourth node N4 corresponding to the gate node of the PMOS transistor PT to the clamp circuit 510, and the sub-capacitor C _sub connecting the fourth node N4 corresponding to the gate node of the PMOS transistor PT to the second node N2 corresponding to the gate node of the NMOS transistor NT.

FIG. 9 is a graph illustrating a voltage level of each node in an ESD event and a normal operation event according to an embodiment.

9 , when an ESD event occurs, a surge voltage V _ESD may be applied to the VPP pin. When the surge voltage V _ESD is applied through the VPP pin, the surge voltage may be coupled to the capacitor C. When the surge voltage is momentarily applied to the VPP pin, the capacitor C may be operated as a short circuit, so that the voltage level of the second node N2 may be boosted by the magnitude of the surge. (V _ESD =V _ESD2 ). The voltage of the second node N2 may be coupled back to the sub-capacitor C _sub connected to the second node N2. When the sub-capacitor C _sub is coupled, the sub-capacitor C _sub momentarily operates as a short circuit, so that the voltage level of the fourth node N4 as the gate node of the PMOS transistor PT may follow the voltage level of the second node N2. The gate-source voltage difference V _GS of the PMOS transistor PT is a value obtained by subtracting the voltage level V _ESD4 of the fourth node N4 from the voltage level V _ESD2 of the second node N2. Because the voltage level V _ESD4 of the fourth node N4 follows the voltage level V _ESD2 of the second node N2, the magnitude of the gate-source voltage difference V _GS of the PMOS transistor PT may be relatively small and may not be sufficient to turn on the PMOS transistor PT. That is, in an ESD event, the PMOS transistor PT may be turned off, and in an ESD event, the second node N2 of the NMOS transistor NT may not be electrically connected to the clamp circuit 510.

According to an embodiment, a normal operation event may occur. When a normal operation event occurs, an operation voltage V _NOP according to a low slope boost may be applied to the VPP pin. When the low slope operation voltage V _NOP is applied through the VPP pin, each of the capacitor C and the sub-capacitor C _sub may operate as a resistor device. The sub-capacitor C _sub may operate as a resistor device so that the rate at which the voltage level V _NOP4 of the fourth node N4, which is the gate node of the PMOS transistor PT, follows the voltage level V _NOP2 of the second node N2 may be slow. Therefore, the magnitude of the gate-source voltage difference V _GS of the PMOS transistor PT may be relatively increased compared to when an ESD event occurs. As the magnitude of the gate-source voltage difference V _GS of the PMOS transistor PT increases, the PMOS transistor PT may be turned on in a normal operation event. Because the PMOS transistor PT is turned on in a normal operation event, the second node N2 of the NMOS transistor NT may be electrically connected to the clamp circuit 510. When the second node N2 is connected to the clamp circuit 510, the voltage level V _NOP2 of the second node N2 may further drop.

According to the present embodiment, the ESD protection circuit 800 includes a GC-PMOS switch 810 connected in series with the clamp circuit 510, so that in an ESD event, the second node N2 and the clamp circuit 510 can be electrically disconnected to prevent degradation of ESD performance, and in a normal operation event, the second node N2 can be electrically connected to the clamp circuit 510. FIG. 10 is a graph showing an improvement in margin in an ESD event and a normal operation event according to an embodiment. Referring to FIG. 10, it can be confirmed that the same voltage margin as in the ESD protection circuit 500 of the previous embodiment is maintained in a normal operation event. The reason why the voltage margins of the ESD protection circuit 500 and the ESD protection circuit 800 are the same in a normal operation event is because the PMOS transistor PT is turned on and the second node N2 is connected to the clamp circuit 510. In an ESD event, it can be confirmed that the voltage margin is improved compared to the ESD protection circuit 500 of the second comparative example. That is, the ESD protection circuit 800 according to the present embodiment has a larger margin with the breakdown voltage PeBV. Since the PMOS transistor PT is turned off and is not electrically connected to the clamp circuit 510 at the second node N2 , the ESD protection circuit 800 has a greater voltage margin.

FIG. 11 shows an example of an electronic device 1100 according to an embodiment.

11, in the electronic device 1100, the controller 1110 and the memory 1120 may be arranged to exchange electrical signals. For example, when the controller 1110 issues a command, the memory 1120 may write or read data. According to an embodiment, each of the controller 1110 and the memory 1120 may include an IC chip. In detail, each IC chip included in the controller 1110 and the memory 1120 may include the ESD protection circuits 1111 and 1121 described in the embodiment. The controller 710 or the memory 720 may include at least one pad, and the ESD protection circuit according to the present embodiment may be connected between at least one pad to prevent permanent damage caused by an ESD event in advance.

While the disclosure has been particularly shown and described with reference to disclosed embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims (20)

1. An electrostatic discharge, ESD, protection circuit comprising:

An n-type metal oxide semiconductor (NMOS) transistor connected to the power supply voltage pin through a first node and connected to the ground pin through a second node;

A resistor-capacitor RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor; and

A clamp circuit connected in parallel with a resistor of the RC circuit and including a plurality of diodes, the number of which is set based on a breakdown voltage and an operation voltage of an internal circuit to be protected by the ESD protection circuit; and

A switch connecting the clamp circuit to a gate node of the NMOS transistor, and comprising:

A p-type metal oxide semiconductor PMOS transistor connecting a gate node of the NMOS transistor to the clamp circuit; and

A sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

2. The ESD protection circuit of claim 1, wherein the internal circuit is connected to the supply voltage pin through a first node, to the ground pin through a second node, and in parallel with the ESD protection circuit.

3. The ESD protection circuit of claim 1, wherein the NMOS transistor comprises: a gate terminal connected to the third node, a drain terminal connected to the first node, and a source terminal connected to the second node,

Wherein a resistor of the RC circuit is connected between the second node and the third node, and

Wherein the sub-resistor of the sub-RC circuit connects a fourth node corresponding to the gate node of the PMOS transistor to the clamp circuit.

4. The ESD protection circuit of claim 3, wherein a capacitor of the RC circuit is connected between the first node and the third node, and

Wherein a sub-capacitor of the sub-RC circuit connects the third node to the fourth node.

5. The ESD protection circuit of claim 4, wherein the NMOS transistor is configured to: receiving an ESD voltage at the drain terminal, the ESD voltage being input through the supply voltage pin, and

Wherein the NMOS transistor is configured to discharge the ESD current through the source terminal based on the ESD voltage exceeding the trigger voltage.

6. The ESD protection circuit of claim 5, wherein the trigger voltage is inversely proportional to a voltage level of a third node corresponding to a gate terminal of an NMOS transistor.

7. The ESD protection circuit of claim 6, wherein the number of the plurality of diodes is set such that the trigger voltage is below the breakdown voltage and above the operating voltage.

8. The ESD protection circuit of claim 7, wherein the PMOS transistor is configured to be turned off based on an input of an ESD voltage through a supply voltage pin.

9. An electronic device, comprising:

An internal circuit connected to the power supply voltage pin through a first node, connected to the ground pin through a second node, and configured to transmit or receive data through a plurality of input/output (I/O) pins;

a first ESD protection circuit connected between the first node and the second node; and

A plurality of second ESD protection circuits connected to each of the plurality of I/O pins,

Wherein the first ESD protection circuit comprises:

a first n-type metal oxide semiconductor, NMOS, transistor comprising a drain terminal connected to the first node and a source terminal connected to the second node;

A first resistor-capacitor RC circuit connected in parallel with the first NMOS transistor and including a capacitor and a resistor;

A first clamp circuit connected in parallel with a resistor of the first RC circuit and including a plurality of first diodes, the number of which is set based on a breakdown voltage and an operation voltage of an internal circuit to be protected by the ESD protection circuit; and

A switch connected in series with the first clamp circuit and connected to a third node corresponding to a gate terminal of the first NMOS transistor,

Wherein the switch comprises a p-type metal oxide semiconductor PMOS transistor connecting the third node to the first clamp circuit and a sub-RC circuit connected in parallel with the PMOS transistor and comprising a sub-capacitor and a sub-resistor.

10. The electronic device of claim 9, wherein a resistor of the first RC circuit is connected between the second node and the third node, and

Wherein the sub-resistor of the sub-RC circuit connects the first clamp circuit to a fourth node corresponding to the gate terminal of the PMOS transistor.

11. The electronic device of claim 10, wherein a capacitor of the first RC circuit is connected between the first node and the third node, and

Wherein the sub-capacitor of the sub-RC circuit is connected between the third node and the fourth node.

12. The electronic device of claim 10, wherein the first NMOS transistor is configured to receive an ESD voltage at a drain terminal of the first NMOS transistor, the ESD voltage being input through a supply voltage pin, and

Wherein the first NMOS transistor is configured to discharge the ESD current through the source terminal of the first NMOS transistor based on the ESD voltage exceeding the trigger voltage.

13. The electronic device of claim 12, wherein the trigger voltage is inversely proportional to a voltage level of a third node corresponding to a gate terminal of the first NMOS transistor.

14. The electronic device of claim 13, wherein a number of the plurality of first diodes is set such that the trigger voltage is below the breakdown voltage and above the operating voltage.

15. The electronic device of claim 14, wherein the PMOS transistor is turned off based on the ESD voltage input through the supply voltage pin.

16. The electronic device of claim 9, wherein each of the plurality of second ESD protection circuits comprises:

A second NMOS transistor that includes a drain terminal connected to the I/O pin and a source terminal connected to the ground node;

a second RC circuit connected in parallel with the second NMOS transistor and including a capacitor and a resistor; and

A second clamping circuit connected in parallel with the resistor of the second RC circuit and including a plurality of second diodes,

Wherein the number of the plurality of second diodes is determined based on a breakdown voltage of the internal circuit.

17. The electronic device of claim 16, wherein a resistor of the second RC circuit is connected between a source terminal and a gate terminal of the second NMOS transistor,

Wherein the second clamping circuit is connected between the source terminal and the gate terminal of the second NMOS transistor, and

Wherein the capacitor of the second RC circuit is connected between the drain terminal and the gate terminal of the second NMOS transistor.

18. The electronic device of claim 17, wherein the second NMOS transistor is configured to receive the ESD voltage input through the I/O pin through a drain terminal of the second NMOS transistor, and

Wherein the second NMOS transistor is configured to discharge the ESD current through the source terminal of the second NMOS transistor based on the ESD voltage exceeding the trigger voltage.

19. The electronic device of claim 18, wherein the trigger voltage is inversely proportional to a voltage level of a gate terminal of the second NMOS transistor, and

Wherein the number of the plurality of second diodes is set such that the trigger voltage is lower than the breakdown voltage.

20. An electrostatic discharge, ESD, protection circuit comprising:

An n-type metal oxide semiconductor (NMOS) transistor connected to the power supply voltage pin through a first node and connected to the ground pin through a second node;

A resistor-capacitor RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor; and

A clamp circuit connected in parallel with the resistor of the RC circuit and comprising at least one diode; and

A switch connecting the clamp circuit to a gate node of the NMOS transistor, and comprising:

A p-type metal oxide semiconductor PMOS transistor connecting a gate node of the NMOS transistor to the clamp circuit; and

A sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.