CN118693615B

CN118693615B - A VCSEL array chip and a manufacturing method thereof

Info

Publication number: CN118693615B
Application number: CN202411178458.6A
Authority: CN
Inventors: 陈宝; 孙岩; 谢粤平; 戴文; 郑万乐
Original assignee: Nanchang Kaixun Photoelectric Co ltd
Current assignee: Nanchang Kaixun Photoelectric Co ltd
Priority date: 2024-08-27
Filing date: 2024-08-27
Publication date: 2025-02-07
Anticipated expiration: 2044-08-27
Also published as: CN118693615A

Abstract

The present invention relates to the technical field of vertical cavity surface emitting lasers, and specifically to a VCSEL array chip and a manufacturing method thereof, wherein the VCSEL array chip comprises, from bottom to top, a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a P+GaAs, a TaN thin film layer, a contact electrode, and a front electrode; the light exit holes of the VCSEL array chip are arranged in an array; the front electrode is a separated front electrode, which is respectively located in the welding wire area and the contact electrode area of the light exit hole, and is connected through the TaN thin film layer. The present invention optimizes the chip structure, arranges the light exit holes in an array, separates the front electrodes, and connects through the TaN thin film layer, thereby reducing the consumption of the electrode material Au while ensuring conductivity, greatly reducing costs, improving reliability, and facilitating processing.

Description

VCSEL array chip and manufacturing method thereof

Technical Field

The invention relates to the technical field of vertical cavity surface emitting lasers, in particular to a VCSEL array chip and a manufacturing method thereof.

Background

The VCSEL (vertical cavity surface emitting laser) chip is a novel semiconductor laser, has the advantages of small volume, low threshold current, good temperature characteristic, easy two-dimensional integration and the like, and is widely applied to the fields of optical communication, optical interconnection, optical sensing and the like. With the development of technology, the market demand for VCSELs is increasing, especially in occasions where high power output is required, such as laser radar, optical communication, and the like. Meanwhile, the reliability of the chip is also an important factor affecting the application thereof, and thus, improving the reliability of the VCSEL is one of the hot spots of current researches.

In the process of manufacturing the VCSEL chip, in order to improve the output power and the reliability of the VCSEL, the method is mainly realized by improving the structure of a device, optimizing the quality of materials, optimizing the manufacturing process and the like. However, the power and reliability are improved, the size and cost of the chip are often increased, which is not beneficial to miniaturization and cost reduction of the chip, and the stability design of the device is often unable to effectively influence environmental changes and long-term operation, so the cost and reliability of the chip are still to be improved.

Disclosure of Invention

Aiming at the problem that the reliability and the cost of the VCSEL chip cannot be considered in the prior art, the invention provides the VCSEL array chip and the manufacturing method thereof, and the VCSEL array chip device has high reliability, simple processing process and low cost.

The invention provides a VCSEL array chip, which sequentially comprises a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, P+ GaAs, a TaN film layer, a contact electrode and a front electrode from bottom to top;

The light emergent holes of the VCSEL array chip are arranged in an array manner;

the front electrode is a separated front electrode, is respectively positioned in the welding line area and the contact electrode area of the light emergent hole, and is connected through the TaN film layer.

The structure of the VCSEL chip is optimized, the light emitting holes are arranged in an array mode, the front electrodes of the light emitting hole areas are separated from the front electrodes of the bonding wire areas, then the electrodes are connected through the TaN film layer, consumption of an electrode material Au is effectively reduced while conductivity is guaranteed, cost is greatly reduced, meanwhile, taN serving as an important transition metal nitride is high in melting point, high in hardness, high in density, high in heat conductivity and the like, is suitable for a high-temperature environment, in addition, the TaN is high in chemical inertness, is not easy to corrode in corrosive gas and liquid, has good oxidation resistance at a high temperature, and the reliability of the chip can be improved by introducing the TaN film layer.

Further, in the above technical scheme, the TaN film layer is an insulating layer, a transition layer and a conductive layer from bottom to top in sequence, wherein the thickness of the insulating layer is 3000±20 angstroms, the thickness of the transition layer is 1000±10 angstroms, and the thickness of the conductive layer is 4000±30 angstroms. The TaN thin film layer in the technical scheme is of a multi-layer TaN structure, and films with different functions are obtained through a magnetron sputtering process, wherein the bottom insulating layer plays a role in insulating protection, and the surface conductive layer is of a metal-like structure, can conduct electricity and plays a role in connecting the front electrode.

Further, in the above technical scheme, the contact electrode is located at the top of the step of the light emitting hole and is in a ring shape, the thickness is 3000+ -20 angstroms, and the materials are Ti/Pt/Au in sequence.

Further, in the above technical scheme, an oxidation limiting ring is formed in a region corresponding to the light emitting hole on the oxide layer, and the inner diameter of the oxidation limiting ring is smaller than or equal to the inner diameter of the contact electrode.

Furthermore, in the above technical scheme, the thickness of the front electrode is 20000+ -100 angstrom, and the materials are Ti/Ni/Pd/Au in sequence.

Further, in the above technical scheme, the thickness of the back electrode is 5000±50 angstroms, and the materials are AuGe/Au in sequence.

The invention also provides a manufacturing method of the VCSEL array chip, which comprises the following steps:

S1, growing an AlGaAs laser epitaxial wafer on a GaAs substrate by MOCVD (metal organic chemical vapor deposition), wherein the epitaxial wafer sequentially grows a GaAs buffer layer, an N-DBR (distributed Bragg reflector), an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR and P+GaAs on the GaAs substrate, wherein the logarithm of the N-DBR is 45-50 pairs, and the logarithm of the P-DBR is 16-22 pairs;

s2, cleaning by adopting an organic solution, carrying out negative photoresist alignment, carrying out electron beam evaporation, and carrying out negative photoresist stripping in combination, so as to manufacture a contact electrode on the surface of the epitaxial wafer;

S3, manufacturing an oxidation channel pattern by adopting a positive photoresist alignment mode, etching the oxidation channel pattern with a certain width by ICP (inductively coupled plasma), etching the oxidation channel pattern to the N-DBR layer to form a photoresist hole step, and removing surface photoresist by using photoresist removing solution;

s4, carrying out wet oxidation on the oxidation layer corresponding to the contact electrode through a wet oxidation furnace to form an oxidation limiting ring;

S5, cleaning the wafer by using weak alkaline ammonia water solution, magnetically sputtering a TaN film layer in a negative photoresist alignment mode, and stripping by matching with negative photoresist to form a patterned TaN film pattern on the surface;

S6, cleaning by adopting an organic solution, carrying out negative photoresist alignment, carrying out electron beam evaporation, and carrying out negative photoresist stripping in combination, so as to manufacture a separated front electrode on the surface of the epitaxial wafer;

s7, thinning the GaAs substrate by utilizing mechanical grinding, carrying out CMP (chemical mechanical polishing), cleaning the back surface by utilizing an acidic solution, and evaporating a back electrode by utilizing an electron beam evaporation mode;

S8, finally, cutting and separating the chips at fixed intervals to form VCESL single chips and carrying out AOI sorting.

According to the manufacturing method, the annular contact electrode of the array light emitting holes is manufactured preferentially in the chip manufacturing process, then the oxidation limiting ring smaller than or equal to the inner diameter of the contact electrode ring is manufactured on the corresponding oxide layer to restrict current, light emitting power is improved, the sputtering conditions, especially the flow of nitrogen, are controlled in a magnetron sputtering mode, the TaN film layers with different film layers are manufactured at one time, the three layers are formed, the bottom layer plays an insulating protection role, the reliability of the chip is effectively guaranteed, the surface layer plays a conductive role to connect the separated front electrodes, consumption of materials such as Au is greatly reduced, and the manufacturing method is convenient to process, low in cost, good in reliability, capable of improving light emitting efficiency and excellent in overall performance.

Further, in the above technical scheme S3, the power of ICP etching is 500W, the pressure is 30mtorr, the flow rate of bcl ₃ is 25sccm, the flow rate of cl ₂ is 8sccm, the flow rate of n ₂ is 30sccm, the flow rate of sf ₆ is 50sccm, and the step gradient of the light exit hole is 90 °.

Further, in the technical scheme S5, the process of magnetron sputtering the TaN film layer comprises the steps of enabling the vacuum degree to be 1Torr-10Torr, enabling the purity of a tantalum target to be 99.99%, enabling mixed gas of argon and nitrogen to be introduced at the temperature of a substrate to be 25 ℃, enabling the flow rate of the argon to be 20sccm in the first stage, enabling the flow rate of the nitrogen to be 30sccm-40sccm, enabling the sputtering power to be 200W, enabling the sputtering time to be 30min, enabling the flow rate of the argon to be 20sccm, enabling the flow rate of the nitrogen to be 5sccm-10sccm, enabling the sputtering power to be 200W, enabling the sputtering time to be 10min, enabling the flow rate of the argon to be 20sccm, enabling the flow rate of the nitrogen to be 0.5sccm-1sccm, enabling the sputtering power to be 200W, and enabling the sputtering time to be 40min, and enabling the conductive layer to be obtained. According to the technical scheme, the TaN film layer adopts a magnetron sputtering process, and the TaN film layers with different characteristics can be obtained by adjusting the nitrogen flow, if the first layer adopts high nitrogen flow, the film layer presents insulativity, the second layer adopts conventional nitrogen flow, the film layer presents semi-conductivity, and when the third layer adopts low nitrogen flow, the film has characteristics close to metal, and the conductivity is good.

Further, in the above technical solution S7, the acidic solution is a mixed solution of hydrochloric acid and water in a volume ratio of 1:20.

Compared with the prior art, the invention has the beneficial effects that:

1. According to the invention, the light emitting hole array is arranged by optimizing the chip structure, the front electrodes of the light emitting hole areas are separated from the front electrodes of the bonding wire areas, and then the electrodes are connected through the TaN film layer, so that the consumption of electrode material Au is effectively reduced while the conductivity is ensured, the cost is greatly reduced, and meanwhile, the reliability of the chip can be improved by introducing the high-performance TaN film layer.

2. The chip of the invention can restrict current by preferentially manufacturing the annular contact electrode with the array of light holes, then manufacturing the oxidation limiting ring smaller than or equal to the inner diameter of the contact electrode ring on the corresponding oxide layer, improving light-emitting power, and then realizing the manufacture of different film layers at one time by controlling sputtering conditions in a magnetron sputtering mode, wherein the obtained TaN film layers have three layers, the bottom layer plays an insulating protection role, the reliability of the chip is effectively ensured, the surface layer plays a conductive role to connect the separated front electrodes, the consumption of materials such as Au is greatly reduced, and the manufacturing method has the advantages of convenient processing, low cost, good reliability, and excellent overall performance, and can also ensure light-emitting efficiency.

Drawings

Fig. 1 is a schematic diagram of an epitaxial wafer structure of a VCSEL array chip according to the present invention;

fig. 2 is a schematic structural diagram of a VCSEL array chip according to the present invention.

The reference numerals in the schematic drawings indicate:

1. GaAs substrate, 2, gaAs buffer layer, 3, N-DBR, 4, N-limiting layer, 5, multiple quantum well active layer, 6, P-limiting layer, 7, oxide layer, 8, P-DBR, 9, P+ GaAs, 10, contact electrode, 11, oxidation limiting ring, 12, taN film layer, 12-1, insulating layer, 12-2, transition layer, 12-3, conductive layer, 13, front electrode, 14, back electrode.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for defining the components, and are merely for convenience in distinguishing the corresponding components, and the terms are not meant to have any special meaning unless otherwise indicated, so that the scope of the present application is not to be construed as being limited.

In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, and are merely for convenience of describing the present application and simplifying the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of the present application, and the azimuth terms "inside and outside" refer to inside and outside with respect to the outline of each component itself.

Referring to fig. 1 to 2, it should be noted that the illustrations provided in the present embodiment are only schematic illustrations of the basic concept of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The organic solution used for cleaning is common organic solvent such as acetone, isopropanol, etc.

Some embodiments of the present invention provide a VCSEL array chip, whose schematic structural diagram is shown in fig. 1, where the VCSEL array chip sequentially includes, from bottom to top, a back electrode 14, a GaAs substrate 1, a GaAs buffer layer 2, an N-DBR3, an N-confinement layer 4, a multiple quantum well active layer 5, a P-confinement layer 6, an oxide layer 7, a P-DBR8, p+gaas9, a TaN thin film layer 12, a contact electrode 10, and a front electrode 13;

Specifically, the light emitting holes of the VCSEL array chip are arranged in an array, where fig. 1 is only a specific embodiment, and is not limited to three rows, and may be any type of array;

the front electrode is a separated front electrode, is respectively positioned in the bonding wire area and the contact electrode area of the light emitting hole, and is connected through the TaN film layer, more specifically, is connected through the surface conductive layer. Therefore, only the front electrode material is needed to be used in the welding line area and the contact electrode area, so that the consumption of materials such as Au and the like is greatly reduced, and the cost is reduced.

Specifically, the TaN film layer sequentially comprises an insulating layer, a transition layer and a conductive layer from bottom to top, wherein the thickness of the insulating layer is 3000+/-20 angstroms, the thickness of the transition layer is 1000+/-10 angstroms, and the thickness of the conductive layer is 4000+/-30 angstroms. The TaN film layer is three layers, wherein the bottom layer is an insulating layer with insulating protection function, the reliability of the chip is improved, the middle layer is a transition layer, the surface layer is a conductive layer with conductivity, the front electrode can be connected, the conductivity of the chip is ensured, and the material cost is reduced.

Specifically, the contact electrode is positioned at the top of the step of the light emitting hole and is in a ring shape, the thickness is 3000+/-20 angstroms, and the materials are Ti/Pt/Au in sequence.

Specifically, the oxidation limiting ring 11 is formed on the oxidation layer in the area corresponding to the light emitting hole, and the inner diameter of the oxidation limiting ring is smaller than or equal to the inner diameter of the contact electrode, so that the light emitting efficiency can be ensured.

Still further embodiments of the present invention provide a method for fabricating a VCSEL array chip, comprising the steps of:

S1, growing an AlGaAs laser epitaxial wafer on a GaAs substrate by MOCVD, wherein the structure schematic diagram of the AlGaAs laser epitaxial wafer is shown in FIG 1, and the epitaxial wafer sequentially grows a GaAs buffer layer 2, an N-DBR3, an N-limiting layer 4, a multiple quantum well active layer 5, a P-limiting layer 6, an oxide layer 7, a P-DBR8 and a P+GaAs9 on the GaAs substrate 1, wherein the logarithm of the N-DBR is 45-50 pairs, and the logarithm of the P-DBR is 16-22 pairs.

S2, adopting an organic solution for cleaning, negative photoresist alignment, electron beam evaporation and stripping matched with negative photoresist to manufacture a contact electrode on the surface of the epitaxial wafer, specifically adopting an organic solution for cleaning, a negative photoresist alignment, electron beam evaporation and stripping matched with negative photoresist to manufacture an annular contact electrode on the surface of the epitaxial wafer, wherein the thickness of the contact electrode is 3000+/-20 angstroms, the contact electrode sequentially comprises a Ti/Pt/Au metal material, and the contact electrode annular is positioned on a light outlet hole step.

S3, an oxide channel pattern is manufactured in a positive photoresist alignment mode, an oxide channel pattern with a certain width is etched through ICP etching, the etching depth reaches the N-DBR layer to form a photoresist outlet step, photoresist on the surface is removed through photoresist removing solution, specifically, OES (optical emission and electrical direct reading spectroscopy) is used for monitoring in the etching process, the etching depth reaches 2 pairs of-4 pairs of N-DBR, ICP etching power is 500W, pressure is 30mTorr, BCl ₃ flow is 25sccm, cl ₂ flow is 8sccm, N ₂ flow is 30sccm, SF ₆ flow is 50sccm, the inclination of the photoresist outlet step is 90 degrees, and the photoresist on the surface is removed through photoresist removing solution.

S4, carrying out wet oxidation on the oxidation layer corresponding to the contact electrode through a wet oxidation furnace to form an oxidation limiting ring, wherein the inner diameter of the oxidation limiting ring is smaller than or equal to the inner diameter of the contact electrode ring, so that current can be restrained, and the light-emitting power can be improved.

S5, cleaning a wafer by using a weak alkaline ammonia water solution, performing magnetron sputtering on a TaN film layer in a negative photoresist alignment mode, and stripping the TaN film layer in a matched manner to form a patterned TaN film pattern on the surface, wherein the TaN film layer comprises three layers, the magnetron sputtering process comprises the steps of obtaining a transition layer 12-2 with the thickness of 1000+/-10 angstroms by vacuum degree of 1Torr-10Torr, the purity of a tantalum target material of 99.99%, the temperature of a substrate of 25 ℃, introducing mixed gas of argon and nitrogen, wherein the flow rate of the argon in the first stage is 20sccm, the flow rate of the nitrogen is 30sccm-40sccm, the sputtering power is 200W, the sputtering time is 30min, the insulating layer 12-1 with the thickness of 3000+/-20 angstroms is obtained, the flow rate of the argon in the second stage is 20sccm, the flow rate of the nitrogen is 5sccm-10sccm, the sputtering time is 10min, the transition layer 12-2 with the thickness of 1000+/-10 angstroms is obtained, the flow rate of the argon in the third stage is 0.5sccm-1 cm, the sputtering power is 200W, and the sputtering time is 40+/-30 angstroms and the conductive layer is 4000+/-30 angstroms. Through adjusting nitrogen flow, can obtain the TaN thin film layer of different characteristics, wherein first layer adopts high nitrogen flow, and the thin film layer presents insulativity, improves the reliability of chip, and the second layer adopts conventional nitrogen flow, and the thin film layer presents semi-conductive nature, and when the third layer adopted low nitrogen flow, the film has the characteristic that is close to the metal, and electric conductivity is good for connect the front electrode, reduce cost.

S6, adopting organic solution for cleaning, negative photoresist alignment, electron beam evaporation and stripping in combination with negative photoresist, and manufacturing a separated front electrode on the surface of the epitaxial wafer, wherein the thickness of the front electrode is 20000+/-100 angstroms, and the front electrode sequentially comprises Ti/Ni/Pd/Au metal materials, one part of which is positioned on the surface of the light emitting hole and is connected with the base electrode, and the other part of which is positioned in the bonding wire area and is used for packaging and wiring.

S7, thinning the GaAs substrate by mechanical grinding, polishing by CMP, cleaning the back surface by an acidic solution, evaporating a back electrode by an electron beam evaporation mode, specifically, the acidic solution is mixed solution of hydrochloric acid and water in a volume ratio of 1:20, the thickness of the back electrode is 5000+/-50 angstroms, the materials are AuGe/Au in sequence, and high-temperature fusion at 360 ℃.

In summary, the invention optimizes the array arrangement of the light emitting holes from the chip structure, and the front electrode of each light emitting hole area is separated from the front electrode of the bonding wire area, and then is connected through the TaN film layer, thereby effectively reducing the consumption of electrode material Au while ensuring conductivity, greatly reducing cost, simultaneously, the introduced high-performance TaN film layer can also improve the reliability of the chip, and the preparation of different film layers is realized once by controlling the magnetron sputtering condition, the obtained TaN film layer has three layers, wherein the bottom layer plays an insulation protection role, effectively ensures the reliability of the chip, the surface layer plays a conductive role to connect the separated front electrodes, greatly reduces the consumption of materials such as Au, and the like.

Finally, it should be emphasized that the foregoing description is merely illustrative of the preferred embodiments of the invention, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and principles of the invention, and any such modifications, equivalents, improvements, etc. are intended to be included within the scope of the invention.

Claims

1. A VCSEL array chip, characterized in that the VCSEL array chip comprises, from bottom to top, a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a P+GaAs, a TaN thin film layer, a contact electrode, and a front electrode;

The light exit holes of the VCSEL array chip are arranged in an array;

The front electrode is a separated front electrode, which is respectively located in the welding line area and the contact electrode area of the light exit hole, and is connected through the TaN thin film layer;

The TaN thin film layer is a multi-layer TaN structure, which includes an insulating layer, a transition layer, and a conductive layer from bottom to top, wherein the thickness of the insulating layer is 3000±20 angstroms, the thickness of the transition layer is 1000±10 angstroms, and the thickness of the conductive layer is 4000±30 angstroms; the insulating layer, the transition layer, and the conductive layer are obtained by controlling different magnetron sputtering conditions using a magnetron sputtering process.

2. A VCSEL array chip according to claim 1, characterized in that the contact electrode is located at the top of the step of the light exit hole and is in a circular ring shape, with a thickness of 3000±20 angstroms, and the materials are Ti/Pt/Au in sequence.

3. A VCSEL array chip according to claim 2, characterized in that an oxidation restriction ring is formed in a region of the oxide layer corresponding to the light exit hole, and the inner diameter of the oxidation restriction ring is less than or equal to the inner diameter of the contact electrode.

4. A VCSEL array chip according to claim 1, characterized in that the thickness of the front electrode is 20000±100 angstroms, and the materials are Ti/Ni/Pd/Au in sequence.

5 . The VCSEL array chip according to claim 1 , wherein the thickness of the back electrode is 5000±50 angstroms, and the materials are AuGe/Au in sequence.

6. A method for manufacturing a VCSEL array chip according to any one of claims 1 to 5, characterized in that it comprises the following steps:

S1. On a GaAs substrate, an AlGaAs laser epitaxial wafer is grown by MOCVD, wherein a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, and a P+GaAs are sequentially grown on the GaAs substrate;

S2. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make contact electrodes on the surface of the epitaxial wafer;

S3. An oxidation channel pattern is produced by positive photolithography, and an oxidation channel pattern having a certain width is etched by ICP etching, the etching depth reaches the N-DBR layer, and the surface photoresist is removed by a stripping solution;

S4. Wet oxidation is performed on the oxide layer corresponding to the contact electrode by a wet oxidation furnace to form an oxidation restriction ring;

S5. Clean the wafer with a weak alkaline ammonia solution, magnetron sputter a TaN thin film layer using a negative resist overlay method, and cooperate with negative resist stripping to form a patterned TaN thin film pattern on the surface;

S6. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make a separate front electrode on the surface of the epitaxial wafer;

S7. Thinning the GaAs substrate by mechanical grinding and performing CMP polishing, cleaning the back surface with an acid solution, and depositing a back electrode by electron beam evaporation;

S8. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and then AOI sorting is performed.

7. The method for manufacturing a VCSEL array chip according to claim 6, characterized in that, in S3, the power of ICP etching is 500 W, the pressure is 30 mTorr, the BCl ₃ flow rate is 25 sccm, the Cl ₂ flow rate is 8 sccm, the N ₂ flow rate is 30 sccm, and the SF ₆ flow rate is 50 sccm.

8. A method for manufacturing a VCSEL array chip according to claim 6, characterized in that, in S5, the process of magnetron sputtering the TaN thin film layer is: the vacuum degree is 1 Torr-10 Torr, the purity of the tantalum target is 99.99%, the temperature of the substrate is 25°C, and a mixed gas of argon and nitrogen is introduced, wherein, in the first stage, the flow rate of argon is 20 sccm, the flow rate of nitrogen is 30 sccm-40 sccm, the sputtering power is set to 200 W, and the sputtering time is 30 min to obtain an insulating layer; in the second stage, the flow rate of argon is 20 sccm, the flow rate of nitrogen is 5 sccm-10 sccm, the sputtering power is set to 200 W, and the sputtering time is 10 min to obtain a transition layer; in the third stage, the flow rate of argon is 20 sccm, the flow rate of nitrogen is 0.5 sccm-1 sccm, the sputtering power is set to 200 W, and the sputtering time is 40 min to obtain a conductive layer.

9 . The method for manufacturing a VCSEL array chip according to claim 6 , wherein in S7 , the acidic solution is a mixture of hydrochloric acid and water in a volume ratio of 1:20.