CN118692518A - A three-dimensional memory, reference voltage providing method and device - Google Patents

Abstract

A three-dimensional memory, a reference voltage providing method and a device relate to the technical field of storage and are used for solving the problem that the accuracy of reading is affected due to the fact that the physical layer of a memory unit is inconsistent in size, process, performance and the like. The three-dimensional memory includes: a plurality of memory cell physical layers stacked, each memory cell physical layer including a plurality of rows and columns of memory cells, the plurality of memory cell physical layers including a first memory cell physical layer and a second memory cell physical layer; a plurality of bit lines and a plurality of word lines coupled to the plurality of memory cell physical layers; and the reference voltage supply circuit is used for supplying a first reference voltage to the physical layer of the first memory cell through the bit line and supplying a second reference voltage to the physical layer of the second memory cell through the bit line, wherein the first reference voltage and the second reference voltage are different.

Description

A three-dimensional memory, reference voltage providing method and device

Technical Field

The present application relates to the field of storage technology, and in particular to a three-dimensional memory, a reference voltage providing method and a device.

Background Art

With the development of memory technology, three-dimensional (3D) memory has become an important direction for future memory. Among them, the three-dimensional memory based on the 1TnC structure has become one of the important development directions of 3D memory due to its higher storage density. A three-dimensional memory usually includes multiple physical layers of storage cells, and the related technology usually uses a working mode similar to a three-dimensional dynamic random access memory (DRAM) to realize the reading and writing of storage cells in the multiple physical layers of storage cells. However, in a three-dimensional memory, different physical layers of storage cells in the multiple physical layers of storage cells may have inconsistencies in size, process, and performance, which will affect the accuracy of the three-dimensional memory reading when using a working mode similar to a three-dimensional DRAM for reading and writing.

Summary of the invention

The present application provides a three-dimensional memory, a reference voltage providing method and a device, which are used to solve the problem that the reading accuracy is affected by the inconsistency of the size, process and performance of the physical layer of the storage unit.

To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a three-dimensional memory is provided, which may be a three-dimensional memory integrated in a chip, and includes: a plurality of stacked physical layers of memory cells, each physical layer of the memory cells including a layer of memory cells with multiple rows and columns, the plurality of physical layers of the memory cells including a first physical layer of memory cells and a second physical layer of memory cells; a plurality of bit lines and a plurality of word lines coupled to the plurality of physical layers of memory cells; and a reference voltage providing circuit for providing a first reference voltage to the first physical layer of memory cells through the bit lines, and providing a second reference voltage to the second physical layer of memory cells through the bit lines, the first reference voltage and the second reference voltage being different.

In the above technical solution, the three-dimensional memory can provide different reference voltages for different physical layers of storage cells. In this way, when different physical layers of storage cells are selected, different reference voltages can be provided for different physical layers of storage cells through bit lines, that is, data of different physical layers of storage cells are read through different reference voltages, thereby solving the problem of reading accuracy affected by inconsistencies in the size, process and performance of the physical layers of storage cells.

In a possible implementation of the first aspect, the first reference voltage is used to read data of a storage cell in the first storage cell physical layer, and the second reference voltage is used to read data of a storage cell in the second storage cell physical layer. Optionally, when a read process is used to read data of a storage cell in the first storage cell physical layer or the second storage cell physical layer, the reference voltage providing circuit can be specifically used to provide a first reference voltage to the first storage cell physical layer and a second reference voltage to the second storage cell physical layer through a bit line in an exchange phase. In the above possible implementation, data of different storage cell physical layers are read by different reference voltages, so that correct reading of data in storage cell physical layers of different sizes, processes and performances can be achieved.

In a possible implementation of the first aspect, the size of the storage cell in the first storage cell physical layer is larger than the size of the storage cell in the second storage cell physical layer, and the first reference voltage is larger than the second reference voltage. The size of the storage cell may also be referred to as the diameter of the storage cell, and may specifically refer to: the diameter of the pillar corresponding to the capacitor in the storage cell in the storage cell physical layer in which it is located. In the above possible implementation, by setting a larger reference voltage for the storage cell physical layer with a larger size, it is possible to correctly read data in the storage cell physical layers of different sizes.

In a possible implementation of the first aspect, the reference voltage providing circuit includes: a power pump, which is used to output a preset reference voltage; and a voltage regulating circuit, which is used to output the first reference voltage and the second reference voltage respectively according to the preset reference voltage, the first ratio and the second ratio. In the above possible implementation, different reference voltages are provided for different storage unit physical layers by the power pump and the voltage regulating circuit, which can reduce the number of power pumps in the reference voltage providing circuit and reduce costs.

In a possible implementation of the first aspect, the voltage regulating circuit includes: a resistor voltage divider circuit, configured to divide the preset reference voltage according to the first ratio to output the first reference voltage; and the resistor voltage divider circuit, configured to divide the preset reference voltage according to the second ratio to output the second reference voltage. In the above possible implementation, the resistor voltage divider circuit can divide the preset reference voltage according to different ratios to generate different reference voltages.

In a possible implementation of the first aspect, the reference voltage providing circuit further includes: a digital-to-analog conversion circuit, configured to output an indication signal to the voltage regulating circuit according to a target physical layer address, the indication signal being configured to indicate outputting the first reference voltage or the second reference voltage, the target physical layer address being an address of a selected storage unit physical layer from the multiple storage unit physical layers. In the above possible implementation, a simple and effective method of indicating the voltage regulating circuit to output a corresponding reference voltage is provided.

In a possible implementation of the first aspect, the reference voltage providing circuit includes: a first power pump, used to output the first reference voltage; and a second power pump, used to output the second reference voltage; wherein the first power pump and the second power pump have different circuit parameters, and the circuit parameters include a resistance value. In the above possible implementation, different power pumps provide different reference voltages for different storage unit physical layers, so that different reference voltages can be generated independently, thereby avoiding mutual influence.

In a possible implementation of the first aspect, the reference voltage providing circuit further includes: a selection switch, configured to select and output the first reference voltage or the second reference voltage according to a target physical layer address, wherein the target physical layer address is an address of a selected storage unit physical layer among the multiple storage unit physical layers. In the above possible implementation, the selection switch can be used to select corresponding reference voltages for different storage unit physical layers, thereby ensuring correct reading of data in the storage unit physical layer.

In a possible implementation manner of the first aspect, the three-dimensional memory further includes: a physical layer address decoder, configured to decode and output the target physical layer address.

In a possible implementation of the first aspect, the multiple storage unit physical layers include a first group and a second group; wherein the first group includes multiple first storage unit physical layers, and/or the second group includes multiple second storage unit physical layers. In the above possible implementation, by grouping the multiple storage unit physical layers, and providing different reference voltages to the storage unit physical layers in different groups through the reference voltage providing circuit, and providing the same reference voltage to the storage unit physical layers in the same group, the number of different reference voltages provided can be reduced while correctly reading the data in the multiple storage unit physical layers, thereby reducing the complexity of the reference voltage providing circuit, and reducing the cost and occupied area of the reference voltage providing circuit.

In a possible implementation of the first aspect, the first group is obtained through one etching process, and the second group is obtained through another etching process; or, the multiple storage unit physical layers include storage unit physical layers obtained through at least two etching processes, and the first group and the second group respectively include at least one storage unit physical layer corresponding to each etching process in the at least two etching processes; or, the reference voltage reading ranges corresponding to the first group and the second group are different. In the above possible implementations, the flexibility of grouping in the multiple storage unit physical layers can be improved, and at the same time, different reference voltages can be guaranteed for storage unit physical layers in different groups, thereby ensuring the correct reading of data in storage unit physical layers in different groups.

In a possible implementation of the first aspect, the multiple storage cell physical layers further include: a third storage cell physical layer; the reference voltage providing circuit is further used to provide a third reference voltage for the third storage cell physical layer through the bit line, and the third reference voltage is different from both the first reference voltage and the second reference voltage. In the above possible implementation, by grouping the multiple storage cell physical layers, and providing different reference voltages to the storage cell physical layers in different groups through the reference voltage providing circuit, and providing the same reference voltage to the storage cell physical layers in the same group, the number of different reference voltages provided can be reduced while correctly reading the data in the multiple storage cell physical layers, thereby reducing the complexity of the reference voltage providing circuit, and reducing the cost and occupied area of the reference voltage providing circuit.

In a possible implementation of the first aspect, the plurality of storage cell physical layers, the plurality of bit lines, and the plurality of word lines are formed by a front-end process, and the reference voltage providing circuit is formed by a back-end process. In the above possible implementation, the reference voltage providing circuit can provide different reference voltages, and read data of different storage cell physical layers through different reference voltages, thereby solving the problem of affecting the accuracy of reading due to inconsistency in the size, process, and performance of the storage cell physical layer.

In a second aspect, a reference voltage providing method is provided for reading data of a three-dimensional memory, the three-dimensional memory comprising a plurality of bit lines, a plurality of word lines and a plurality of storage unit physical layers arranged in a stacked manner, the plurality of storage unit physical layers comprising a first storage unit physical layer and a second storage unit physical layer, the method comprising: obtaining a target physical layer address, the target physical layer address being the address of a selected storage unit physical layer among the plurality of storage unit physical layers; if the target physical layer address is the address of the first storage unit physical layer, providing a first reference voltage to the first storage unit physical layer through the bit line; if the target physical layer address is the address of the second storage unit physical layer, providing a second reference voltage to the second storage unit physical layer through the bit line, the first reference voltage and the second reference voltage being different.

During the data reading process of the three-dimensional memory, when different physical layers of the memory cells are selected, different reference voltages can be provided to the different physical layers of the memory cells through the bit lines. In this way, the data of the different physical layers of the memory cells can be read through different reference voltages, thereby solving the problem of the accuracy of reading being affected by the inconsistency of the size, process and performance of the physical layers of the memory cells.

In a third aspect, a storage device is provided, which includes a controller and a three-dimensional memory, wherein the controller is used to control the reading and writing of the three-dimensional memory, and the three-dimensional memory is the three-dimensional memory provided by the first aspect or any possible implementation of the first aspect.

According to a fourth aspect, an electronic device is provided, which includes the storage device provided by the third aspect.

It can be understood that the beneficial effects that can be achieved by any of the reference voltage providing methods, storage devices, and electronic devices provided above can correspond to the beneficial effects in the three-dimensional memory provided above, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an array of a three-dimensional memory based on a 1TnC structure;

FIG2 is a schematic diagram of a 1TnC structure provided in an embodiment of the present application;

FIG3 is a timing diagram of a reading process provided in an embodiment of the present application;

FIG4 is a schematic diagram of a corresponding relationship between a reference voltage and a read pass rate provided in an embodiment of the present application;

FIG5 is a cross-sectional view of a physical layer of a storage unit provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of a three-dimensional memory provided in an embodiment of the present application;

FIG7 is a schematic diagram of a grouping of multiple storage units at the physical layer provided by an embodiment of the present application;

FIG8 is a schematic diagram of the structure of another three-dimensional memory provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of a reference voltage providing circuit provided in an embodiment of the present application;

FIG10 is a schematic diagram of the structure of another reference voltage providing circuit provided in an embodiment of the present application;

FIG11 is a schematic diagram of a training reference voltage provided in an embodiment of the present application;

FIG12 is a schematic diagram of another training reference voltage provided in an embodiment of the present application;

FIG13 is a schematic diagram of a flow chart of a reference voltage providing method provided in an embodiment of the present application;

FIG. 14 is a schematic diagram of the structure of a storage device provided in an embodiment of the present application.

DETAILED DESCRIPTION

The making and use of each embodiment will be discussed in detail below. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed only illustrate specific ways to implement and use this description and this technology, and do not limit the scope of this application.

Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit/component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit/component is not currently operational (e.g., not turned on), the circuit/component may be referred to as being configured to perform the task. Circuits/components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

The technical scheme in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. In the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And/or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and/or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiment of the present application, the words "first", "second" and the like do not limit the quantity and order.

In this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. "Coupled" in this application can be understood as a direct connection or an indirect connection. For example, A is coupled to B, which can mean: A is directly connected to B, or A is indirectly connected to B.

Before introducing the embodiments of the present application, the relevant contents of the three-dimensional (3D) memory involved in the present application are first introduced and explained.

With the development of memory technology, three-dimensional (3D) memory has become an important direction for future memory. Among them, the three-dimensional memory based on the 1TnC structure has become one of the important development directions of 3D memory due to its higher storage density, such as the three-dimensional ferroelectric capacitance (FeCAP) memory (which can be referred to as three-dimensional ferroelectric memory). Among them, a 1TnC structure includes a transistor and n capacitors, and the n capacitors can be used to form n memory cells set in a queue, and the memory cell can also be called a bit cell. The n memory cells share the one transistor.

FIG1 is a schematic diagram of an array of a three-dimensional memory based on a 1TnC structure, and the three-dimensional memory may be a three-dimensional ferroelectric memory. The array may include: a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of storage cell physical layers (plates). Each of the plurality of storage cell physical layers includes a plurality of storage cells arranged in a plane, and the plurality of storage cells are arranged in the form of multiple rows and columns. For each storage cell physical layer, a plurality of storage cells located in the same row share the same word line WL, and a plurality of storage cells located in the same column share the same bit line BL. Storage cells located in the same row at the same position in different storage cell physical layers also share the same word line WL, and a plurality of storage cells located in the same column at the same position in different storage cell physical layers also share the same bit line BL.

Furthermore, the three-dimensional memory may also include a sense amplifier (SA), which may be used to amplify signals during the reading and writing process of the three-dimensional memory. Optionally, the sense amplifier SA may include a bit line sense amplifier BL_SA and/or a global sense amplifier (GSA). In addition, the three-dimensional memory may also include one or more of other devices such as a row address decoder, a column address decoder, a physical layer address decoder, and a bit line selector (BL MUX).

The following is an example of a 1TnC (for example, n=3) structure in a three-dimensional ferroelectric memory to introduce the reading process of the storage unit (i.e., bitcell). Exemplarily, as shown in FIG2 , the 1TnC structure includes a transistor and three capacitors. The gate of the transistor is connected to the word line WL, and one electrode (for example, the source or the drain) of the transistor is coupled to the bit line BL and the bit line sense amplifier BL_SA, and the bit line sense amplifier BL_SA is also coupled to the inverted /BL of the bit line BL. The other electrode (for example, the source or the drain) of the transistor is connected to the first end of each of the three capacitors, and the second ends of the three capacitors are respectively connected to the layer lines (i.e., PL0, PL1, and PL2) of the physical layers of the three storage cells in a one-to-one correspondence. The first ends of the three capacitors share the same electrode, which can also be called a pillar.

In one embodiment, the reading process of the memory cell may include four stages, namely a pre-charge stage, a switch stage, a charge sharing stage and a sensing amplification stage. The timing diagram of the four stages may be shown in FIG. 3 .

In the precharge stage, the word line WL is set to a high level, and the potential of the first end of the capacitor in the memory cell is pulled down to 0V by the potential of the bit line BL. Then the word line WL is set to a low level, and the first end of the capacitor is in a floating state.

During the exchange phase, the first end of the capacitor remains in a floating state, the potential of the layer line PL is increased from low to high, and the stored charge in the memory cell is read; in the process of the potential of the layer line PL increasing from low to high, the potential of the first end of the capacitor is raised due to the coupling effect; at this time, the potential of the bit line BL and the potential of the inverted bit line /BL are both maintained at the reference voltage VREF.

In the charge sharing stage, the word line WL is turned on, and the first end of the capacitor and the bit line BL share charge. If the storage data of the memory cell is 0, the memory cell has no charge release, and due to the coupling effect, the potential of the first end of the capacitor is slightly raised (lower than VREF); the potential of the bit line BL will be pulled down by the potential of the first end of the capacitor to obtain VREF-, which is lower than the potential VREF of the inverted phase /BL of the bit line. If the storage data of the memory cell is 1, the memory cell releases the charge and the coupling effect will raise the potential of the first end of the capacitor (higher than VREF); the potential of the bit line BL will be pulled up by the potential of the first end of the capacitor to obtain VREF+, which is higher than the potential VREF of the inverted phase /BL of the bit line.

In the sensing and amplifying stage, the SA corresponding to the bit line BL amplifies the potential difference between the bit line BL and the inverted /BL of the bit line, thereby determining whether the read data is "0" or "1".

Therefore, the setting of the above-mentioned reference voltage VREF needs to consider the two cases where the stored data is "0" and "1". Exemplarily, FIG4 shows the size of the reference voltage corresponding to the data "0" and "1" at different read pass rates. Among them, if the reference voltage VREF is set to be larger, it is conducive to reading the data "1"; if the reference voltage VREF is set to be smaller, it is conducive to reading the data "0". Therefore, the setting of the reference voltage VREF needs to satisfy the correct reading of "0" and "1" at the same time. In this application, the range of reference voltages that can satisfy the correct reading of "0" and "1" at the same time is referred to as the reference voltage reading range or the reference voltage window. For example, the reference voltage reading range can be the black area in FIG4.

However, the formation of multiple physical layers of storage cells in a three-dimensional memory may go through one or more etching processes, and the multiple physical layers of storage cells obtained by the same etching process may also have size differences in the vertical direction, resulting in inconsistencies in the size, process and performance of storage cells in different physical layers of storage cells, thereby making the reference voltage reading ranges corresponding to different physical layers of storage cells different. Furthermore, when the data of storage cells in different physical layers of storage cells are read using the same reference voltage VREF reading range according to the above reading process, the accuracy of reading will be affected. Exemplarily, as shown in FIG5, it is a cross-sectional view of a physical layer of storage cells in a three-dimensional ferroelectric memory, assuming that multiple physical layers of storage cells include layer i+1, layer i and layer i-1 stacked in sequence from top to bottom. Among them, the size D(i+1) of the storage cell in layer i+1 can be greater than the size Di of the storage cell in layer i, and the size Di of the storage cell in layer i can be greater than the size D(i-1) of the storage cell in layer i-1, that is, D(i+1)＞Di＞D(i-1). The size of the storage unit may also be referred to as the diameter of the storage unit (ie, bit cell), and specifically refers to the diameter of the pillar (or the first end of the capacitor) corresponding to the capacitor in the storage unit in the physical layer of the storage unit.

Based on this, the embodiment of the present application provides a three-dimensional memory, which can be a three-dimensional ferroelectric memory, or other three-dimensional memory except the three-dimensional ferroelectric memory, such as a three-dimensional magnetic random access memory (MRAM), or a three-dimensional DRAM, etc. Specifically, the three-dimensional memory can provide different reference voltages for different physical layers of storage cells, so that when different physical layers of storage cells are selected, different reference voltages can be provided for different physical layers of storage cells through bit lines, that is, data of different physical layers of storage cells can be read through different reference voltages, thereby solving the problem of affecting the accuracy of reading due to the inconsistency of the size, process and performance of the physical layers of storage cells. The structure of the three-dimensional memory provided by the embodiment of the present application is introduced and explained below.

FIG6 is a schematic diagram of the structure of a three-dimensional memory provided in an embodiment of the present application, and the three-dimensional memory may be a three-dimensional memory integrated in a chip. The three-dimensional memory includes: a plurality of memory cell physical layers 10 stacked, a plurality of bit lines BL and a plurality of word lines WL, and a reference voltage providing circuit 20. The plurality of bit lines BL and the plurality of word lines WL are coupled to the plurality of memory cell physical layers 10, and the plurality of bit lines BL are also coupled to the reference voltage providing circuit 20.

Each of the plurality of storage unit physical layers 10 includes a layer of storage units arranged in multiple rows and columns, which can also be referred to as each storage unit physical layer including a layer of storage unit arrays. For example, each storage unit physical layer includes n rows and n columns of storage units, where n is an integer greater than 1. The plurality of storage unit physical layers 10 may include a first storage unit physical layer 11 and a second storage unit physical layer 12.

In addition, the multiple bit lines BL and the multiple word lines WL are coupled to the multiple memory cell physical layers 10, which may specifically include: in the same memory cell physical layer, multiple memory cells located in the same row share the same word line WL, and multiple memory cells located in the same column share the same bit line BL; in different memory cell physical layers, memory cells located in the same row at the same plane position also share the same word line WL, and multiple memory cells located in the same column at the same position also share the same bit line BL.

Exemplarily, the plurality of bit lines BL include a first bit line BL1 to an nth bit line BLn, and the plurality of word lines WL include a first word line WL1 to an nth word line WLn. For example, in the first memory cell physical layer 11, a plurality of memory cells located in the i-th row may share the i-th word line WLi, and a plurality of memory cells located in the i-th column may share the i-th bit line BLi, where the value of i may be 1 to n. For another example, in the second memory cell physical layer 12, a plurality of memory cells located in the j-th row may share the j-th word line WLj, and a plurality of memory cells located in the j-th column may share the j-th bit line BLj, where the value of j may be 1 to n.

In an embodiment of the present application, the reference voltage providing circuit 20 can be used to: provide a first reference voltage VREF1 for the first storage unit physical layer 11 through one or more of the first bit line BL1 to the nth bit line BLn, and provide a second reference voltage VREF2 for the second storage unit physical layer 12 through one or more of the first bit line BL1 to the nth bit line BLn, and the first reference voltage VREF1 and the second reference voltage VREF2 are different.

Optionally, the plurality of memory cell physical layers 10 , the plurality of bit lines WL, and the plurality of word lines BL are formed through a front-end process, and the reference voltage providing circuit is formed through a back-end process.

The first reference voltage VREF1 can be used to read data of the storage cells in the first storage cell physical layer 11, and the second reference voltage VREF2 can be used to read data of the storage cells in the second storage cell physical layer 12. When the data of the storage cells in the first storage cell physical layer 11 or the second storage cell physical layer 12 are read using the reading process related to FIG. 4, the reference voltage providing circuit 20 can be specifically used to provide the first reference voltage VREF1 to the first storage cell physical layer 11 and provide the second reference voltage VREF2 to the second storage cell physical layer 12 through the bit line BL in the above-mentioned exchange phase.

The following takes reading the data of the memory cells in the first column of the first memory cell physical layer 11 and the second memory cell physical layer 12 as an example. Exemplarily, when reading the data of the memory cells in the first column of the first memory cell physical layer 11, the reference voltage providing circuit 20 may keep the potential of the first bit line BL1 and the inverted phase /BL of the first bit line as the first reference voltage VREF1 during the exchange phase, so as to provide the first reference voltage VREF1 to the first memory cell physical layer 11 through the first bit line BL1; when reading the data of the memory cells in the first column of the second memory cell physical layer 12, the reference voltage providing circuit 20 may keep the potential of the first bit line BL1 and the inverted phase /BL of the first bit line as the second reference voltage VREF2 during the exchange phase, so as to provide the second reference voltage VREF2 to the second memory cell physical layer 12 through the first bit line BL1.

Optionally, the size of the storage cell in the first storage cell physical layer 11 may be greater than the size of the storage cell in the second storage cell physical layer 12, and the first reference voltage VREF1 is greater than the second reference voltage VREF2. The size of the storage cell may also be referred to as the diameter of the storage cell, and may specifically refer to: the diameter of the pillar (or the first end of the capacitor) corresponding to the capacitor in the storage cell in the storage cell physical layer, as shown in FIG5. Exemplarily, the first storage cell physical layer 11 may be layer i+1 in FIG5, and the second storage cell physical layer 12 may be layer i or layer i-1 in FIG5; or, the first storage cell physical layer 11 may be layer i in FIG5, and the second storage cell physical layer 12 may be layer i-1 in FIG5.

Further, the multiple storage unit physical layers 10 may include a first group GP1 and a second group GP2. The first group GP1 may include multiple first storage unit physical layers 11, and/or the second group GP2 may include multiple second storage unit physical layers 12. Accordingly, when the first group GP1 includes multiple first storage unit physical layers 11, the multiple first storage unit physical layers 11 all correspond to the first reference voltage VREF1, so that the first reference voltage VREF1 can be used to read data of storage units in any one of the multiple first storage unit physical layers 11. Similarly, when the second group includes multiple second storage unit physical layers 12, the multiple second storage unit physical layers 12 all correspond to the second reference voltage VREF2, so that the second reference voltage VREF2 can be used to read data of storage units in any one of the multiple second storage unit physical layers 12.

In practical applications, the multiple storage cell physical layers 10 may be obtained through a single etching process or through multiple etching processes. The multiple storage cell physical layers 10 include two or more groups, each of which may include one or more storage cell physical layers. In the two or more groups, the reference voltages corresponding to the storage cell physical layers in different groups are different, and the reference voltages corresponding to the storage cell physical layers in the same group are the same. Exemplarily, the multiple storage cell physical layers 10 may also include a third group GP3, and the third group GP3 may include one or more third storage cell physical layers. Accordingly, the reference voltage providing circuit 20 may also be used to: provide a third reference voltage VREF3 for the third storage cell physical layer through the bit line BL, and the third reference voltage VREF3 is different from both the first reference voltage VREF1 and the second reference voltage VREF2.

The following takes the case where the multiple storage unit physical layers 10 include two groups or three groups as an example to introduce the grouping method of the multiple storage unit physical layers 10.

In a possible embodiment, the plurality of storage unit physical layers 10 include a first group GP1 and a second group GP2, the plurality of first storage unit physical layers 11 in the first group GP1 may be obtained through one etching process, and the plurality of second storage unit physical layers 12 in the second group GP2 may be obtained through another etching process. Exemplarily, as shown in (a) of FIG. 7 , the plurality of storage unit physical layers 10 include 10 storage unit physical layers PL0 to PL9 obtained through two etching processes, the second group GP2 includes 5 storage unit physical layers PL0 to PL4 obtained through the first etching process, and the first group GP1 includes 5 storage unit physical layers PL5 to PL9 obtained through the second etching process.

In another possible embodiment, the multiple storage unit physical layers 10 include storage unit physical layers obtained through at least two etching processes, and each group includes at least one storage unit physical layer corresponding to each etching process in the at least two etching processes. Exemplarily, as shown in (b) of FIG7 , the multiple storage unit physical layers 10 include five storage unit physical layers PL0 to PL4 obtained through the first etching process, and five storage unit physical layers PL5 to PL9 obtained through the second etching process, and the multiple storage unit physical layers 10 correspond to three groups; wherein the first group GP1 includes storage unit physical layers PL0 to PL1 and PL5 to PL6, the second group GP2 includes storage unit physical layers PL2 to PL3 and PL7 to PL8, and the third group GP3 includes storage unit physical layers PL4 and PL9.

In another possible embodiment, the reference voltage reading ranges corresponding to the storage unit physical layers 11 in different groups are different. For example, the reference voltage reading ranges corresponding to the multiple first storage unit physical layers 11 in the first group GP1 are different from the reference voltage reading ranges corresponding to the multiple second storage unit physical layers 12 in the second group GP2. The reference voltage reading range may refer to a range of reference voltages that can simultaneously satisfy the correct reading of data "0" and "1". In practical applications, the reference voltage corresponding to each storage unit physical layer in the multiple storage unit physical layers 10 may be obtained through testing, and the reference voltage may refer to a reference voltage that can simultaneously satisfy the correct reading of data "0" and "1". Afterwards, the reference voltage reading range in which the reference voltage corresponding to each storage unit physical layer is located in the preset multiple reference voltage reading ranges may be determined, so that the storage unit physical layers whose reference voltages are in the same reference voltage reading range may be determined as the same group. The preset multiple reference voltage reading ranges may be set in advance, and the embodiments of the present application do not impose specific restrictions on this. Exemplarily, the multiple storage unit physical layers 10 may correspond to three groups, and the preset multiple reference voltage reading ranges may include three reference voltage reading ranges, namely (0, 0.3V), [0.3V, 0.5V] and (0.5V, 2V).

In an embodiment of the present application, by grouping the multiple storage cell physical layers 10, and providing different reference voltages for the storage cell physical layers in different groups through the reference voltage providing circuit 20, and providing the same reference voltage for the storage cell physical layers in the same group, it is possible to reduce the number of different reference voltages provided while achieving correct reading of data in the multiple storage cell physical layers 10, thereby reducing the complexity of the reference voltage providing circuit 20, and reducing the cost and occupied area of the reference voltage providing circuit 20.

Further, in combination with FIG6 , as shown in FIG8 , the three-dimensional memory may further include a bit line selector 30. The bit line selector 30 may be coupled between the plurality of bit lines BL and the reference voltage providing circuit 20. The bit line selector 30 may be used to select a bit line BL receiving the first reference voltage VREF1 or the second reference voltage VREF2 provided by the reference voltage providing circuit 20 from the plurality of bit lines BL.

For example, when reading data of the memory cells in the first column in the first memory cell physical layer 11, the reference voltage providing circuit 20 may be used to provide the first reference voltage VREF1, the bit line selector 30 may be used to select the first bit line BL1 to receive the first reference voltage VREF1, and provide the first reference voltage VREF1 to the first memory cell physical layer 11. For another example, when reading data of the memory cells in the second column in the second memory cell physical layer 12, the reference voltage providing circuit 20 may be used to provide the second reference voltage VREF2, the bit line selector 30 may be used to select the second bit line BL2 to receive the second reference voltage VREF2, and provide the second reference voltage VREF2 to the second memory cell physical layer 12.

Furthermore, as shown in FIG. 8 , the three-dimensional memory may further include: one or more decoders, and the one or more decoders may be used to decode the addresses of the storage units to be read.

In a possible embodiment, the one or more decoders may include three decoders, and the three decoders may be respectively a row address decoder 41, a column address decoder 42, and a physical layer address decoder 43. The row address decoder 41 may be used to decode the row address of the storage unit to be read; the column address decoder 42 may be used to decode the column address of the storage unit to be read; and the physical layer address decoder 43 may be used to decode the physical layer address of the storage unit to be read, and the physical layer address may refer to the address of the physical layer of the storage unit where the storage unit to be read is located.

In addition, as shown in FIG8 , the three-dimensional memory may further include: a plurality of bit line sense amplifiers BL_SA, and/or a global sense amplifier GSA. Each of the plurality of bit line sense amplifiers BL_SA may be connected in series with a bit line BL, and is used to amplify the signal transmitted in the bit line BL, for example, to amplify the potential on the bit line BL in the sensing and amplification stage in the above-mentioned reading process. The global sense amplifier GSA may be connected to the plurality of bit lines BL at the same time, and is used to globally amplify the signal transmitted in the plurality of bit lines BL, for example, to amplify the potential on the bit line BL in the sensing and amplification stage in the above-mentioned reading process. The global sense amplifier GSA may also be used to amplify input and output data, and is coupled with the column address decoder 42, and is used to amplify the column address decoded by the column address decoder 42, and transmit it to the bit line selector 30. The bit line selector 30 may select the corresponding bit line according to the amplified column address.

Furthermore, the reference voltage providing circuit 20 can be implemented in a variety of different ways, as long as it can provide a plurality of different reference voltages. The following takes the reference voltage providing circuit 20 providing the first reference voltage VREF1 and the second reference voltage VREF2 as an example to illustrate the specific structure of the reference voltage providing circuit 20.

In a first possible implementation, as shown in FIG. 9 , the reference voltage providing circuit 20 may include: a power pump 21 and a voltage regulating circuit 22 , and the output end of the power pump 21 may be coupled to the first input end of the voltage regulating circuit 22 .

The power pump 21 can be used to output a preset reference voltage. The voltage regulating circuit 22 can be used to receive the preset reference voltage and output a first reference voltage VREF1 and a second reference voltage VREF2 according to the preset reference voltage, a first ratio and a second ratio. The first ratio can be a ratio of the first reference voltage VREF1 to the preset reference voltage, and the second ratio can be a ratio of the second reference voltage VREF2 to the preset reference voltage.

Optionally, the voltage regulating circuit 22 may be a resistor voltage divider circuit. The resistor voltage divider circuit may be used to: divide the preset reference voltage according to a first ratio to output a first reference voltage VREF1; divide the preset reference voltage according to a second ratio to output a second reference voltage VREF2. Exemplarily, the resistor voltage divider circuit may be a resistor string, which may include multiple resistors. In practical applications, the voltage division processing of the first ratio and the second ratio may be achieved by configuring the resistance values of the multiple resistors.

In addition, as shown in FIG10 , the reference voltage providing circuit 20 may further include a digital to analog converter circuit (ADC). The output end of the digital to analog converter circuit ADC may be coupled to the second input end of the voltage regulating circuit 22. The input end of the digital to analog converter circuit ADC may be coupled to the output end of the physical layer address decoder 43.

The digital-to-analog conversion circuit ADC can be used to: receive a target physical layer address, and output an indication signal to the voltage regulating circuit 22 according to the target physical layer address, the indication signal being used to indicate outputting the first reference voltage VREF1 or the second reference voltage VREF2. The target physical layer address is the address of the selected storage unit physical layer among the multiple storage unit physical layers 10. Exemplarily, when the target physical layer address is the physical layer address of the first storage unit physical layer 11, the indication signal output by the digital-to-analog conversion circuit ADC can be used to indicate the voltage regulating circuit 22 to output the first reference voltage VREF1; when the target physical layer address is the physical layer address of the second storage unit physical layer 12, the indication signal output by the digital-to-analog conversion circuit ADC can be used to indicate the voltage regulating circuit 22 to output the second reference voltage VREF2.

Optionally, the reference voltage providing circuit 20 may further include an output amplifier (out amplifier), the input end of the output amplifier may be coupled to the output end of the voltage regulating circuit 22 , and is used to amplify the first reference voltage VREF1 and the second reference voltage VREF2 output by the voltage regulating circuit 22 .

In a second possible implementation, as shown in Fig. 10, the reference voltage providing circuit 20 may include: a first power pump 24 and a second power pump 25. The structures of the first power pump 24 and the second power pump 25 may be the same or different.

The first power pump 24 is used to output a first reference voltage VREF1. The second power pump 25 is used to output a second reference voltage VREF2. When the structures of the first power pump 24 and the second power pump 25 are the same, the circuit parameters of the first power pump 24 and the second power pump 25 may be different, and the circuit parameters may include the resistance value of the resistor. Exemplarily, the first power pump 24 and the second power pump 25 may both be low dropout regulators (LDOs), and the circuit parameters used to adjust the output voltage in the LDO may include the resistance ratio of the two resistors, so that the resistance ratio corresponding to the first power pump 24 may be different from the resistance ratio corresponding to the second power pump 25.

Optionally, as shown in FIG10 , the reference voltage providing circuit 20 may further include a selection switch 26. Two selection terminals of the selection switch 26 may be respectively coupled to the output terminal of the first power pump 24 and the output terminal of the second power pump 25. A fixed terminal of the selection switch 26 may be coupled to the output terminal of the physical layer address decoder 43.

The selection switch 26 may be used to receive a target physical layer address, and select to output a first reference voltage VREF1 or a second reference voltage VREF2 according to the target physical layer address. The target physical layer address is the address of a selected storage unit physical layer among the multiple storage unit physical layers 10. Exemplarily, when the target physical layer address is the physical layer address of the first storage unit physical layer 11, the selection switch 26 may be used to enable the first power pump 24 to select to output the first reference voltage VREF1; when the target physical layer address is the physical layer address of the second storage unit physical layer 12, the selection switch 26 may be used to enable the second power pump 25 to select to output the second reference voltage VREF2.

Furthermore, the reference voltages used in the data reading process of the three-dimensional memory (for example, the first reference voltage VREF1 and the second reference voltage VREF2) can be obtained through training, and can be trained before use (i.e., the life cycle is time0), or can be trained at different life cycles during use.

In a possible embodiment, when the reference voltage is trained before use, multiple preset reference voltages can be used to train multiple storage unit physical layers 10 in the three-dimensional memory in a reference voltage training mode, and based on the grouping of the multiple storage unit physical layers 10, the reference voltage corresponding to each group can be determined.

Exemplarily, as shown in FIG11 , the method may include the following steps. S11. Enter reference voltage training mode and initialize k=0, where k can be used to represent the kth storage unit physical layer. S12. Traverse multiple preset reference voltages, read the data of the storage unit in the kth storage unit physical layer, and determine the read pass rate of data "0" and "1" based on the read result. S13. Determine whether k is equal to n; if not (i.e., k is not equal to n), execute k=k+1 and return to S12; if yes (i.e., k is equal to n), execute S14. S14. Based on the read pass rate under different preset reference voltages, determine the reference voltage corresponding to each group, and write it into the three-dimensional memory.

In another possible embodiment, when the reference voltage is trained in different life cycles, the reference voltage corresponding to each group can be trained in the above-mentioned manner of training the reference voltage before use when the three-dimensional memory is in an idle state. The different life cycles can be reflected by the number of read and write times.

Exemplarily, as shown in FIG12 , the method may include the following steps. S21. Determine whether to enter the idle state; if not, return to the idle state; if so (i.e., enter the idle state), execute S22. S22. Query the number of read and write times. S23. Whether the number of read and write times meets the training trigger condition, for example, the number of read and write times is greater than or equal to the preset number; if not, return to the idle state, if so, execute S24. S24. Execute the reference voltage training process, and execute S25 after the training is completed. S25. Return to the idle state.

In an embodiment of the present application, by training the reference voltages used by the physical layers of storage cells in different groups during the data reading process, the accuracy of the reference voltages corresponding to the physical layers of storage cells in different groups can be ensured. In this way, when reading data from different physical layers of storage cells, the corresponding reference voltage can be provided to the selected physical layers of storage cells through the bit lines, thereby ensuring the correct reading of data from different physical layers of storage cells.

FIG. 13 is a flow chart of a reference voltage providing method provided in an embodiment of the present application. The method can be applied to the three-dimensional memory provided above. The method includes the following steps.

S301: Acquire a target physical layer address, where the target physical layer address is an address of a selected storage unit physical layer from among multiple storage unit physical layers.

The selected storage unit physical layer may be any one of the multiple storage unit physical layers, for example, the selected storage unit physical layer may be the first storage unit physical layer or the second storage unit physical layer.

In a possible embodiment, the three-dimensional memory can obtain a physical layer address and decode the physical layer address to obtain the target physical layer address. For example, the three-dimensional memory can include a physical layer address decoder, which can receive the physical layer address and decode the physical layer address to obtain the target physical layer address.

S302: Determine a reference voltage corresponding to the physical layer of the selected storage unit according to the target physical layer address.

The multiple storage unit physical layers may include two or more groups, each of which may include one or more storage unit physical layers. In the two or more groups, the reference voltages corresponding to the storage unit physical layers in different groups are different, and the reference voltages corresponding to the storage unit physical layers in the same group are the same.

In a possible embodiment, the multiple storage unit physical layers may include a first group and a second group. The first group may include multiple first storage unit physical layers, and/or the second group may include multiple second storage unit physical layers. Optionally, the reference voltage corresponding to the first storage unit physical layer in the first group may be a first reference voltage, and the reference voltage corresponding to the second storage unit physical layer in the second group may be a second reference voltage. The first reference voltage and the second reference voltage are different.

Furthermore, the plurality of storage unit physical layers may further include a third group, and the third group may include one or more third storage unit physical layers. The reference voltage corresponding to the third storage unit physical layer in the third group may be a third reference voltage. The third reference voltage is different from both the first reference voltage and the second reference voltage.

S303: Providing a corresponding reference voltage to the physical layer of the selected memory cell via the bit line.

In a possible embodiment, if the target physical layer address is the address of the physical layer of the first storage unit, a first reference voltage is provided to the physical layer of the first storage unit through a bit line; if the target physical layer address is the address of the physical layer of the second storage unit, a second reference voltage is provided to the physical layer of the second storage unit through a bit line. Further, if the target physical layer address is the address of the physical layer of the third storage unit, a third reference voltage is provided to the physical layer of the third storage unit through a bit line.

Exemplarily, the three-dimensional memory may include a reference voltage providing circuit, which can be used to: provide a first reference voltage to a first memory cell physical layer through a bit line, provide a second reference voltage to a second memory cell physical layer through a bit line, and provide a third reference voltage to a third memory cell physical layer through a bit line.

In a method embodiment of the present application, during the data reading process of a three-dimensional memory, when different physical layers of storage cells are selected, different reference voltages can be provided for different physical layers of storage cells through bit lines, so that data of different physical layers of storage cells can be read through different reference voltages, thereby solving the problem of affecting the reading accuracy due to inconsistencies in the size, process and performance of the physical layers of the storage cells.

In another embodiment of the present application, a storage device is also provided, as shown in FIG14 , the storage device may include a controller and a three-dimensional memory, the controller is used to control the reading and writing of the three-dimensional memory, and the three-dimensional memory may be any of the three-dimensional memories provided above. Optionally, the three-dimensional memory may be a three-dimensional ferroelectric memory, a three-dimensional MRAM, or a three-dimensional DRAM, etc.

In another embodiment of the present application, an electronic device is provided, which may include a circuit board and a storage device fixed on the circuit board, and the storage device is the storage device provided above. Optionally, the electronic device may include but is not limited to: a mobile phone, a tablet computer, a computer, a laptop computer, an ultra-mobile personal computer (ultra-mobile personal computer, umPC), a netbook, a camera, a camera, a wearable device, a vehicle-mounted device (for example, a car, a bicycle, an electric car, an airplane, a ship, a train, a high-speed rail, etc.), a virtual reality (virtual reality, VR) device, an augmented reality (augmented reality, AR) device or an intelligent robot, etc.

The detailed descriptions of the structure and data reading process of the three-dimensional memory mentioned above can be referred to in the corresponding embodiments of the reference voltage providing method, storage device and electronic device, and the embodiments of the present application will not be repeated here.

Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (18)

1. A three-dimensional memory, comprising: A plurality of storage unit physical layers arranged in a stacked manner, each storage unit physical layer comprising a plurality of rows and columns of storage units, the plurality of storage unit physical layers comprising a first storage unit physical layer and a second storage unit physical layer; A plurality of bit lines and a plurality of word lines, physically coupled to the plurality of memory cells; The reference voltage providing circuit is used to provide a first reference voltage for the first memory cell physical layer through the bit line, and to provide a second reference voltage for the second memory cell physical layer through the bit line, wherein the first reference voltage and the second reference voltage are different. 2. The three-dimensional memory according to claim 1, wherein the first reference voltage is used to read data of a storage cell in the first storage cell physical layer, and the second reference voltage is used to read data of a storage cell in the second storage cell physical layer. 3. The three-dimensional memory according to claim 1 or 2, characterized in that the size of the storage cell in the first storage cell physical layer is larger than the size of the storage cell in the second storage cell physical layer, and the first reference voltage is larger than the second reference voltage. 4. The three-dimensional memory according to any one of claims 1 to 3, wherein the reference voltage providing circuit comprises: A power pump, used for outputting a preset reference voltage; The voltage regulating circuit is used to output the first reference voltage and the second reference voltage respectively according to the preset reference voltage, the first ratio and the second ratio. 5. The three-dimensional memory according to claim 4, wherein the voltage regulating circuit comprises: a resistor voltage divider circuit, configured to divide the preset reference voltage according to the first ratio to output the first reference voltage; The resistor voltage divider circuit is further used to divide the preset reference voltage according to the second ratio to output the second reference voltage. 6. The three-dimensional memory according to claim 4 or 5, characterized in that the reference voltage providing circuit further comprises: A digital-to-analog conversion circuit is used to output an indication signal to the voltage regulation circuit according to a target physical layer address, wherein the indication signal is used to indicate output of the first reference voltage or the second reference voltage, and the target physical layer address is the address of a selected storage unit physical layer among the multiple storage unit physical layers. 7. The three-dimensional memory according to any one of claims 1 to 3, wherein the reference voltage providing circuit comprises: a first power pump, configured to output the first reference voltage; a second power pump, configured to output the second reference voltage; Wherein, the circuit parameters of the first power pump and the second power pump are different, and the circuit parameters include resistance values. 8. The three-dimensional memory according to claim 7, wherein the reference voltage providing circuit further comprises: The selection switch is used to select and output the first reference voltage or the second reference voltage according to a target physical layer address, wherein the target physical layer address is an address of a selected storage unit physical layer among the multiple storage unit physical layers. 9. The three-dimensional memory according to claim 6 or 8, characterized in that the three-dimensional memory further comprises: A physical layer address decoder is used to decode and output the target physical layer address. 10. The three-dimensional memory according to any one of claims 1 to 9, characterized in that the multiple storage unit physical layers include a first group and a second group; wherein the first group includes multiple first storage unit physical layers, and/or the second group includes multiple second storage unit physical layers. 11 . The three-dimensional memory according to claim 10 , wherein the first group is obtained through one etching process, and the second group is obtained through another etching process. 12. The three-dimensional memory according to claim 10, characterized in that the multiple storage unit physical layers include storage unit physical layers obtained through at least two etching processes, and the first group and the second group respectively include at least one storage unit physical layer corresponding to each etching process in the at least two etching processes. 13 . The three-dimensional memory according to claim 10 , wherein the reference voltage reading ranges corresponding to the first group and the second group are different. 14. The three-dimensional memory according to any one of claims 1 to 13, characterized in that the plurality of storage unit physical layers further comprises: a third storage unit physical layer; The reference voltage providing circuit is further used to provide a third reference voltage for the third storage unit physical layer through the bit line, and the third reference voltage is different from both the first reference voltage and the second reference voltage. 15 . The three-dimensional memory according to claim 1 , wherein the plurality of memory cell physical layers, the plurality of bit lines and the plurality of word lines are formed by a front-end process, and the reference voltage providing circuit is formed by a back-end process. 16. A reference voltage providing method, characterized in that it is used for reading data of a three-dimensional memory, the three-dimensional memory comprising a plurality of bit lines, a plurality of word lines and a plurality of memory cell physical layers stacked, the plurality of memory cell physical layers comprising a first memory cell physical layer and a second memory cell physical layer, the method comprising: Acquire a target physical layer address, where the target physical layer address is an address of a physical layer of a storage unit selected from the multiple physical layers of the storage units; If the target physical layer address is the address of the first storage unit physical layer, providing a first reference voltage to the first storage unit physical layer through the bit line; If the target physical layer address is the address of the second storage unit physical layer, a second reference voltage is provided to the second storage unit physical layer through the bit line, and the first reference voltage is different from the second reference voltage. 17. A storage device, characterized in that the storage device comprises a controller and a three-dimensional memory, the controller is used to control the reading and writing of the three-dimensional memory, and the three-dimensional memory is the three-dimensional memory according to any one of claims 1 to 15. 18. An electronic device, characterized in that the electronic device comprises a circuit board, and the storage device according to claim 17 fixed on the circuit board.