CN118689596A - Method, device, equipment and storage medium for processing cache miss state transactions - Google Patents

Abstract

The present application provides a method, device, electronic device and computer-readable storage medium for processing a cache missing state transaction, including: receiving a request message for a target request; the request message is a message generated by a missing state transaction generated by the target request; the missing state transaction indicates that the target request has not been successfully executed by the cache pipeline; parsing the request message, and determining the recovery process of the missing state according to the parsing result; operating the waiting register, the preparation register and the information register respectively according to the recovery process, and completing the recovery process through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline. The present application enables the missing state register to efficiently, accurately and with low power consumption to process cache missing state transactions.

Description

Method, device, equipment and storage medium for processing cache miss state transactions

Technical Field

The present application relates to the field of computer technology, and in particular to a method, device, electronic device and computer-readable storage medium for processing cache miss state transactions.

Background Art

The way of handling transactions in cache miss state is a design idea of non-blocking parallel transaction flow that is widely used in cache consistency design.

Currently, in the process of processing cache miss state transactions, in order to implement miss state transaction processing based on cache consistency, it often leads to inefficient related circuit design, high energy consumption and poor accuracy.

Summary of the invention

Embodiments of the present application provide a method, device, electronic device, and computer-readable storage medium for processing cache miss state transactions to solve the problems in the prior art.

In a first aspect, an embodiment of the present application provides a method for processing a cache miss state transaction, the method comprising:

Receive a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request is not successfully executed by the cache pipeline;

Parsing the request message, and determining a recovery process for the missing state according to the parsing result;

The waiting register, the preparation register and the information register are operated respectively according to the recovery process, and the recovery process is completed through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline;

Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process.

In a second aspect, an embodiment of the present application provides a device for processing a cache miss state transaction, the device comprising:

An acquisition module, configured to receive a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request has not been successfully executed by the cache pipeline;

A parsing module, used for parsing the request message and determining a recovery process of the missing state according to the parsing result;

a configuration module, configured to respectively operate the waiting register, the preparation register and the information register according to the recovery process, and complete the recovery process through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline;

Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

a memory for storing instructions executable by the processor;

The processor is configured to execute the instructions to implement the method of the first aspect.

In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

The embodiment of the present application parses the request message corresponding to the missing state transaction to obtain the recovery process of the missing state; and operates the waiting register, the preparation register and the information register respectively according to the recovery process, and completes the recovery process through the register values of the waiting register, the preparation register and the information register. The present application can realize the recovery process efficiently, accurately and with low power consumption by setting and resetting the waiting register, the preparation register and the information register respectively. This is because the design of these three types of registers is non-redundant and these three types of registers can be implemented by high-speed physical circuits, the energy consumption during execution is low and the circuit occupies a small area. In addition, the maintenance of the register values of these three types of registers is simple and efficient. The control of the recovery process can be realized by setting and resetting these three types of registers, so that the missing state register can realize the processing of cache missing state transactions efficiently, accurately and with low power consumption.

The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flowchart of a method for processing a cache miss state transaction provided by an embodiment of the present application;

FIG2 is a schematic diagram of a cache miss state transaction processing architecture provided by an embodiment of the present application;

FIG3 is a block diagram of a cache miss state transaction processing device provided by an embodiment of the present application;

FIG4 is a block diagram of a device of the present application;

FIG5 is a schematic diagram of the structure of the server in some embodiments of the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and/or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and/or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character "/" generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

In order to improve execution efficiency and reduce the interaction between the processor and memory, modern processors can integrate a multi-level cache architecture on the processor. The common architecture is a three-level cache structure, including: Level 1 cache L1, Level 2 cache L2 and Level 3 cache L3. Level 1 cache L1 is the cache closest to the processor, it has the smallest capacity and the fastest speed; Level 2 cache L2 has a larger capacity, but is slower than Level 1 cache L1. Level 2 cache L2 is the buffer of Level 1 cache L1. The function of Level 2 cache L2 is to store data that is needed for processor processing but cannot be stored by Level 1 cache L1; Level 3 cache L3 has the largest capacity and is also the slowest level. Level 3 cache L3 and memory can be regarded as buffers for Level 2 cache L2.

When the processor is running, the processor will first go to the first-level cache L1 to find the required data according to the memory access instruction, then go to the second-level cache L2, and then go to the third-level cache L3. If the third-level cache does not find the data it needs, it will get the data from the memory. The longer the search path, the longer it takes, so if you need to get certain data very frequently, make sure that the data is in the first-level cache L1, so that the speed will be very fast. Among them, the memory access instruction is an instruction to read data from a specified address in the memory, or write data to a specified address in the memory.

In the above process, if the memory access instruction does not hit in the first-level cache L1 (meaning that the data requested by the memory access instruction is not stored in the first-level cache L1), the memory access instruction will continue to be searched whether it hits in the second-level cache L2. If it hits in the second-level cache L2, the second-level cache L2 will refill the data requested by the memory access instruction into the first-level cache L1; if it does not hit in the second-level cache L2, the memory access instruction will continue to be searched whether it hits in the third-level cache L3. If it hits in the third-level cache L3, the third-level cache L3 will refill the data requested by the memory access instruction into the second-level cache L2, and then the second-level cache L2 will refill the data into the first-level cache L1. If it does not hit in the third-level cache L3, it is necessary to further search for data in the memory.

When a memory access instruction misses in a certain level of cache, it means that the memory access instruction currently processed by the cache pipeline has a cache miss status transaction, that is, a transaction generated when the cache pipeline cannot successfully execute the memory access instruction. At this time, the miss status register (MSHR, Miss-statusHandlingRegisters) is needed to handle the cache miss status transaction. The miss status register is a register used to record each unfinished transaction. The recorded information includes the invalid address, keyword information, and unfinished instructions. Once the problem that prevents the successful execution of the memory access instruction is eliminated, the memory access instruction in the miss status register can re-enter the pipeline queue for execution.

FIG. 1 is a flowchart of a method for processing a cache miss state transaction provided by an embodiment of the present application. As shown in FIG. 1 , the method may include:

Step 101, receiving a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request has not been successfully executed by the cache pipeline.

In the embodiment of the present application, a MSHR design scheme based on a coherent hub interface (CHI) is implemented, which aims to standardize the implementation process of MSHR through the CHI protocol. When a target instruction misses in a certain level of cache (such as the target instruction cannot be read or written in the cache at this level), it means that a cache miss state transaction occurs in the target instruction currently processed by the cache pipeline, that is, the cache pipeline generates a cache miss state transaction when the target instruction cannot be successfully executed. At this time, the cache miss state transaction needs to be processed through the miss state register (MSHR).

Further, referring to Fig. 2, a schematic diagram of the architecture of a MSHR is shown, including a MSHR, a cache pipeline, a receiving channel and a sending channel. The MSHR is connected to the cache pipeline, the receiving channel and the sending channel respectively.

Among them, the Miss Status Register (MSHR) is a concept related to cache control in computer architecture. When an instruction attempts to obtain data from the cache, but the data does not hit the cache, a cache miss status (i.e., cache miss status transaction) is subsequently generated, and the corresponding information (such as the address of the miss, the type of operation, the size of the data block, etc.) is stored in the MSHR, which allows the cache pipeline to continue to perform other operations while waiting for the cache data to return without having to stop. Once the cache receives the data later, it can retrieve the corresponding information from the MSHR and continue to perform the operation to complete the data acquisition process.

Cache pipeline (CLP, CachePipeLine) is a technology in computer architecture that is used to improve the throughput and performance of cache access. The cache pipeline can provide cache-related information to MSHR. The cache pipeline includes multiple sequentially arranged data bits, each data bit corresponds to a pipeline moment, and different data bits correspond to different pipeline moments. The request is used to enter the pipeline from the initial data bit of the cache pipeline to start execution, and as time passes, the data bit is changed until it leaves the cache pipeline after the execution is completed. Based on this structure, the cache pipeline can execute instructions efficiently and accurately. The receiving channel is the channel used by MSHR to receive external information; the sending channel is the channel used by MSHR to send information to the outside.

In this step, for the target request that generates a missing state transaction, it means that the cache pipeline currently fails to successfully execute the target request. The reasons for the unsuccessful execution may include that the target data requested to read/write by the target request is not stored in the target cache, which is also called a target request miss in the target cache. At this time, the target cache will generate a request message for the missing state transaction of the target request and send the request message to MSHR through the RXREQ channel. This is called the enqueueing of the cache missing state transaction. The request message includes the invalid address, transaction type, keyword information, etc. The purpose of the request message is to instruct MSHR to establish a recovery process to find the target data required for the target request and provide the target data to the target cache and execute it.

Step 102: parse the request message, and determine the recovery process of the missing state according to the parsing result.

In an embodiment of the present application, MSHR can parse the request message, and the obtained parsing result reflects the cause of the cache miss state transaction. Based on the parsing result, a recovery process can be formulated to solve the problem corresponding to the cache miss state transaction.

The recovery process is designed to solve the problem in the cache that prevents the target instruction from being successfully executed, so that the subsequent target instruction can re-enter the cache pipeline and be successfully executed. For example, the target instruction is an instruction to read the target data in the L2 cache, but because the target data is not stored in the L2 cache, the target instruction does not hit in the L2 cache. After the MSHR finds the target data and stores it in the L2 cache, the problem that prevents the target instruction from being successfully executed is solved, and the target instruction can be successfully executed.

Specifically, the recovery process includes MSHR first interacting with the cache pipeline to determine whether there is a target object that may contain the target data in addition to the target cache; when it is determined that the target object exists, MSHR interacts with the target object to control the target object to provide the target data to the target cache, and finally MSHR interacts with the target cache to complete the recovery process after determining that the target cache has indeed received the target data.

Step 103, according to the recovery process, the waiting register, the preparation register and the information register are operated respectively, and the recovery process is completed through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline.

Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process.

In the embodiment of the present application, referring to FIG. 2, in the MSHR design concept, the MSHR can maintain three types of registers: a waiting register, a preparation register, and an information register. The register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed. The register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the parsing result and the execution information in the recovery process. The setting of the waiting register indicates that the MSHR needs to wait for the end of a certain behavior. When all the waiting registers are not set, it means that a cache missing state transaction completes all processes and can be dequeued (referring to a cache missing state transaction in the MSHR to complete the required operations and no longer occupy MSHR resources). The setting of the preparation register indicates that the MSHR currently has a read/write request that needs to be sent by the cache pipeline or a message sent to each sending channel. The information register records information transmitted from the outside of the MSHR. This information either indicates that a certain message has been received or indicates the content of the message that needs to be sent.

For example, when the recovery process corresponding to a cache miss state transaction begins, the MSHR needs to interact with the cache pipeline, the target object, and the target cache in sequence. When the cache miss state transaction enters the MSHR, the MSHR can first set the wait register 1, wait register 2, and wait register 3 respectively. After the wait register 1 is set, it is used to indicate that the current interaction with the cache pipeline needs to be completed; after the wait register 2 is set, it is used to indicate that the current interaction with the target object needs to be completed; after the wait register 3 is set, it is used to indicate that the current interaction with the target cache needs to be completed. In addition, when the cache miss state transaction enters the MSHR, the MSHR first needs to send a request to the cache pipeline. At this time, the MSHR can set the prepare register 1. After the prepare register 1 is set, it is used to indicate that the operation of sending a request to the cache pipeline needs to be executed immediately. The specific information of the cache miss state transaction and the information during the execution process can be recorded in the information register for retrieval and use during the execution process. It can be seen that through the maintenance of register values by these three types of registers, the step generation and flow of the recovery process are accurately and efficiently realized, and the implementation of the recovery process is standardized.

The embodiment of the present application can realize the recovery process efficiently, accurately and with low power consumption by setting and resetting the three types of registers respectively. This is because the design of the three types of registers is non-redundant, and the three types of registers are implemented by high-speed physical circuits, the energy consumption during execution is low and the circuit occupies a small area, and the maintenance of register values by the three types of registers is simple and efficient. Setting and resetting the three types of registers can realize the control of the flow of steps in the recovery process, so that the cache missing state transaction can be efficiently processed.

Specifically, MSHR has a two-dimensional structure. When MSHR is regarded as a two-dimensional array including multiple elements, each element corresponds to a cache miss status transaction, and each element is configured with corresponding three types of registers (wait register, ready register and information register). When multiple elements in MSHR are unrelated to each other, the three types of registers corresponding to these elements can be used to realize simultaneous and parallel processing of cache miss status transactions corresponding to multiple elements, thereby improving the throughput of MSHR in processing cache miss status transactions.

In the embodiment of the present application, the specific situations of the waiting register, the preparation register and the information register are enumerated respectively:

The wait registers include but are not limited to the following 8 registers:

mshr_pipeline_busy: set to indicate waiting for cache pipeline feedback;

mshr_snp_busy: set to indicate waiting for a reply from the target object;

mshr_mem_rd_busy: set to wait for SNF (SubordinateNodeFullcoherent, a component used to receive, process, and reply to messages initiated by MSHR) to complete the read transaction request;

mshr_mem_wr_busy: set to wait for SNF to complete the write transaction request;

mshr_compack_busy: When set, it indicates waiting to receive the response message sent by the target buffer;

mshr_datbuf_rn_busy: When set, it indicates that data is received from the cache pipeline or RXDAT channel and needs to wait for the target data to be transmitted. The transmission direction is to send to the target cache.

mshr_datbuf_sn_busy: When set, it indicates that a message from the cache pipeline or RXDAT channel has been received and it needs to wait for the data to be transmitted. The transmission direction is to send it to SNF.

mshr_rsp_busy: When set, it indicates that the TXRSP message is waiting to be sent. These RSP messages (Response messages, a type of message in the CHI protocol) are DBIDResp, Comp, CompDBIDResp, ReadReceipt, etc. (the above are all RSP message types defined in the CHI protocol).

The preparation registers include but are not limited to the following 11 registers:

mshr_cachepipeline_rd_rdy: When set, it indicates that a read request needs to be sent to the cache pipeline;

mshr_cachepipeline_fill_rdy: When set, it indicates that a write request needs to be sent to the cache pipeline;

mshr_txreq_rd_rdy: When set, it indicates that a read message needs to be sent to the TXREQ channel. The specific content of the message is provided by the information register;

mshr_txreq_wr_rdy: When set, it indicates that a write message needs to be sent to the TXREQ channel. The specific content of the message is provided by the information register;

mshr_txrsp_rdy: When set, it indicates that an RSP message needs to be sent to the TXRSP channel. The specific content of the message is provided by the information register;

mshr_txrsp_comp_rdy: When set, it indicates that a response (comp) message needs to be sent to the TXRSP channel. The specific content of the message is provided by the information register;

mshr_txrsp_dbid_rdy: When set, it indicates that a database identification (DBID) message needs to be sent to the TXRSP channel. The specific content of the message is provided by the information register;

mshr_txrsp_rdreceipt_rdy: When set, it indicates that a ReadReceipt message needs to be sent to the TXRSP channel. The specific content of the message is provided by the information register;

mshr_txsnp_rdy: When set, it indicates that a SNP (snoop) message needs to be sent to the TXSNP channel. The specific content of the message is provided by the information register;

mshr_txdat_rn_rdy: When set, it indicates that a data message needs to be sent to the TXDAT channel, and its transmission direction is to send to the target buffer. The specific content of the message is provided by the information register;

mshr_txdat_sn_rdy: When set, it indicates that a data message needs to be sent to the TXDAT channel, and its transmission direction is to send to SNF. The specific content of the message is provided by the information register;

Information registers include but are not limited to the following 36 registers:

mshr_snp_bit: records the target objects to which the SNP message needs to be sent;

mshr_l3hit: records whether the last level cache (LLC, LastLevelCache, such as L3 in the third level cache) hits;

mshr_snp_direct: records whether the SNP message needs to be sent to only one target object;

mshr_snp_cnt: records the number of SNP messages that need to be sent;

mshr_snp_opcode: records the type of SNP message to be sent;

mshr_rettosrc: records the rettosrc field content of the SNP message to be sent (the content of the SNP message in the CHI protocol specification);

mshr_l3_resp: records the resp field content in the data message that needs to be sent when LLC hits (the content in the DAT message in the CHI protocol specification);

mshr_opcode: records the opcode field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_qos: records the qos field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_memattr: records the memattr field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_srcid: records the srcid field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_txnid: records the txnid field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_excl: records the excl field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_ne: records the ne field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_order: records the order field content in the Request message received from the RXREQ channel (the content in the REQ message in the CHI protocol specification);

mshr_rdnosnp: records that the Request message type received from the RXREQ channel is readnosnp (REQ message type in the CHI protocol specification). This application does not list all similar registers one by one. The Request message type in the CHI protocol specification can be reflected in this form, such as mshr_readunique, etc.;

mshr_snp_dirty: records the dirty data received from the target object through the RXDAT channel;

mshr_snp_getid: records the dataid field content in the data message received from the target object through the RXDAT channel (data message type in the CHI protocol specification);

mshr_snpdat_getone: records the data packets received from the target object through the RXDAT channel. It flips once each time it is received;

mshr_snp_getnum: records the responses received from the target object. It increases by one each time a response from the target object is received;

mshr_snpfwd: records whether a snpfwd type message is received;

mshr_rn_dat_gat_d: records whether dirty data is received from the requester;

mshr_dat_rngetone: records the data packets received from the requester through the RXDAT channel. Each time a data packet is received, it is flipped once;

mshr_dat_memgetone: records the data packets received from SNF through the RXDAT channel. Each time a data packet is received, it is flipped once;

mshr_dat_old_get: records whether to obtain complete data from the target object or SNF (a cache pipeline);

mshr_dat_new_get: records whether to obtain complete data from the requester (a cache pipeline);

mshr_dat_stop_cb: records whether a CopyBackWrData (data message type in the CHI protocol specification) with an invalid or clean shared status is received;

mshr_cb_wr_mem: records whether it is necessary to send a Request message to SNF after receiving data from requesterdirty;

mshr_get_compack: records whether a response message is received;

mshr_dbid: records the content of the DBID field in the DBIDResp or CompDBIDResp (response message type in the CHI protocol specification) received from the RXRSP channel;

mshr_get_dbid: records whether a DBIDResp or CompDBIDResp message is received;

mshr_get_comp: records whether a response message or CompDBIDResp message is received;

mshr_get_rd_receipt: records whether the ReadReceipt message is received;

mshr_get_retry: records whether the RetryAck message is received;

mshr_pcrdtype: records the content of the pcrdtype field in the RetryAck message received from the RXRSP channel;

mshr_resent: records whether all RetryAck and pcrdgnt messages with the same content in the message field pcrdtype have been received.

Optionally, the target request is used to process target data, and the target request does not hit in the target cache. The recovery process determined in step 102 includes:

Step A1, interacting with the cache pipeline to determine whether there is a target object that may store the target data; the target object is a cache object or memory object other than the target cache.

Step A2: When it is determined that the target object exists, interact with the target object so that the target data is provided to the target cache.

Step A3: interact with the target cache, and complete the recovery process after determining that the target cache has received the target data.

In the embodiment of the present application, based on steps A1-A3, an instruction attempts to obtain data from the cache, but when the data does not hit the cache, a cache miss state (i.e., cache miss state transaction) will be generated later. Once the cache that missed the data receives the data later, the cause of the cache miss state transaction is eliminated, and the corresponding information can be retrieved from the MSHR, and the operation can be continued to complete the data acquisition process.

Therefore, the embodiment of the present application can construct a recovery process based on the results obtained by parsing the request message. Specifically, the request message includes the invalid address, transaction type, keyword information, etc., which describes the specific situation and cause of the cache missing state transaction. The recovery process constructed based on this information aims to find the target object storing the target data and provide the target data to the target cache that needs the data, thereby solving the problem of the target instruction not hitting the target cache.

For example, the target instruction is an instruction to read the target data in the L2 cache, but since the target data is not stored in the L2 cache, the target instruction does not hit in the L2 cache. The recovery process specified based on this information includes: MSHR interacts with the cache pipeline to determine a number of target objects that may store the target data, then MSHR interacts with the target object to control the target object that actually stores the target data to provide the target data to the L2 cache, and finally MSHR interacts with the L2 cache to complete the recovery process after determining that the L2 cache has actually received the target data. After the target data is stored in the L2 cache, the problem that hinders the successful execution of the target instruction is solved, and the target instruction can be successfully executed.

Optionally, the target request is used to process target data, and the target request does not hit in the target cache. Step 103 may specifically include:

Sub-step 1031, respectively setting the first waiting register, the second waiting register, the third waiting register and the first preparation register, thereby initiating a read request to the cache pipeline, and saving the parsing result to the information register. Optionally, when it is determined that the cache pipeline has received the read request, it also includes: step B1, resetting the register value of the first preparation register.

Sub-step 1032, receiving the read result sent by the cache pipeline, determining the target object that may store the target data based on the read result, and setting the fourth wait register and the second preparation register respectively, thereby sending a monitoring message to the target object, so that the target object can provide the target data to the target cache. Optionally, when receiving the read result sent by the cache pipeline, it also includes: step B2, resetting the register values of the first wait register and the second wait register. Optionally, when the monitoring message is successfully sent to the target object, it also includes: step B3, resetting the register value of the second preparation register. Optionally, in the process of providing target data to the target cache, it also includes: step B4, resetting the register value of the fourth wait register.

Sub-step 1033: upon receiving the response message sent by the target cache, determining that the target cache has received the target data and completing the recovery process. Optionally, upon receiving the response message sent by the target cache, the process further includes: step B5: resetting the register value of the third waiting register.

Optionally, the register value after the first wait register is set is used to represent waiting for feedback from the cache pipeline; the register value after the second wait register is set is used to represent waiting for a response to the monitoring message; the register value after the third wait register is set is used to represent waiting for a response message from the target cache; the register value after the first preparation register is set is used to represent the need to initiate a read request to the cache pipeline; the register value after the fourth wait register is set is used to represent waiting for the target object to complete the target data provision transaction; the register value after the second preparation register is set is used to represent the need to send a monitoring message to the target object. It should be noted that the register values of the wait register and the preparation register in the embodiment of the present application can be Boolean distribution values, such as register values can be 1 or 0. The register value after setting can be 1, and the register value after resetting can be 0.

In the embodiment of the present application, for sub-steps 1031-1033, when the recovery process starts to execute, it is first necessary to determine the overall step process and the operation that needs to be executed immediately. Specifically, the embodiment of the present application can establish the overall step process by setting the first wait register (mshr_pipeline_busy), the second wait register (mshr_snp_busy), and the third wait register (mshr_compack_busy) respectively, that is, the first wait register reflects that MSHR needs to wait for the interaction with the cache pipeline to complete, so as to determine the target object that may store the target data; the second wait register reflects that MSHR needs to wait for the interaction with the target object to complete, so that the target data is provided to the target cache; the third wait register reflects that MSHR needs to wait for the interaction with the target cache to complete, so as to determine that the target cache has indeed received the target data.

In the embodiment of the present application, the establishment of the operation that needs to be executed immediately can be achieved by setting the first preparation register (mshr_cachepipeline_rd_rdy), that is, when the recovery process starts to execute, the MSHR needs to immediately initiate a read request to the cache pipeline, and setting the first preparation register can control the MSHR to immediately initiate a read request to the cache pipeline. In addition, when the MSHR determines that the cache pipeline has received the read request, the register value of the first preparation register can be reset, which indicates that the operation represented by the first preparation register (mshr_cachepipeline_rd_rdy) has been completed.

Furthermore, the cache pipeline records the execution information of each cache object on the data during its historical operation. Therefore, by sending a read request to the cache pipeline, MSHR can determine which target objects may store the target data based on the read result returned by the cache pipeline in response to the read request, and the interaction between MSHR and the cache pipeline is also used to determine whether the third-level cache L3 also misses the target data (if L3 misses, the target data needs to be found from the memory). After determining the target object, MSHR needs to immediately send a snoop message to the target object, and the snoop message is used for the target object to provide the target data to the target cache. Therefore, when MSHR determines the target object that may store the target data based on the read result sent by the cache pipeline, it can set the fourth wait register (mshr_mem_rd_busy), thereby adding a waiting item for the target object to complete the target data provision transaction: and MSHR can also set the second preparation register (mshr_txsnp_rdy) at the same time, thereby controlling MSHR to immediately send a snoop message (snoop message) to the target object.

In addition, when MSHR determines that it has received the read result sent by the cache pipeline, the register values of the first wait register and the second wait register can also be reset, which indicates that the wait represented by the first wait register (mshr_pipeline_busy) for interaction with the cache pipeline has been completed, and the wait represented by the second wait register (mshr_snp_busy) for interaction with the target object has been completed. Further, when MSHR successfully sends a monitoring message to the target object, the register value of the second preparation register (mshr_txsnp_rdy) can also be reset, which indicates that the matter of sending the monitoring message to the target object has been completed. Further, in the process of the target object providing target data to the target cache, the register value of the fourth wait register can also be reset, which indicates that the transaction of waiting for the target object to complete the provision of target data represented by the fourth wait register (mshr_mem_rd_busy) has been completed.

Finally, when MSHR receives the response message sent by the target cache, the register value of the third waiting register (mshr_compack_busy) can be reset, which means that MSHR determines that the target cache has received the target data and has completed the matter of waiting for the response message of the target cache represented by the third waiting register (mshr_compack_busy). At this time, MSHR can complete the recovery process. In addition, the parsing results obtained by parsing the request message and the execution information generated in the entire recovery process can be stored in the information register for use by each link in the recovery process.

It can be seen that through the above-mentioned setting, resetting and information recording of the three types of registers (wait register, preparation register, information register), the steps in the recovery process and the step flow can be quickly determined, and the control of the steps in the recovery process can be accurately achieved.

Optionally, sub-step 1033 may specifically include:

Sub-step 10331: When a response message sent by the target cache is received and all wait registers are not set, it is determined that the target cache has received the target data and the recovery process is completed.

In the embodiment of the present application, the termination condition of the recovery process is when all the waiting registers are not set, that is, there are no unfinished waiting items, and at this time it can be determined that the recovery process is completed.

Optionally, sub-step 1032 may specifically include:

Sub-step 10321: Send a monitoring message to the target object, where the monitoring message is used for the target object to send the target data directly to the target cache.

Or, sub-step 10322, sending a monitoring message to the target object, receiving target data sent by the target object in response to the monitoring message, and then forwarding the target data to the target cache.

In the embodiment of the present application, there are two ways for the target object to provide the target data to the target cache. Way 1 is the scheme shown in sub-step 10321, that is, the target object directly sends the target data to the target cache. For example, assuming that there are multiple processors, each processor has a corresponding L2 cache, there are multiple L2 caches in the scenario, and the target instruction does not hit in L2 cache 1. After the interaction between MSHR and the cache pipeline, it is determined that the target data may be stored in L2 cache 2. In the case that L2 cache 2 does store the target data, L2 cache 2 can directly send the target data to L2 cache 1.

Mode 2 is the scheme shown in step 10322, that is, the target object directly sends the target data to MSHR first, and then MSHR forwards the target data to the target cache. For example, assuming that there are multiple processors, each processor has a corresponding L2 cache, there are multiple L2 caches in the scenario, and the target instruction does not hit in L2 cache 1. After the interaction between MSHR and the cache pipeline, it is determined that the target data may be stored in L2 cache 2. In the case that L2 cache 2 does store the target data, L2 cache 2 can directly send the target data to MSHR, and then MSHR forwards the target data to L2 cache 1.

It should be noted that, assuming that there are multiple processors, each processor has a corresponding secondary cache, there are multiple secondary caches in the scenario, and the target request does not hit in the secondary cache 1. In the case where the target request is a read request, after MSHR sends a snoop message to multiple secondary caches (excluding secondary cache 1) that may contain target data, if these secondary caches that receive the snoop message do store the target data, the secondary cache that does store the target data can directly send the target data to the secondary cache 1, or the secondary cache that does store the target data can first send the target data to MSHR, and then MSHR forwards it to the secondary cache 1.

In the case where the target request is a write request, after MSHR sends a snoop message to multiple secondary caches (excluding secondary cache 1) where the target data may exist, the snoop message will enable the received secondary cache to clear the target data stored in it and provide the target data to secondary cache 1.

In addition, if the target data does not exist in both the L2 cache and the L3 cache, the MSHR sends a request message to the memory through the TXREQ channel; the request message informs the memory which target data is required. In the case where the target request is a read request, the memory can feedback a data message to the MSHR, and the data message includes the required target data. The MSHR can further forward the target data to the missed L2 cache, or the memory can directly feedback the data message to the missed L2 cache so that the missed L2 cache can obtain the target data. In the case where the target request is a write request, the memory can feedback a response message including the target data to the MSHR, and then the MSHR can send a data message including the target data to the missed L2 cache, and the data message includes the data to be written.

Optionally, when the target request is a write request, sub-step 1033 may specifically include:

Sub-step 10323, sending a monitoring message to the target object, wherein the monitoring message is used for the target object to provide the target data to the target cache when the target data is stored so that the write request can be successfully executed, and to clear the target data stored by the target object to ensure data consistency.

In the embodiment of the present application, the CHI protocol standardizes the data consistency problem in the cache processing process. The data consistency problem mainly occurs when the target request is a write request. For example, assuming that there are multiple processors, each processor has a corresponding secondary cache, then there are multiple secondary caches in the scenario, each secondary cache includes 10 cache blocks, and the target request is to write the target data in cache block 5 of secondary cache 1, but because cache block 5 of secondary cache 1 does not store the target data, the target request misses in secondary cache 1, but the cache blocks 5 of secondary cache 2 and secondary cache 3 each store the target data. Target data, then through the recovery process of cache missing state transactions, after finding the target data (from L2 cache 2, L2 cache 3, L3 cache or memory) and storing it in cache block 5 of L2 cache 1, the target request can be successfully executed, and the write operation of the target data in cache block 5 of L2 cache 1 is realized. However, based on the data consistency requirement, if the stored target data is not cleared in the cache blocks 5 of L2 cache 2 and L2 cache 3 (the stored target data must be cleared in other storage objects other than L2 cache 1), data inconsistency problem will be caused, that is, dirty data will appear. This is because after the target request writes the target data in cache block 5 of L2 cache 1, the target data changes, while the target data stored in other storage objects other than L2 cache 1 that store the target data do not receive the write operation, that is, the target data stored in these storage objects are inconsistent with the target data in cache block 5 of L2 cache 1 after the write operation, which leads to inconsistency of the same data in different storage objects, which means that the data of the same address is different in different L2 caches, resulting in calculation errors, which in turn affects the correct operation of the program.

Specifically, if the target request is a request to write to the target cache block of the target cache, it is first determined whether the target cache block stores data. If the target cache block of the target cache does not store data, it is necessary to ensure that the same target cache block of other target caches at the same level also does not store data before performing the write operation, thereby ensuring data consistency. If the target cache block of the target cache stores data, it is necessary to clear the target data stored in other storage objects except the target cache, to ensure that after the target cache is refilled, the target data is only stored in the target cache block of the target cache, and then perform the write operation, thereby ensuring data consistency.

Therefore, in this step, the target object that receives the monitoring message can provide the target data to the target cache to successfully execute the write request if the target data is stored, and at the same time delete the target data stored in the target object. In this way, only the target cache stores the unique target data globally. After the write operation on the target data occurs, the updated target data also exists only in the target cache, and no other storage object will store the target data on which the write operation has not occurred, which ensures the consistency of the target data globally.

In the embodiment of the present application, a specific example of processing a cache missing state transaction is now provided:

Assume that the target request is a ReadUnique request, which is used to perform a write operation in cache block 1 of L2 cache 1, and the other L2 caches and L3 caches of the processor do not store the target data for the write operation, the size of the cache block is 64 bytes, and the width of the data field of the data message is 32 bytes. The ReadUnique request misses cache block 1 of L2 cache 1.

S1. The cache miss status transaction corresponding to the ReadUnique request is queued in MSHR, and the mshr_pipeline_busy, mshr_snp_busy, mshr_compack_busy, and mshr_cachepipeline_rd_rdy registers are set, and the relevant information is saved in the information register.

S2. MSHR initiates a read request to the cache pipeline. After confirming that the cache pipeline has received the read request, it resets the mshr_cachepipeline_rd_rdy register.

S3. The cache pipeline feeds back the read request result to MSHR. MSHR sets the mshr_txreq_rd_rdy and mshr_mem_rd_busy registers according to the read request result, and resets the mshr_snp_busy and mshr_pipeline_busy registers at the same time.

S4. MSHR sends a request message to the memory through the TXREQ channel. If the message is sent successfully, the mshr_txreq_rd_rdy register can be reset.

S5. MSHR receives the first data message from the memory, sets the mshr_dat_memgetone and mshr_datbuf_rn_busy registers, and resets the mshr_mem_rd_busy register.

S6. MSHR receives the second data message from the memory and sets the mshr_txdat_rn_rdy register.

S7, MSHR sends a data message to the secondary cache 1 through the TXDAT channel. Successful message transmission can reset the mshr_txdat_rn_rdy and mshr_datbuf_rn_busy registers.

S8. When receiving the response message sent by the L2 cache 1, the MSHR resets the mshr_compack_busy register.

S9. When all the waiting registers are not set, the recovery process of the current cache miss state transaction ends.

In summary, the embodiment of the present application can parse the request message corresponding to the missing state transaction to obtain the recovery process of the missing state; and operate the waiting register, the preparation register and the information register respectively according to the recovery process, and complete the recovery process through the register values of the waiting register, the preparation register and the information register. The present application can realize the recovery process efficiently, accurately and with low power consumption by setting and resetting the waiting register, the preparation register and the information register respectively. This is because the design of these three types of registers is non-redundant and these three types of registers can be implemented by high-speed physical circuits, the energy consumption during execution is low and the circuit occupies a small area. In addition, the maintenance of the register values of these three types of registers is simple and accurate. Setting and resetting these three types of registers can realize the control of the recovery process, so that the missing state register can realize the processing of cache missing state transactions efficiently, accurately and with low power consumption.

FIG3 is a block diagram of a cache miss state transaction processing device provided by an embodiment of the present application, the device comprising:

The acquisition module 301 is used to receive a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request has not been successfully executed by the cache pipeline;

The parsing module 302 is used to parse the request message and determine the recovery process of the missing state according to the parsing result;

The configuration module 303 is used to operate the waiting register, the preparation register and the information register respectively according to the recovery process, and complete the recovery process through the register values of the waiting register, the preparation register and the information register, so as to eliminate the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline;

Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process.

Optionally, the target request is used to process target data, and the target request does not hit in the target cache, and the recovery process includes:

Interacting with the cache pipeline to determine whether there is a target object that may store the target data; the target object is a cache object or a memory object other than the target cache;

When it is determined that the target object exists, interacting with the target object so that the target data is provided to the target cache;

The device interacts with the target cache and completes the recovery process after determining that the target cache has received the target data.

Optionally, the target request is used to process target data, and the target request does not hit in the target cache. The configuration module 303 includes:

A first interaction submodule, used for respectively setting a first waiting register, a second waiting register, a third waiting register and a first preparation register, so as to initiate a read request to the cache pipeline, and save the parsing result to the information register;

a second interaction submodule, configured to receive a read result sent by the cache pipeline, determine a target object that may store the target data according to the read result, and respectively set a fourth wait register and a second prepare register, thereby sending a monitoring message to the target object, so that the target object provides the target data to the target cache;

The third interaction submodule is used to determine that the target cache has received the target data and complete the recovery process when receiving a response message sent by the target cache.

Optionally, the register value after the first wait register is set is used to represent waiting for feedback from the cache pipeline; the register value after the second wait register is set is used to represent waiting for a response to the monitoring message; the register value after the third wait register is set is used to represent waiting for a response message from the target cache; the register value after the first preparation register is set is used to represent the need to initiate a read request to the cache pipeline; the register value after the fourth wait register is set is used to represent waiting for the target object to complete the transaction of providing the target data; the register value after the second preparation register is set is used to represent the need to send a monitoring message to the target object.

Optionally, the device further comprises:

A first reset module, configured to reset the register value of the first preparation register when it is determined that the cache pipeline has received the read request;

A second reset module, configured to reset register values of the first wait register and the second wait register upon receiving a read result sent by the cache pipeline;

A third resetting module, configured to reset the register value of the second preparation register when the monitoring message is successfully sent to the target object;

a fourth resetting module, configured to reset the register value of the fourth waiting register in the process of providing the target data to the target cache;

The fifth resetting module is used to reset the register value of the third waiting register when receiving the response message sent by the target cache.

Optionally, the third interaction submodule includes:

The checking unit is used to determine that the target cache has received the target data and complete the recovery process when a response message sent by the target cache is received and all the waiting registers are not set.

Optionally, the second interaction submodule includes:

A first sending unit, configured to send a monitoring message to the target object, wherein the monitoring message is used for the target object to directly send the target data to the target cache;

Or, a second sending unit is used to send a monitoring message to the target object, receive target data sent by the target object in response to the monitoring message, and then forward the target data to the target cache.

Optionally, when the target request is a write request, the second interaction submodule includes:

A consistency unit is used to send a monitoring message to the target object, and the monitoring message is used for the target object to provide the target data to the target cache when the target data is stored so that the write request can be successfully executed, and to clear the target data stored by the target object to ensure data consistency.

In summary, the embodiment of the present application can parse the request message corresponding to the missing state transaction to obtain the recovery process of the missing state; and operate the waiting register, the preparation register and the information register respectively according to the recovery process, and complete the recovery process through the register values of the waiting register, the preparation register and the information register. The present application can realize the recovery process efficiently, accurately and with low power consumption by setting and resetting the waiting register, the preparation register and the information register respectively. This is because the design of these three types of registers is non-redundant and these three types of registers can be implemented by high-speed physical circuits, the energy consumption during execution is low and the circuit occupies a small area. In addition, the maintenance of the register values of these three types of registers is simple and accurate. Setting and resetting these three types of registers can realize the control of the recovery process, so that the missing state register can realize the processing of cache missing state transactions efficiently, accurately and with low power consumption.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

An embodiment of the present application provides a processing device for cache miss status transactions, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the methods described in the above-mentioned embodiments.

Fig. 4 is a block diagram of a cache miss state transaction processing device 800 according to an exemplary embodiment. For example, the device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

4 , the device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input/output (I/O) interface 812 , a sensor component 814 , and a communication component 816 .

The processing component 802 generally controls the overall operation of the device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations on the device 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 800.

The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and/or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the device 800 is in an operating mode, such as a call mode, a recording mode, and a voice information processing mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

I/O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the device 800. For example, the sensor assembly 814 can detect the open/closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800, and the sensor assembly 814 can also search for changes in the position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration/deceleration of the device 800, and the temperature change of the device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and other devices. The device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

In an exemplary embodiment, the apparatus 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above method.

In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by the processor 820 of the device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

FIG5 is a schematic diagram of the structure of the server in some embodiments of the present application. The server 1900 may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPU) 1922 (for example, one or more processors) and memory 1932, and one or more storage media 1930 (for example, one or more mass storage devices) storing application programs 1942 or data 1944. Among them, the memory 1932 and the storage medium 1930 can be short-term storage or permanent storage. The program stored in the storage medium 1930 may include one or more modules (not shown in FIG5), and each module may include a series of instruction operations on the server. Furthermore, the central processing unit 1922 can be configured to communicate with the storage medium 1930 and execute a series of instruction operations in the storage medium 1930 on the server 1900.

The server 1900 may also include one or more power supplies 1926, one or more wired or wireless network interfaces 1950, one or more input and output interfaces 1958, one or more keyboards 1956, and/or one or more operating systems 1941, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM, etc.

A non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of a device (server or terminal), enables the device to execute the above-mentioned embodiment method.

A non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by the processor of the device (server or terminal), enables the device to perform the description of the method of the above embodiment, so it will not be repeated here. In addition, the description of the beneficial effects of the same method will not be repeated. For technical details not disclosed in the computer program product or computer program embodiment involved in this application, please refer to the description of the method embodiment of this application.

In addition, it should be noted that: the embodiment of the present application also provides a computer program product or a computer program, which may include computer instructions, which may be stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor may execute the computer instructions so that the computer device performs the description of the method of the above embodiment, so it will not be repeated here. In addition, the description of the beneficial effects of the same method will not be repeated. For technical details not disclosed in the computer program product or computer program embodiment involved in this application, please refer to the description of the method embodiment of this application.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

The above is a detailed introduction to a method, device, electronic device and computer-readable storage medium for processing cache miss state transactions provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (11)

1. A method for processing a cache miss status transaction, applied to a miss status register, characterized in that the method comprises: Receive a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request is not successfully executed by the cache pipeline; Parsing the request message, and determining a recovery process for the missing state according to the parsing result; The waiting register, the preparation register and the information register are operated respectively according to the recovery process, and the recovery process is completed through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline; Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process. 2. The method for processing a cache miss transaction according to claim 1, wherein the target request is used to process target data, the target request does not hit in the target cache, and the recovery process comprises: Interacting with the cache pipeline to determine whether there is a target object that may store the target data; the target object is a cache object or a memory object other than the target cache; When determining that the target object exists, interacting with the target object so that the target data is provided to the target cache; The device interacts with the target cache and completes the recovery process after determining that the target cache has received the target data. 3. The method for processing a cache miss state transaction according to claim 1 or 2, wherein the target request is used to process target data, the target request does not hit in the target cache, and the waiting register, the preparation register and the information register are operated respectively according to the recovery process, and the recovery process is completed through the register values of the waiting register, the preparation register and the information register, including: respectively setting the first waiting register, the second waiting register, the third waiting register and the first preparing register, thereby initiating a read request to the cache pipeline, and saving the parsing result to the information register; receiving a read result sent by the cache pipeline, determining a target object that may store the target data according to the read result, and setting a fourth wait register and a second prepare register respectively, thereby sending a monitoring message to the target object, so that the target object provides the target data to the target cache; When the response message sent by the target cache is received, it is determined that the target cache has received the target data, and the recovery process is completed. 4. The method for processing cache miss status transactions according to claim 3 is characterized in that the register value after the first wait register is set is used to represent waiting for feedback from the cache pipeline; the register value after the second wait register is set is used to represent waiting for a response to the monitoring message; the register value after the third wait register is set is used to represent waiting for a response message from the target cache; the register value after the first preparation register is set is used to represent the need to initiate a read request to the cache pipeline; the register value after the fourth wait register is set is used to represent waiting for the target object to complete the target data provision transaction; the register value after the second preparation register is set is used to represent the need to send a monitoring message to the target object. 5. The method for processing cache miss state transactions according to claim 3, characterized in that the method further comprises: When it is determined that the cache pipeline has received the read request, resetting the register value of the first preparation register; When receiving the read result sent by the cache pipeline, resetting the register values of the first wait register and the second wait register; When the monitoring message is successfully sent to the target object, resetting the register value of the second preparation register; In the process of providing the target data to the target cache, resetting the register value of the fourth wait register; When a response message sent by the target cache is received, the register value of the third waiting register is reset. 6. The method for processing a cache miss state transaction according to claim 3, wherein upon receiving a response message sent by the target cache, determining that the target cache has received the target data and completing the recovery process comprises: When the response message sent by the target cache is received and all the waiting registers are not set, it is determined that the target cache has received the target data, and the recovery process is completed. 7. The method for processing a cache miss state transaction according to claim 3, wherein the sending of a monitoring message to the target object comprises: Sending a monitoring message to the target object, wherein the monitoring message is used for the target object to directly send the target data to the target cache; Or, a monitoring message is sent to the target object, and target data sent by the target object in response to the monitoring message is received, and then the target data is forwarded to the target cache. 8. The method for processing a cache miss state transaction according to claim 3, wherein, when the target request is a write request, the sending of a monitoring message to the target object comprises: A monitoring message is sent to the target object, wherein the monitoring message is used for the target object to provide the target data to the target cache when the target data is stored so that the write request is successfully executed, and to clear the target data stored by the target object to ensure data consistency. 9. A device for processing cache miss state transactions, characterized in that the device comprises: An acquisition module, configured to receive a request message for a target request; the request message is a message generated by a missing state transaction generated for the target request; the missing state transaction indicates that the target request has not been successfully executed by the cache pipeline; A parsing module, used for parsing the request message and determining a recovery process of the missing state according to the parsing result; a configuration module, configured to respectively operate the waiting register, the preparation register and the information register according to the recovery process, and complete the recovery process through the register values of the waiting register, the preparation register and the information register, thereby eliminating the cause of the missing state transaction in the cache, so that the target request is successfully executed by the cache pipeline; Among them, the register value of the waiting register is used to indicate whether it is necessary to wait for the unfinished first operation to be completed, and the register value in the preparation register is used to indicate whether it is necessary to execute the second operation immediately; the register value in the information register is used to record the analysis result and the execution information in the recovery process. 10. An electronic device, comprising: a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 8. 11. A computer-readable storage medium, characterized in that when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method as claimed in any one of claims 1 to 8.