CN118689402B - Data merging method and storage device - Google Patents

Abstract

The invention provides a data merging method and a storage device. The method includes configuring a cache entity unit in a memory module, executing a host write operation to store data from a host system, determining whether an available capacity of the cache entity unit is less than a preset capacity, monitoring a data write performance of the host write operation if the available capacity of the cache entity unit is less than the preset capacity, adjusting a threshold value according to the data write performance to characterize a threshold condition for triggering a target data integration, and if the target data integration is triggered, synchronously executing a data integration operation on the memory module during execution of the host write operation, which is used for moving valid data in the memory module to release an idle entity unit. Thus, the operation stability of the memory device can be improved.

Description

Data merging method and storage device

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a data merging method and a storage device.

Background

In order to improve the data processing capability of the storage device, the storage space can be optimized by executing data integration operations such as garbage collection (Garbage Collection, GC) and the like, so that the purposes of improving the performance and/or response speed of the storage device and the like are achieved.

In general, garbage collection can be divided into background (i.e., garbage collection performed while the storage device is in a idle state) and foreground (foreground) garbage collection (i.e., garbage collection performed while the storage device is in a busy state). In contrast to background garbage collection, foreground garbage collection is often performed in synchronization with host write operations, and in practice, its trigger condition is often set to be activated when an emergency event is encountered (e.g., the idle blocks in the storage device are nearly exhausted). At this time, the idle blocks in the storage device are almost used up, and even if the foreground garbage collection is started to forcedly perform garbage collection, the performance of the host write operation is still further reduced.

Therefore, there is a need for a data consolidation method to solve the above problems.

Disclosure of Invention

The present invention provides a data merging method and a storage device, which can improve the above problems.

An embodiment of the invention provides a data merging method, which is used for a storage device, wherein the storage device comprises a memory module, the data merging method comprises the steps of configuring a cache entity unit in the memory module, executing a host write operation to store data from a host system, judging whether the available capacity of the cache entity unit is smaller than a preset capacity, monitoring the data write efficiency of the host write operation if the available capacity is smaller than the preset capacity, adjusting a critical value according to the data write efficiency, wherein the critical value is used for representing a threshold condition for triggering target data merging, and synchronously executing data merging operation on the memory module during the execution of the host write operation if the target data merging is triggered, wherein the data merging operation is used for moving effective data in the memory module to release idle entity units.

The embodiment of the invention further provides a storage device, which comprises a connection interface, a memory module and a memory controller. The connection interface is used for connecting to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to configure a cache entity in the memory module, perform a host write operation to store data from the host system, determine whether an available capacity of the cache entity is less than a preset capacity, monitor a data write performance of the host write operation if the available capacity is less than the preset capacity, adjust a threshold according to the data write performance, wherein the threshold is used to characterize a threshold condition that triggers a target data integration, and synchronize performing a data integration operation on the memory module during execution of the host write operation if the target data integration is triggered, wherein the data integration operation is used to move valid data in the memory module to release an idle entity.

Based on the above, after the available capacity of the cache physical unit in the memory module is smaller than the preset capacity, the data writing efficiency of the host writing operation can be monitored, and the critical value used for representing the threshold condition for triggering the target data integration can be adjusted according to the data writing efficiency. Thus, before triggering an emergency (e.g., the idle physical unit in the memory module is almost exhausted), the execution of the target data is started early and new idle physical units are gradually released without affecting the data writing performance of the host write operation as much as possible. Therefore, the problem that the efficiency of the host write operation is greatly reduced, which is easily encountered after the storage device is used for a period of time, can be solved, and the operation stability of the storage device can be improved.

Drawings

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating adjustment thresholds according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating the host write performance without early triggering of data consolidation according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating the host write performance in the case of early trigger data consolidation according to an embodiment of the present invention;

fig. 7 is a flow chart of a data consolidation method according to an embodiment of the invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 may be connected to the host system 11 and may be used to store data from the host system 11. For example, the host system 11 may be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game machine, a server, or a computer provided in a specific carrier (e.g., a vehicle), or the like, and the type of the host system 11 is not limited thereto. Further, the storage device 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage device.

The memory device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, connection interface 121 may support an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC), universal flash memory (Universal Flash Storage, UFS), peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express), non-volatile memory Express (Non-Volatile Memory Express, NVM Express), serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA), universal serial bus (Universal Serial Bus, USB), or other types of connection interface standards. Accordingly, storage device 12 may communicate (e.g., exchange signals, instructions, and/or data) with host system 11 via connection interface 121.

The memory module 122 is used for storing data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each of the rewritable non-volatile memory modules may include one or more memory cell arrays. Memory cells in a memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single level memory cell (SINGLE LEVEL CELL, SLC) NAND-type flash memory module, a second level memory cell (Multi LEVEL CELL, MLC) NAND-type flash memory module, a third level memory cell (TRIPLE LEVEL CELL, TLC) NAND-type flash memory module, a fourth level memory cell (Quad LEVEL CELL, QLC) NAND-type flash memory module, and/or other memory modules having the same or similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be considered a control core of storage device 12 and may be used to control storage device 12. For example, the memory controller 123 may be used to control or manage the operation of the storage device 12 in whole or in part. For example, the memory controller 123 may include a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In an embodiment, the memory controller 123 may comprise a flash memory controller.

Memory controller 123 may send a sequence of instructions to memory module 122 to access memory module 122. For example, memory controller 123 may send a sequence of write instructions to memory module 122 to instruct memory module 122 to store data in a particular memory location. For example, memory controller 123 can send a sequence of read instructions to memory module 122 to instruct memory module 122 to read data from a particular memory location. For example, memory controller 123 can send a sequence of erase instructions to memory module 122 to instruct memory module 122 to erase data stored in a particular memory cell. In addition, memory controller 123 may send other types of instruction sequences to memory module 122 to instruct memory module 122 to perform other types of operations, as the invention is not limited. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access memory locations within the memory module 122 according to the sequence of instructions.

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the operation of the memory controller 123 in whole or in part. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiment, the explanation of the memory control circuit 23 is equivalent to the explanation of the memory controller 123.

In one embodiment, memory controller 123 may also include buffer memory 24. The buffer memory 24 is used for buffering data. For example, buffer memory 24 may be used to buffer instructions from host system 11, data from host system 11, and/or data from memory module 122. In one embodiment, the memory controller 123 may also include various circuit modules of other types (e.g., power management circuits, etc.), which are not limiting.

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical units 301 (1) to 301 (D). Each physical unit comprises a plurality of memory cells and is used for nonvolatile memory data.

In one embodiment, a physical cell may include one or more physical erase units. One physical erase unit may include a plurality of physical program units. One physical programming unit may include a plurality of physical sectors (sectors). For example, a physical sector may have a data size of 512 Bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of one physical fan and/or the total number of physical fans included in one physical programming unit can be adjusted according to the practical requirements, and the present invention is not limited thereto. In one embodiment, a physical programmer may be considered a physical page. For example, the data capacity of one physical programming unit may be 4 kilobytes (4 KB), and the present invention is not limited thereto.

In one embodiment, one physical programmer is the minimum unit of synchronous write data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation or a data write operation) on a physical programming unit to write data into the physical programming unit, a plurality of memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. The threshold voltage of each memory cell may reflect the bit data stored by the memory cell.

In one embodiment, a plurality of physical program units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physically erased cell, an erase voltage may be applied to a plurality of physically programmed cells in the physically erased cell to change the threshold voltage of at least some of the physically programmed cells. By performing an erase operation on a physically erased cell, data stored in the physically erased cell may be erased.

In one embodiment, the memory control circuit 23 may logically associate the physical units 301 (1) -301 (A) to the data area (also referred to as a first type data area or a cache area) 31 and the physical units 301 (A+1) -301 (B) to the data area (also referred to as a second type data area) 32. The physical units 301 (1) -301 (a) in the data area 31 and the physical units 301 (a+1) -301 (B) in the data area 32 each store data (also referred to as user data) from the host system 11. For example, any one of the physical units in the data areas 31 and 32 may store valid (valid) data and/or invalid (invalid) data.

In one embodiment, the memory control circuit 23 may logically associate the physical units 301 (B+1) -301 (C) and 301 (C+1) -301 (D) to the idle (spare) region 33. For example, none of the physical units 301 (B+1) -301 (C) and 301 (C+1) -301 (D) in the idle region 33 store data (e.g., valid data).

In one embodiment, if a certain physical unit does not store valid data, the physical unit may be associated with the idle area 33. In addition, the physical cells in the spare area 33 may be erased to erase the data in the physical cells. In one embodiment, the physical units in the idle region 33 are also referred to as idle physical units. In one embodiment, the free area 33 is also referred to as a free pool (free pool).

In one embodiment, the memory control circuit 23 may configure the physical units 301 (B+1) -301 (C) as a first type of physical unit (also referred to as a cache physical unit). In one embodiment, the memory control circuit 23 may configure the physical units 301 (C+1) -301 (D) as the second type of physical units.

In one embodiment, the speed at which the memory control circuit 23 accesses the first type of physical units (e.g., the speed at which data is read from and/or written to the first type of physical units) is higher than the speed at which the memory control circuit 23 accesses the second type of physical units (e.g., the speed at which data is read from and/or written to the second type of physical units).

In one embodiment, the memory control circuit 23 may program the first type of physical unit based on a certain programming mode (also referred to as a first programming mode) to store data into the first type of physical unit. In one embodiment, the memory control circuit 23 may program the second type of entity unit based on another programming mode (also referred to as a second programming mode) to store data into the second type of entity unit. The first programming mode is different from the second programming mode.

In an embodiment, the first programming mode may include an SLC mode or a virtual SLC (pSLC) mode. In an embodiment, the second programming mode may include an MLC, TLC mode, or QLC mode. It should be noted that the first programming mode and the second programming mode can be set or adjusted according to the practical requirement, and the invention is not limited thereto.

In one embodiment, one memory cell in the first type of physical unit may store k bits. In one embodiment, one memory cell in the second class of physical units may store p bits, and k is less than p. For example, assuming k is "1", p may be "2", "3", "4" or other integer greater than "1". Or assuming k is "2", p may be "3", "4", or other integer greater than "2". The present invention is not limited to the values of k and p.

In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical units from the idle area 33 and instruct the memory module 122 to store the data in the selected physical units. In particular, if the selected entity belongs to a first type of entity (e.g., one of entity 301 (B+1) -301 (C)), then the entity may be associated with the data field 31 after storing the data into the entity. However, if the selected entity belongs to a second type of entity (e.g., one of entity 301 (C+1) -301 (D)), then the entity may be associated with the data field 32 after storing the data into the entity. In other words, the first type of physical units (i.e., physical units 301 (1) -301 (A) and 301 (B+1) -301 (C)) can be used alternately between the data area 31 and the idle area 33, and the second type of physical units (i.e., physical units 301 (A+1) -301 (B) and 301 (C+1) -301 (D)) can be used alternately between the data area 32 and the idle area 33.

In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302 (1) -302 (E) to map physical units (i.e., physical units 301 (1) -301 (A) and 301 (A+1) -301 (B)) in the data areas 31 and 32. For example, a logical unit may correspond to a logical block address (Logical Block Address, LBA) or other logical management unit. One logical unit may be mapped to one or more physical units in data areas 31 and/or 32.

In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in the logical-to-physical mapping table. In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform data reading, writing or erasing operations according to the information in the logical-to-physical mapping table.

In one embodiment, the memory control circuit 23 may fetch instructions from the host system 11. For example, the instruction includes a write instruction. This write instruction may indicate that particular data is stored. In one embodiment, the memory control circuit 23 may perform a write operation (also referred to as a host write operation) according to this instruction to store data from the host system 11. For example, in a host write operation, the memory control circuit 23 may send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store particular data to particular physical units.

In one embodiment, in a host write operation, the memory control circuit 23 may preferentially instruct the memory module 122 to store data from the host system 11 into a first type of physical unit (e.g., physical units 301 (B+1) -301 (C) in FIG. 3). Thus, the data writing efficiency of the host writing operation can be improved. However, if the first type of physical units are exhausted (e.g., the physical units 301 (B+1) -301 (C) in FIG. 3 are all associated with the data area 31), the memory control circuit 23 may instead store data from the host system 11 into the second type of physical units (e.g., the physical units 301C+1) -301 (D) in FIG. 3). Thus, normal execution of the host write operation can be maintained, although the data write efficiency of the host write operation may be reduced.

In one embodiment, the memory control circuit 23 may determine whether the available capacity of the cache physical unit (i.e., the first type of physical unit) is less than a predetermined capacity. For example, the available capacity of the physical cache unit refers to the total capacity of the physical units 301 (B+1) -301 (C) in the current free area 33. In one embodiment, the available capacity of the physical cache units may also be represented by the total number of physical units 301 (B+1) -301 (C) in the current free area 33. For example, the total number of physical units 301 (B+1) -301 (C) in the current free area 33 may be directly related to the available capacity of the cache physical unit. That is, the more the total number of physical units 301 (B+1) -301 (C) in the current free area 33, the more available capacity of the cache physical unit.

In one embodiment, the memory control circuit 23 may determine whether the physical cache unit is exhausted (i.e., whether the available capacity of the physical cache unit is zero). If the cache physical unit is exhausted (i.e., the available capacity of the cache physical unit is zero), the memory control circuit 23 may determine that the available capacity of the cache physical unit is less than the predetermined capacity. Alternatively, if the cache physical unit is not exhausted (i.e., the available capacity of the cache physical unit is not zero), the memory control circuit 23 may determine that the available capacity of the cache physical unit is not less than the predetermined capacity.

In one embodiment, if the available capacity of the cache physical unit is less than the predetermined capacity (e.g., the cache physical unit has been exhausted), the memory control circuit 23 may begin to monitor the data write performance of the host write operation. For example, the data write performance of the host write operation may reflect the current write speed of the storage device 12 for data from the host system 11. This writing speed can be expressed by how much data is stored to the storage device 12 per unit time.

Therefore, by the method according to the above embodiment, the usage of the cache entity unit is monitored to determine whether the current cache entity unit is used up, and then whether the data writing efficiency of the host writing operation needs to be monitored is determined according to the determination result. Therefore, the problem of system resource waste caused by directly monitoring the data writing efficiency of the host computer when data is written every time can be avoided.

In one embodiment, the memory control circuit 23 may monitor the status of the instruction queue in the buffer memory 24 and evaluate the data writing performance of the host write operation according to the detection result. For example, the instruction queue may be used to cache at least one instruction (e.g., a write instruction) from the host system 11.

In one embodiment, the state of the instruction queue may reflect the depth of the instruction queue. For example, the depth of an instruction queue may be positively correlated to the total number of instructions currently buffered in the instruction queue. In one embodiment, the memory control circuit 23 may evaluate the data write performance of the host write operation based on the depth of the instruction queue. For example, the depth of the instruction queue may be positively correlated to the data write performance of the host write operation. That is, the deeper the instruction queue depth, the more instructions from the host system 11 currently waiting to be executed. The more instructions from the host system 11 waiting to be executed, the higher the data write performance indicated in the host write operation.

It should be noted that the present invention is not limited to the specific embodiment for obtaining the data writing performance of the host writing operation. For example, in one embodiment, the memory control circuit 23 may also evaluate the data writing performance of the host write operation by monitoring the data transmission status of the connection interface 121.

In one embodiment, if the available capacity of the cache physical unit is detected to be less than the predetermined capacity, the memory control circuit 23 may adjust (e.g., increase or decrease) a threshold according to the monitored data write performance of the host write operation. In particular, this threshold may be used to trigger target data consolidation. For example, the target data set includes a foreground (foreground) data set (also referred to as a foreground data set). In one embodiment, this threshold may be used to characterize a threshold condition that triggers the integration of the target data.

In one embodiment, the memory control circuit 23 may not adjust the threshold until the available capacity of the physical cache unit is less than the predetermined capacity. Therefore, the memory control circuit 23 may not monitor the data writing performance of the host write operation before the available capacity of the cache physical unit is smaller than the predetermined capacity, so as to save the system resources.

In one embodiment, the memory control circuit 23 can continuously detect whether the total number of idle physical units (i.e. the physical units in the idle area 33) in the memory module 122 is less than the threshold. If the total number of idle physical units in the memory module 122 is less than the threshold, the memory control circuit 23 may trigger the target data merge. If the total number of idle physical units in the memory module 122 is not less than (e.g., greater than or equal to) the threshold, the memory control circuit 23 may not trigger the target data merge.

In one embodiment, after the target data merge is triggered, the memory control circuitry 23 may synchronize the execution of the data merge operation on the memory module 122 during the execution of the host write operation. This data consolidation operates to move valid data in the memory module 122 to free up (new) idle physical units. For example, this data consolidation operation includes a garbage collection (Garbage Collection, GC) operation.

In one embodiment, the target data set is not equal to the background data set. For example, the target data integration refers to a data integration operation that the memory control circuit 23 synchronously performs on the memory module 122 during execution of a host write operation. In one embodiment, the target data integration is performed synchronously with the host write operation, so that the target data integration may occupy the bandwidth of the host write operation, thereby affecting the data write performance of the host write operation. In one embodiment, the targeting is performed while the storage device 12 is busy.

On the other hand, the background data integration refers to a data integration operation performed by the memory control circuit 23 on the memory module 122 during the period in which the host write operation is not performed. In one embodiment, the background data integration is performed when the memory device 12 is not busy (i.e., in an idle state) as compared to the target data integration. Therefore, the background data does not occupy the bandwidth of the host write operation, nor does it affect the data write performance of the host write operation.

It can be seen that by the method proposed by the above-described embodiment, it is determined whether to perform the data merging operation while performing the host write operation based on the state of the storage device. This can realize that the release of the physical unit is performed while avoiding the influence on the data writing efficiency.

In one embodiment, in the data merging operation (e.g., GC operation), the memory control circuit 23 may select at least one entity unit from the data areas 31 and/or 32 (e.g., entity units 301 (1) to 301 (B)) as a source entity unit, and select at least one entity unit from the idle area 32 (e.g., entity units 301 (b+1) to 301 (D)) as a target entity unit. The memory control circuit 23 may collect valid data from the source entity unit and store the collected valid data in the target entity unit (i.e., move valid data from the source entity unit to the target entity unit). If all valid data in a source physical unit has been moved to a target physical unit, the memory control circuit 23 may associate the source physical unit with the spare area 33.

Thus, the above-mentioned operation of associating at least one entity unit to the idle area 33 is also called releasing (new) idle entity units, and the total number of entity units (i.e. idle entity units) in the idle area 33 can be gradually increased. By synchronizing the execution of data-merge operations (i.e., target data-merge) to the memory module 122 during the execution of a host write operation, new idle physical units may be continually replenished during the consumption of idle physical units by the execution of a host write operation, thereby avoiding idle physical units from being exhausted.

In one embodiment, the memory control circuit 23 may preferentially select the physical units (i.e., cache physical units) in the idle region 33 as the source physical units during the data merge operation. After the valid data in one cache physical unit is completely moved to the target physical unit, the cache physical unit may be re-associated to the free area 33 to become one of the physical units 301 (B+1) -301 (C).

Thus, the physical units (i.e., cache physical units) dedicated to storing the data written by the host write operation in the spare area 33 can be continuously replenished, thereby improving the data write performance of the host write operation.

In one embodiment, by adjusting (e.g., increasing) the threshold, the target data integrity may be triggered in advance during execution of the host write operation. By triggering the target data integration in advance, the physical units (i.e., cache physical units) in the free area 33 dedicated to storing the data written by the host write operation can be replenished in advance (i.e., free physical units belonging to the cache physical units begin to be released in advance) during the execution of the host write operation.

Thus, during the execution of the host write operation, although the cache physical units (i.e., physical units 301 (B+1) -301 (C)) in the free area 33 are continuously consumed, the cache physical units (i.e., physical units 301 (B+1) -301 (C)) in the free area 33 are continuously replenished, thereby slowing down the consumption of the cache physical units (i.e., physical units 301 (B+1) -301 (C)) in the free area 33.

In one embodiment, the memory control circuit 23 can determine whether the monitored data writing performance of the host writing operation is lower than a preset performance. In one embodiment, if the monitored data writing performance of the host writing operation is lower than the preset performance, the memory control circuit 23 may adjust the threshold value from one threshold value (also referred to as a first threshold value) to another threshold value (also referred to as a second threshold value). The second threshold is different from the first threshold. For example, the second threshold may be greater than the first threshold. Alternatively, in one embodiment, if the monitored data writing performance of the host writing operation is not lower than (e.g., higher than or equal to) the preset performance, the memory control circuit 23 may maintain the threshold value at the first threshold value. It should be noted that the setting of the preset performance may be set by performing data statistics analysis according to the writing performance of the host writing operation in practice, or may be set according to the relevant parameters of the storage device, which is not limited herein.

In one embodiment, the memory control circuit 23 may use a value (also referred to as a first performance evaluation value) to represent the data writing performance of the host writing operation. For example, the first performance evaluation value may be positively correlated to the data write performance of the host write operation. That is, if the first performance evaluation value is larger, the data writing performance of the host writing operation is higher.

In one embodiment, the memory control circuit 23 may compare the first performance evaluation value with a predetermined value. For example, the predetermined value may represent the predetermined performance. This preset value may be positively correlated to the preset performance. That is, if the preset value is larger, the preset performance is higher.

In one embodiment, if the comparison result between the first performance evaluation value and the preset value indicates that the first performance evaluation value is smaller than the preset value, the memory control circuit 23 may determine that the data writing performance of the host writing operation is lower than the preset performance. However, if the comparison between the first performance evaluation value and the predetermined value reflects that the first performance evaluation value is not smaller (e.g., greater than or equal to) than the predetermined value, the memory control circuit 23 may determine that the data writing performance of the host write operation is not lower than the predetermined performance.

In one embodiment, the memory control circuit 23 may determine that the currently executing host write operation is a host low-speed write or a host high-speed write according to the comparison result between the monitored data write performance of the host write operation and the preset performance. For example, if the data writing performance of the host writing operation is lower than the preset performance, the memory control circuit 23 may determine that the currently executing host writing operation is a host low-speed writing operation. Alternatively, if the data writing performance of the host writing operation is not lower than the preset performance, the memory control circuit 23 may determine that the currently executing host writing operation is a host high-speed writing operation.

In one embodiment, if it is determined that the currently executing host write operation is a host low speed write, the memory control circuit 23 may adjust (e.g., raise) the threshold value from the first threshold value to a second threshold value. However, in one embodiment, if it is determined that the currently executing host write operation is a host high-speed write operation, the memory control circuit 23 may maintain the threshold at the first threshold or return the threshold from the second threshold to the first threshold.

In one embodiment, if the currently executing host write operation is a host low-speed write operation (i.e., the data write performance of the host write operation is lower than the preset performance), it means that even if the host write operation and the data merge operation are simultaneously executed, the effect on the data write performance of the host write operation perceived by the host system 11 is almost negligible. Thus, in one embodiment, by increasing the threshold (e.g., increasing the threshold to a second threshold) to trigger the target data set in advance when the host system 11 performs the host low-speed write, the idle entity (particularly the idle entity belonging to the cache entity) can be released (i.e., replenished) in advance without affecting the data write performance of the host write operation. Thus, the data writing efficiency of the host writing operation is maintained or even improved.

On the other hand, in one embodiment, if the currently executing host write operation is a host high-speed write operation (i.e., the data write performance of the host write operation is not lower than the preset performance), it means that if the host write operation and the data merge operation are executed synchronously, the data write performance of the host write operation may be significantly degraded (because part of the bandwidth is occupied by the data merge operation) as perceived by the host system 11. Thus, in one embodiment, by reducing or reverting the threshold (e.g., reverting the threshold from the second threshold to the first threshold) to shut down or cancel the early trigger for target data integration when the host system 11 performs host high speed writing, the data writing performance of the host write operation is prevented from being affected.

In one embodiment, the memory control circuit 23 may evaluate the performance of the data merging operation before or after triggering the target data merging. The memory control circuit 23 may adjust the threshold according to the execution performance of the data merging operation.

In one embodiment, the memory control circuit 23 may determine a parameter value (also referred to as an adjustment parameter value) according to the execution performance of the data merging operation. For example, this adjustment parameter value may negatively relate to the performance of the data merge operation. That is, the higher the estimated performance of the data merge operation, the smaller the adjustment parameter value may be. Based on this adjustment parameter value, the memory control circuit 23 can adjust the threshold value from the first threshold value to the second threshold value. For example, the adjustment parameter value may be directly related to the difference between the first threshold and the second threshold. That is, if the adjustment parameter value is larger, the difference between the first threshold and the second threshold may be larger.

Fig. 4 is a schematic diagram illustrating the adjustment threshold according to an embodiment of the present invention. Referring to fig. 4, in an embodiment, assuming that the currently executing host write operation is a host low-speed write operation, the memory control circuit 23 may set the threshold for triggering the target data integration to the threshold THR (1) (i.e., the first threshold).

In one embodiment, if the currently executing host write operation is a host high-speed write operation, the memory control circuit 23 may adjust (e.g., raise) the threshold for triggering the target data integration to the threshold THR (2) (i.e., the second threshold). For example, the difference ΔP between the threshold values THR (1) and THR (2) is positive with respect to the adjustment parameter value. The difference ΔP may be inversely related to the performance of the data merge operation.

In one embodiment, the memory control circuit 23 may add the threshold value THR (1) to the difference Δp to obtain the threshold value THR (2). In one embodiment, the memory control circuit 23 may subtract the difference ΔP from the threshold THR (2) to obtain the threshold THR (1).

In one embodiment, the performance of the data merging operation may reflect that N idle physical units are released per unit time during the data merging operation. For example, the value of N may be positively correlated to the performance of the data merge operation. That is, the larger the value of N, the more idle physical units are released per unit time during the execution of the data merging operation (equivalently, the higher the execution performance of the data merging operation).

In one embodiment, the memory control circuit 23 may obtain the storage state of valid data in the memory module 122. For example, the storage state of the valid data in the memory module 122 may reflect the distribution state of the valid data in one or more physical cells in the memory module 122. The memory control circuit 23 may evaluate the performance of the data merge operation based on the storage status of the valid data in the memory module 122.

In one embodiment, the memory control circuit 23 may use a value (also referred to as a second performance evaluation value) to represent the performance of the data merging operation. For example, the second performance evaluation value may be positively correlated to the performance of the data merge operation. That is, if the second performance evaluation value is larger, it means that the performance of the data merging operation is higher. In one embodiment, the second performance evaluation value may be positively correlated to the value of N.

In one embodiment, the memory control circuit 23 may obtain the second performance evaluation value according to the following algorithms (1.1) and (1.2).

R1=(V1-(V×f%))/V(1.1)

R2=R1/UT(1.2)

In the algorithms (1.1) and (1.2), the parameter V1 represents the total number of used physical units in the memory module 122 (i.e., the physical units in the memory module 122 currently storing valid data), the parameter V represents the total number of all physical units in the memory module 122, the parameter f% represents the ratio of valid data to total data stored in one or more used physical units, the parameter UT represents one unit time, and the parameter R2 represents the second performance evaluation value.

In one embodiment, the memory control circuit 23 may determine the adjustment parameter value (e.g., the parameter ΔP in FIG. 4) according to the following algorithm (2.1).

ΔP=M/R2(2.1)

In algorithm (2.1), the parameter M may be "1" or other value greater than zero. It should be noted that the algorithms (1.1), (1.2) and (2.1) can be adjusted according to the practical requirements, and the invention is not limited thereto.

In one embodiment, the memory control circuit 23 may adjust the parameter M in the algorithm (2.1) according to the monitored host write operation. In one embodiment, if the currently executing host write operation is a host low-speed write operation (i.e., the data write performance of the host write operation is lower than the preset performance), the memory control circuit 23 predicts that the host write operation is maintained in the time range of the host low-speed write operation according to the monitored host write operation. For example, a relatively high probability of a host write operation may remain operating on a host low-speed write during the predicted time frame. The memory control circuit 23 may decide the parameter M in the algorithm (2.1) on the basis of the predicted time frame. For example, parameter M may be positively maintained in a host low-speed write time range with respect to a predicted host write operation. That is, the larger the predicted host write operation remains in the host low-speed write time range, the larger the parameter M may be. Or in an embodiment, the parameter M may represent or reflect the time at which the host write operation is expected to remain low-speed.

In one embodiment, the memory control circuit 23 may predict that the host write operation is maintained in the time range of the host low-speed write by analyzing at least one of the type of data written by the host write operation, the size of data written by the host write operation, the total number of instructions indicating the host write operation, and the acquisition frequency of instructions indicating the host write operation as the characteristic parameter. For example, the memory control circuit 23 may input one or more of the above-described characteristic parameters to an operation model or a lookup table, and obtain the time range or parameter M according to the output of the operation model or the lookup table. The details of the related operations may be designed or adjusted according to the practical requirements, and the invention is not limited.

Therefore, by the method provided by the above embodiment, when the first performance evaluation value is larger, Δp is set smaller, and the idle entity unit is quickly released by integrating and processing the target data in a short time, so as to achieve the effect of quickly improving the performance of the host. When the first performance evaluation value is smaller, Δp is set to be relatively larger, and when the host write operation is in low-speed write operation, the target data can be integrated and the fast release idle entity units can be processed earlier, so that the release of enough idle entity units before the host switches back to the high-speed data write operation is ensured as much as possible.

FIG. 5 is a diagram illustrating the host write performance without early triggering of data consolidation according to an embodiment of the present invention. Referring to fig. 5, assume that the horizontal axis is time and the vertical axis is data write performance (also referred to as host write performance) of a host write operation. Assume that prior to time T (0), storage device 12 is in an idle state. Thus, prior to time point T (0), memory control circuit 23 may instruct storage device 12 to perform background data consolidation.

Assume that after time point T (0), storage device 12 begins performing a host write operation. Curve 51 may reflect the variation of host write performance at different time points. For example, assume at time T (1) that the cache entity in memory module 122 is exhausted. Therefore, after time T (1), the host write performance begins to drop. At time T (2), the total number of idle physical units in the memory module 122 is less than a threshold (i.e., a threshold for triggering the integration of the target data). Therefore, after time T (2), the memory control circuit 23 triggers the target data merge to release the idle physical units belonging to the cache physical units. Further, it is assumed that after the time point T (3), the storage device 12 is again in the idle state. It should be noted that in the embodiment of FIG. 5, the host write performance is greatly reduced between time point (1) (i.e., the point when the cache physical unit is exhausted) and T (2) (i.e., the trigger target data merge). The host write performance does not stabilize until the target data is triggered.

FIG. 6 is a diagram illustrating the host write performance in the case of early trigger data consolidation according to an embodiment of the present invention. Referring to fig. 6, a curve 61 may reflect the variation of the host write performance at different time points. It should be noted that, in the embodiment of fig. 6, the threshold for triggering the target data integration is increased compared to the embodiment of fig. 5. For example, after time T (1) (i.e., the time at which the cache entity is exhausted), the threshold for triggering the target data merge may be increased according to the host write performance (and the performance of the data merge operation). Details of the related operations are described above, and the detailed description thereof is not repeated here.

After the threshold is raised, the target data is triggered earlier in the aggregate at a time point T (2) '(time point T (2)' is between time points T (1) and T (2)). After triggering the target data merge, after the time point T (2)' during the execution of the host write operation, the data merge operation may be synchronously performed to gradually release the idle physical units belonging to the cache physical units.

In particular, in the embodiment of FIG. 6, the target data is integrated and triggered early, as compared to the embodiment of FIG. 5. Therefore, in the embodiment of FIG. 6, the decrease in the write performance of the host after the time point T (1) (i.e. the time point when the cache physical unit is exhausted) is smaller than that in the embodiment of FIG. 5, the decrease in the write performance of the host after the time point T (1) (i.e. the time point when the cache physical unit is exhausted). Thus, the problem of a significant decrease in the performance of a host write operation that is conventionally experienced with the memory device 12 over a period of time is ameliorated.

Fig. 7 is a flow chart of a data consolidation method according to an embodiment of the application. Referring to fig. 7, the data merging method according to the embodiment of the present application specifically includes the following steps:

In step S701, a cache entity unit is configured in a memory module.

In step S702, a host write operation is performed to store data from the host system.

In step S703, it is determined whether the available capacity of the cache entity unit is less than a predetermined capacity. If the available capacity of the cache physical unit is not less than the predetermined capacity, step S702 may be repeated.

If the available capacity of the cache physical unit is smaller than the predetermined capacity, in step S704, the data writing performance of the host writing operation is monitored.

In step S705, a threshold is adjusted according to the data writing performance, wherein the threshold is used to characterize a threshold condition for triggering the integration of the target data.

In step S706, after the target data integration is triggered, the data integration operation is performed on the memory module synchronously during the execution of the host write operation. The data consolidation is used for moving the effective data in the memory module to release the idle entity units.

In one embodiment, the step of adjusting the threshold according to the data writing performance includes determining whether the data writing performance is lower than a preset performance, adjusting the threshold from a first threshold to a second threshold if the data writing performance is lower than the preset performance, wherein the second threshold is greater than the first threshold, and maintaining the threshold at the first threshold if the data writing performance is not lower than the preset performance.

In one embodiment, the step of adjusting the threshold from the first threshold to the second threshold includes evaluating an execution performance of the data merge operation, determining an adjustment parameter value based on the execution performance, and adjusting the threshold from the first threshold to the second threshold based on the adjustment parameter value, wherein the adjustment parameter value is directly related to a difference between the first threshold and the second threshold.

In one embodiment, the step of evaluating the performance of the data merge operation includes evaluating the performance of the data merge operation based on a storage state of the valid data in the memory module.

In one embodiment, the step of monitoring the data write performance of the host write operation includes evaluating the data write performance of the host write operation based on a depth of an instruction queue, wherein the instruction queue is configured to cache at least one instruction from the host system.

In one embodiment, the data merging method further includes determining whether the total number of idle entity units is less than the threshold, and triggering the target data merging if the total number of idle entity units is less than the threshold.

However, the steps in fig. 7 are described in detail above, and will not be described again here. It should be noted that each step in fig. 7 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 7 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the data merging method and the storage device provided by the invention can adjust the threshold value for triggering the target data merging according to the data writing efficiency of the host writing operation after the available capacity of the cache entity unit in the memory module is smaller than the preset capacity. Therefore, on the premise that the data writing efficiency of the host writing operation is not affected as much as possible, the target data integration is started to be executed in advance and new idle entity units are released gradually, so that the problem that the efficiency of the host writing operation is greatly reduced and the operation stability of the storage device is improved, which is easy to be encountered after the storage device is used for a period of time in the prior art, is solved.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (16)

1. A data consolidation method for a storage device, the storage device comprising a memory module, and the data consolidation method comprising:

Configuring a cache entity unit in the memory module;

performing a host write operation to store data from the host system;

judging whether the available capacity of the cache entity unit is smaller than a preset capacity or not;

if the available capacity is smaller than the preset capacity, monitoring the data writing efficiency of the host writing operation;

adjusting a threshold value according to the data writing performance, wherein the threshold value is used for representing a threshold condition for triggering the integration of target data, and

If the target data merge is triggered, a data merge operation is synchronously performed on the memory module during the execution of the host write operation, wherein the data merge operation is used for moving valid data in the memory module to release idle physical units.

2. The data consolidation method according to claim 1, wherein the step of adjusting the threshold according to the data writing performance comprises:

judging whether the data writing efficiency is lower than a preset efficiency or not;

If the data writing efficiency is lower than the preset efficiency, adjusting the critical value from a first critical value to a second critical value, wherein the second critical value is larger than the first critical value, and

And if the data writing efficiency is not lower than the preset efficiency, maintaining the critical value at the first critical value.

3. The data consolidation method of claim 2, wherein the step of adjusting the threshold from the first threshold to the second threshold comprises:

evaluating the execution efficiency of the data merging operation;

determining an adjustment parameter value according to the execution performance, and

And adjusting the critical value from the first critical value to the second critical value according to the adjustment parameter value, wherein the adjustment parameter value is positively related to the difference value between the first critical value and the second critical value.

4. A data consolidation method according to claim 3, wherein the step of evaluating the performance of the data consolidation operation comprises:

and evaluating the execution efficiency of the data merging operation according to the storage state of the effective data in the memory module.

5. The data consolidation method of claim 3, wherein the performance of the data consolidation operation reflects that N of the idle physical units are released per unit time during execution of the data consolidation operation.

6. The data consolidation method of claim 3, wherein the adjustment parameter value negatively relates to the performance of the data consolidation operation.

7. The data consolidation method of claim 1, wherein monitoring the data write performance of the host write operation comprises:

And evaluating the data writing performance of the host writing operation according to the depth of an instruction queue, wherein the instruction queue is used for caching at least one instruction from the host system.

8. The data consolidation method of claim 1, further comprising:

Judging whether the total number of the idle entity units is less than the critical value, and

And if the total number of the idle entity units is less than the critical value, triggering the target data integration.

9. A memory device, comprising:

a connection interface for connecting to a host system;

Memory module, and

A memory controller connected to the connection interface and the memory module,

Wherein the memory controller is to:

Configuring a cache entity unit in the memory module;

Performing a host write operation to store data from the host system;

judging whether the available capacity of the cache entity unit is smaller than a preset capacity or not;

if the available capacity is smaller than the preset capacity, monitoring the data writing efficiency of the host writing operation;

adjusting a threshold value according to the data writing performance, wherein the threshold value is used for representing a threshold condition for triggering the integration of target data, and

If the target data merge is triggered, a data merge operation is synchronously performed on the memory module during the execution of the host write operation, wherein the data merge operation is used for moving valid data in the memory module to release idle physical units.

10. The memory device of claim 9, wherein the memory controller adjusting the threshold according to the data write performance comprises:

judging whether the data writing efficiency is lower than a preset efficiency or not;

If the data writing efficiency is lower than the preset efficiency, adjusting the critical value from a first critical value to a second critical value, wherein the second critical value is larger than the first critical value, and

And if the data writing efficiency is not lower than the preset efficiency, maintaining the critical value at the first critical value.

11. The memory device of claim 10, wherein the operation of the memory controller to adjust the threshold value from the first threshold value to the second threshold value comprises:

evaluating the execution efficiency of the data merging operation;

determining an adjustment parameter value according to the execution performance, and

And adjusting the critical value from the first critical value to the second critical value according to the adjustment parameter value, wherein the adjustment parameter value is positively related to the difference value between the first critical value and the second critical value.

12. The memory device of claim 11, wherein the operation of the memory controller to evaluate the performance of the data merge operation comprises:

and evaluating the execution efficiency of the data merging operation according to the storage state of the effective data in the memory module.

13. The memory device of claim 11, wherein the performance of the data merge operation reflects that N of the idle physical units are released per unit time during execution of the data merge operation.

14. The memory device of claim 11, wherein the adjustment parameter value negatively correlates to the performance of the data merge operation.

15. The storage device of claim 9, wherein the operation of the memory controller to monitor the data write performance of the host write operation comprises:

And evaluating the data writing performance of the host writing operation according to the depth of an instruction queue, wherein the instruction queue is used for caching at least one instruction from the host system.

16. The storage device of claim 9, wherein the memory controller is further to:

Judging whether the total number of the idle entity units is less than the critical value, and

And if the total number of the idle entity units is less than the critical value, triggering the target data integration.