CN118677450B - DTC Correction Method and ADPLL Based on Sequencing - Google Patents

Abstract

The invention discloses a DTC correction method and an ADPLL based on a sequence adjustment. In order to correct nonlinearity in the DTC, the DTC correction method based on the order adjustment at least receives the phase to be delayed through a correction circuit and outputs a DTC code value; the sequence-adjusting mapping module determines a delay unit set of an access delay circuit in the DTC according to the received DTC code value; the DTC controls the delay unit to access the delay circuit according to the received indication about the delay unit set; the delay units in the DTC are divided into M segments, each segment comprises N delay units, each delay unit has a unique sequence number, and the sequence number of the delay unit in each segment is increased; the set of delay cells is the same as the delay cells determined in the following manner: sequentially selecting delay units with the smallest sequence number and not selected from the M segments until the number of the selected delay units is equal to the DTC code value. The invention can realize the nonlinear correction in the DTC only by consuming lower resource consumption.

Description

DTC Correction Method and ADPLL Based on Sequencing

Technical Field

The invention relates to the field of clock chips, and in particular to a DTC correction method based on sequencing and an ADPLL.

Background Art

All-Digital Phase-Locked Loop (ADPLL) is a phase-locked loop system that is completely implemented using digital circuits, including frequency detectors, phase detectors, and digitally controlled oscillators, etc., which are used to synchronize the phase and frequency of the output signal with the reference signal. Traditional phase-locked loops usually contain analog components, while ADPLL eliminates these analog components and adopts the advantages of digital circuits, such as programmability, low power consumption, reduced size, and enhanced integration.

In a fully digital phase-locked loop circuit, a digital to time converter (DTC) is often used to delay the clock signal to obtain the required clock phase.

Figure 1 shows the distribution of the original step values of different delay units in a DTC. In the example, the horizontal axis is the serial number of the delay unit, and the vertical axis is the original step value. The larger the original step value, the longer the delay. The delay unit of the DTC in the figure is divided into 8 segments during design, and each segment has 16 delay units. In each segment, as the serial number of the delay unit increases, the original step value also increases overall, which is determined by the structure and process of the device.

Figure 2 is a comparison of the original step value and the average step value. If the delay unit of the DTC is not calibrated, the average step value is considered to be the corrected step value. As can be seen from Figure 2, there is a large difference between the original step value and the average step value, and the fluctuation is also large. Therefore, the uncalibrated DTC has a large system error.

Since the digital time converter is greatly affected by the process, voltage and temperature, the step value of the digital time converter will be nonlinear. If the nonlinearity is not corrected, it will cause unexpected advance or delay in the delay of the clock signal, resulting in bumps or spikes on the phase noise spectrum, reducing the clock performance.

Summary of the invention

In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

A DTC correction method based on sequencing is applied to ADPLL, wherein at least a phase to be delayed is received through a correction circuit, and a DTC code value is output; a sequencing mapping module determines a set of delay units in a DTC that are connected to a delay circuit according to the received DTC code value; the DTC controls the delay units to connect to the delay circuit according to the received instructions about the delay unit set; wherein the delay units in the DTC are divided into M segments, each segment includes N delay units, each delay unit has a unique serial number, the serial numbers of the delay units in each segment are incremented, and M and N are both positive integers; the delay unit set is the same as the delay unit determined in the following manner: the delay unit with the smallest serial number and which has never been selected is selected from the M segments in turn, until the number of selected delay units is equal to the DTC code value.

Furthermore, the sequencing mapping module exchanges the front part bits and the rear part bits in the unique sequence number to obtain the sequence number after sequencing; according to the size of the sequence number after sequencing, the delay unit whose sequence number after sequencing does not exceed the DTC code value is used as one of the elements in the delay unit set; wherein, the unique sequence number is a binary sequence number.

Furthermore, M is equal to 8, and N is equal to 16; the first part of the bits in the unique sequence number is the first four bits of the unique sequence number, and the last part of the bits in the unique sequence number is the last three bits of the unique sequence number.

Further, the correction circuit is configured as follows: the received phase to be delayed is added to -0.5 and then squared, and the squared result is multiplied by the first parameter to obtain a third result; the received phase to be delayed is multiplied by the second parameter to obtain a fourth result; the third result and the fourth result are added, and then rounded down by a rounding-down module to obtain a DTC code value.

Furthermore, the first parameter is obtained in the following manner: the delayed phase is added to -0.5 and then squared to obtain a result after the square operation, the result after the square operation is multiplied by the phase error signal, and then multiplied by the first gain coefficient to obtain a first result; the first result is added to a previous value of the first parameter to obtain the first parameter; wherein the phase error signal is a signal output by the phase detector in the ADPLL for indicating a phase error.

Furthermore, the second parameter is obtained in the following manner: after multiplying the delayed phase and the phase error signal, multiplying by the second gain coefficient to obtain a second result; after adding the second result and the previous value of the second parameter, the second parameter is obtained.

An ADPLL includes a DTC; in the ADPLL, the DTC is step-corrected according to any of the above-mentioned DTC correction methods based on sequencing.

The technical solution of the present invention has one or more of the following beneficial technical effects:

(1) The present invention can adaptively correct the nonlinearity of the digital time converter in the background with high accuracy without affecting the system operation. It can also track the step size changes of the digital time converter caused by temperature, voltage, etc. in real time to improve the output clock performance.

(2) It only takes up less chip resources, area and power consumption. It is very suitable for the situation where the step value and nonlinear characteristics of the delay unit in each segment are basically the same.

In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a distribution diagram of the original step values of different delay units of a DTC;

Figure 2 is a comparison chart of the original step length value and the average step length value;

3 is a block diagram of a technical solution for adjusting DTC by a correction circuit according to the present invention;

FIG4( a ) is a schematic diagram of a method for obtaining a first parameter;

FIG4( b ) is a schematic diagram of a method for obtaining the second parameter;

FIG5 is a schematic diagram of a correction circuit of the present invention;

FIG6 is a schematic diagram of the original step value after sequencing;

FIG7 is a comparison diagram of the corrected step value and the original step value after sequencing;

Figure 8 is an error comparison diagram;

FIG. 9 is a flow chart of a DTC correction method based on sequencing according to the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

The DTC is implemented based on a resistor-capacitor circuit unit, and includes a plurality of delay units, which are assigned different serial numbers.

For example, if the DTC includes 128 delay units in total, and the decimal numbers of the delay units are: 0, 1, 2, ..., 126, 127. Obviously, these decimal numbers have corresponding binary representation methods.

If the DTC code value is equal to 3, two delay units numbered 0, 1, and 2 are connected to the delay circuit. If the DTC code value is equal to 15, 15 delay units numbered 0 to 14 are connected to the delay circuit.

FIG3 shows a block diagram of the technical solution of adjusting the DTC by a correction circuit of the present invention. The correction circuit receives the first parameter and the second parameter and the phase to be delayed. The correction circuit outputs a DTC code value to the sequence mapping module, wherein the DTC code value indicates how many delay units should be connected to the delay circuit in the DTC.

As an innovation of the present invention, the sequencing mapping module indicates which delay units in the DTC are connected to the delay circuit, rather than simply indicating how many delay units in the DTC are connected to the delay circuit in the DTC.

Still taking the aforementioned 128 delay units as an example, before sequencing, the 128 delay units each have a corresponding decimal sequence number and binary sequence number, that is, the decimal sequence number before sequencing and the binary sequence number before sequencing.

After sequencing, each of the 128 delay units also has a corresponding sequenced decimal number and sequenced binary number.

The sequencing method of the present invention, for example, exchanges the order of the first four bits of the binary sequence number before sequencing and the last three bits of the binary sequence number before sequencing to obtain the binary sequence number after sequencing, and then obtains the decimal sequence number after sequencing based on the conversion relationship between binary and decimal.

For example, if the decimal sequence number before sequencing is "102", which is a unique sequence number of a delay unit, the corresponding binary sequence number before sequencing is "1100 110". After exchanging the order of the first four bits of the binary sequence number before sequencing and the last three bits of the binary sequence number before sequencing, the binary sequence number after sequencing is "110 1100", which corresponds to the decimal sequence number after sequencing is "108".

According to the above-mentioned sequencing method, the first part of the bits and the last part of the bits of the binary number before sequencing are exchanged, and a comparison table of the binary number and the decimal number before and after sequencing can be obtained, as shown in Table 1 for details.

Table 1: Comparison table of binary and decimal serial numbers of delay units in DTC before and after adjustment

The sequence mapping module determines which delay units in the DTC are connected to the delay circuit according to the obtained DTC code value. Although the original step values of different delay units cannot be changed, the present invention determines the use combination or order of different delay units.

For example, if DTC is 3, in the traditional scheme, the first three delay units are selected according to the sequence number of the delay unit to access the delay circuit, specifically, the three delay units whose decimal sequence numbers are "0", "1" and "2" before sequencing.

The sequencing mapping module still selects a total of 3 delay units to connect to the delay circuit, but the serial numbers of these three delay units are no longer the three delay units with decimal numbers "0", "1" and "2" before sequencing, but the three delay units with decimal numbers "0", "1" and "2" after sequencing, that is, the three delay units with decimal numbers "0", "16" and "32" before sequencing.

If 128 delay units are divided into 8 segments, each segment contains 16 delay units, and in the same segment, the delay unit with a larger decimal number before the sequence adjustment has a larger original step value. The aforementioned three delay units in the present invention are also the first delay units in the first three segments of the DTC.

In other words, after receiving the DTC code value, the sequence mapping module selects the delay unit combination that makes the sum of the decimal sequence numbers before the sequence adjustment the smallest from all the segments in turn as the delay unit combination finally connected to the delay circuit. Since the binary and decimal numbers have the same size relationship, the sum of the decimal sequence numbers before the sequence adjustment is the smallest, that is, the sum of the binary sequence numbers before the sequence adjustment is the smallest, or the sum of the sequence numbers before the sequence adjustment is the smallest.

From another perspective, the delay unit combination is: select the delay unit with the smallest sequence number (decimal sequence number before sequencing or binary sequence number before sequencing) and has never been selected from the 8 segments in turn, until the number of selected delay units is equal to the DTC code value.

FIG4 (a) shows a schematic diagram of a method for obtaining the first parameter. The delayed phase is added to -0.5 and then squared to obtain a squared result. The squared result is multiplied by the phase error signal and further multiplied by the first gain coefficient _u1 to obtain a first result. The first result is added to the previous value of the first parameter to obtain the first parameter.

In addition, the Z ^-1 mark in the drawings of the present invention is a symbol commonly used in the art to express a unit delay, and the value after the unit delay is the previous value. The first parameter represents the slope of the DTC step value curve.

FIG4 (b) shows a schematic diagram of the method for obtaining the second parameter. After the delayed phase and the phase error signal are multiplied, they are multiplied by the second gain coefficient u ₂ to obtain a second result. After the second result and the previous value of the second parameter are added, the second parameter is obtained. The second parameter represents the average step value of the DTC.

Furthermore, the phase error signal is a signal output by a phase detector in the ADPLL and used to represent a phase error.

Figure 5 shows a schematic diagram of the correction circuit of the present invention. The input phase to be delayed is added to -0.5 and then squared, and the squared result is multiplied by the first parameter to obtain a third result.

The delayed phase is further multiplied by the second parameter to obtain a fourth result. After the third result and the fourth result are added, the DTC code value is obtained after the rounding module performs rounding down.

Figure 6 is a schematic diagram of the original step value after the sequence adjustment. The horizontal axis is the decimal sequence number of the delay unit after the sequence adjustment, and the vertical axis is the original step value after the sequence adjustment, and the unit is second. According to the arrangement after the sequence adjustment, the original step value is generally in a linear relationship.

FIG7 is a comparison chart of the corrected step value and the original step value after sequencing. The horizontal axis is the decimal sequence number of the delay unit after sequencing, and the vertical axis is the step value. The solid line in the figure is the original step value after sequencing, and the dotted line is the corrected step value, and the unit is second. As can be seen from FIG7, the present invention is closer to the actual step value and has a better correction effect.

FIG8 is an error comparison chart, comparing the error of the conventional scheme using the average step value as the correction result and the error of the correction step value of the present invention. The horizontal axis is the decimal sequence number of the delay unit after adjustment. The vertical axis is the error value, and the unit is second. The solid line is the average step value error value, and the dotted line is the correction step value error value. It is not difficult to conclude that compared with the conventional scheme, the error value of the present invention is more concentrated near 0, and the accuracy of the correction result is better.

FIG9 shows a DTC correction method based on sequencing of the present invention, which is applied to ADPLL, wherein at least a phase to be delayed is received through a correction circuit, and a DTC code value is output; a sequencing mapping module determines a set of delay units connected to a delay circuit in the DTC according to the received DTC code value; and the DTC controls the delay units to connect to the delay circuit according to the received indication of the delay unit set.

In addition, the delay units in the DTC are divided into M segments, each segment includes N delay units, each delay unit has a unique serial number, and the serial numbers of the delay units in each segment are incremented; the delay unit set is the same as the delay unit determined in the following manner: sequentially select the delay unit with the smallest serial number and never selected from the M segments until the number of selected delay units is equal to the DTC code value. Wherein, M and N are both positive integers.

Furthermore, the sequencing mapping module exchanges the front part bits and the rear part bits in the unique sequence number to obtain the sequence number after sequencing; according to the size of the sequence number after sequencing, the delay unit whose sequence number after sequencing does not exceed the DTC code value is used as one of the elements in the delay unit set; wherein, the unique sequence number is a binary sequence number.

In addition, the present invention also discloses an ADPLL, wherein the ADPLL includes a DTC; in the ADPLL, the DTC is step-corrected according to the aforementioned DTC correction method based on sequencing.

In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (6)

1. A DTC correction method based on sequencing, applied to ADPLL, characterized in that: receiving at least the phase to be delayed through the correction circuit and outputting a DTC code value; The sequence mapping module determines the set of delay units connected to the delay circuit in the DTC according to the received DTC code value; The DTC controls the delay unit to access the delay circuit according to the received indication about the delay unit set; wherein the delay unit in the DTC is divided into M segments, each segment includes N delay units, each delay unit has a unique serial number, the serial number of the delay unit in each segment increases, and M and N are both positive integers; The delay unit set is the same as the delay unit determined by: sequentially selecting the delay unit with the smallest sequence number and never selected from the M segments until the number of selected delay units is equal to the DTC code value; The reorder mapping module exchanges the first part of bits and the second part of bits in the unique sequence number to obtain a reordered sequence number; According to the size of the adjusted sequence number, the delay unit whose sequence number does not exceed the DTC code value is used as one of the elements in the delay unit set; wherein the unique sequence number is a binary sequence number. 2. The DTC correction method based on sequencing according to claim 1, characterized in that: The M is equal to 8, and the N is equal to 16; The first part of the bits in the unique sequence number is the first four bits of the unique sequence number, and the second part of the bits in the unique sequence number is the last three bits of the unique sequence number. 3. The DTC correction method based on sequencing according to claim 2, characterized in that: The correction circuit is configured as follows: The received phase to be delayed is added to -0.5 and then squared, and the squared result is multiplied by the first parameter to obtain a third result; multiplying the received phase to be delayed by the second parameter to obtain a fourth result; After the third result and the fourth result are added, the DTC code value is obtained after the rounding down module performs rounding down. 4. The DTC correction method based on sequencing according to claim 3 is characterized in that: The first parameter is obtained in the following manner: After the delayed phase is added to -0.5, a square operation is performed to obtain a result after the square operation, the result after the square operation is multiplied by the phase error signal, and then multiplied by the first gain coefficient to obtain a first result; The first result is added to the previous value of the first parameter to obtain the first parameter; wherein, The phase error signal is a signal output by the phase detector in the ADPLL and is used to indicate the phase error. 5. The DTC correction method based on sequencing according to claim 4, characterized in that: The second parameter is obtained by: After the delayed phase and the phase error signal are multiplied, the second result is obtained by multiplying the second result by a second gain coefficient; The second result is added to the previous value of the second parameter to obtain the second parameter. 6. An ADPLL, characterized in that: The ADPLL includes a DTC; In the ADPLL, the DTC is step-corrected according to the DTC correction method based on sequencing according to any one of claims 1 to 5.