CN118677386A

CN118677386A - Power amplifier chip, module, circuit, radio frequency front end module and communication equipment

Info

Publication number: CN118677386A
Application number: CN202310296435.4A
Authority: CN
Inventors: 李鹏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-03-15
Filing date: 2023-03-15
Publication date: 2024-09-20
Also published as: WO2024188077A1

Abstract

The embodiment of the application provides a power amplifier chip, a power amplifier module, a power amplifier circuit, a radio frequency front-end module and communication equipment, relates to the technical field of electronics, and is used for reducing the sensitivity of the power amplifier circuit to load impedance change. The power amplifier circuit comprises a radio frequency input end, a radio frequency output end, a first power divider, a first Doherty circuit, a second Doherty circuit, an impedance transformer, a first combining point, a second combining point and a third combining point. The first power divider comprises a first power dividing input end, a first power dividing output end and a second power dividing output end; the first power divider input is coupled to the radio frequency input. The first Doherty circuit is coupled between the first power division output end and the first combining point. The second Doherty circuit is coupled between the second power division output terminal and the second combining point. The impedance transformer is coupled between the first combining point and the third combining point, the second combining point is coupled with the third combining point, and the third combining point is coupled with the radio frequency output end. The method is applied to the radio frequency front-end module.

Description

Power amplifier chip, module, circuit, radio frequency front end module and communication equipment

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a power amplifier chip, a power amplifier module, a power amplifier circuit, a radio frequency front end module, and a communication device.

Background

A Power Amplifier (PA) is an important component of a mobile communication system, and is used as a final amplifying unit of a transmitting channel, and functions to amplify a radio frequency signal with low power and then send the amplified radio frequency signal to an antenna for transmission. With the advent of the fifth generation mobile communication technology (5th generation mobile communication technology,5G), in recent years, the requirements of terminal equipment on the efficiency of PA are higher and higher, and Doherty (Doherty) technology is a circuit architecture for improving the efficiency of PA under the back-off power, but the performance of PA adopting Doherty technology is greatly affected by the load impedance change, so that the application of Doherty technology in terminal equipment is limited.

Disclosure of Invention

The embodiment of the application provides a power amplifier chip, a power amplifier module, a power amplifier circuit, a radio frequency front-end module and communication equipment, which are used for reducing the sensitivity of the power amplifier circuit to load impedance change.

In order to achieve the above purpose, the application adopts the following technical scheme:

In a first aspect of an embodiment of the present application, there is provided a power amplifier circuit including: the device comprises a radio frequency input end, a radio frequency output end, a first power divider, a first Doherty circuit, a second Doherty circuit, an impedance transformer, a first combining point, a second combining point and a third combining point; the first power divider comprises a first power dividing input end, a first power dividing output end and a second power dividing output end; the first power division input end is coupled with the radio frequency input end; the first Doherty circuit is coupled between the first power division output end and the first combining point; the second Doherty circuit is coupled between the second power division output end and the second combining point; the impedance transformer is coupled between the first combining point and the third combining point, the second combining point is coupled with the third combining point, and the third combining point is coupled with the radio frequency output end.

According to the power amplifier circuit provided by the embodiment of the application, as the impedance transformer is arranged on the branch where the first Doherty circuit is located, the branch where the first Doherty circuit is located and the branch where the second Doherty circuit is located can be used as two complementary branches due to the impedance transformation function of the impedance transformer. Under the condition of load impedance mismatch, the first Doherty circuit is seriously deteriorated on the left side of a Smith chart, and the second Doherty circuit is seriously deteriorated on the right side of the Smith chart, and the two are just complementary structures. The branch circuit where the first Doherty circuit and the branch circuit where the second Doherty circuit are connected in parallel perform power synthesis at a third combining point, and the loss of the performance of the other party can be compensated based on the complementation of the first Doherty circuit and the second Doherty circuit, so that the performance degradation of the power amplifier caused by load impedance mismatch is reduced. In addition, the power amplifier circuit adopts two complementary first Doherty circuits and second Doherty circuits to realize load desensitization, so that complicated circuit modules with large area or high insertion loss are not required to be introduced, and the redundancy degree of the circuit is reduced. Therefore, the scheme has the advantages of simple circuit structure, easy realization, small matching circuit area, small insertion loss and high link efficiency, and improves the mismatch resistance of the circuit at lower cost. Furthermore, the power amplifier circuit comprises a first Doherty circuit and a second Doherty circuit, so that the efficiency of the power amplifier circuit can be improved, and the working bandwidth of the power amplifier circuit can be widened.

In one possible implementation, the first Doherty circuit includes a second power divider, a first amplifier, a second amplifier, a first impedance matching network, and a second impedance matching network; the second power divider comprises a second power dividing input end, a third power dividing output end and a fourth power dividing output end; the second power division input end is coupled with the first power division output end, the third power division output end is coupled with the first amplifier, and the fourth power division output end is coupled with the second amplifier; the first impedance matching network is coupled between the output end of the first amplifier and the first combining point; the second impedance matching network is coupled between the output end of the second amplifier and the first combining point. This is a Doherty circuit of simple structure.

In one possible implementation, the second Doherty circuit includes a third power divider, a third amplifier, a fourth amplifier, a third impedance matching network, and a fourth impedance matching network; the third power divider comprises a third power dividing input end, a fifth power dividing output end and a sixth power dividing output end; the third power division input end is coupled with the second power division output end, the fifth power division output end is coupled with the third amplifier, and the sixth power division output end is coupled with the fourth amplifier; the third impedance matching network is coupled between the output end of the third amplifier and the second combining point; the fourth impedance matching network is coupled between the output end of the fourth amplifier and the second combining point. This is a Doherty circuit of simple structure.

In one possible implementation, the first power division output and the second power division output have a phase difference. This is an implementation of the first power divider with a simple structure.

In one possible implementation, the third power division output and the fourth power division output have a phase difference. This is an implementation of the second power divider which is of simple construction.

In one possible implementation, the fifth power division output and the sixth power division output have a phase difference. This is an implementation of the third power divider with a simple structure.

In one possible implementation, the power amplifier circuit further includes a fifth impedance matching network coupled between the third combining point and the rf output terminal. The fifth impedance matching network is used to match the load impedance to a desired impedance point to improve the efficiency of the power amplifier circuit.

In one possible implementation, the first impedance matching network comprises a first inductance and the second impedance matching network comprises a first capacitance. In this way, the power amplifier circuit has a simple structure and a small occupied area.

In one possible implementation, the value of the first inductance is 0.1NH-2NH. Thus, the first impedance matching network can have better performance.

In one possible implementation, the first capacitor has a value of 0.2PF-5PF. Thus, the second impedance matching network can have better performance.

In one possible implementation, the third impedance matching network includes a second inductance and the fourth impedance matching network includes a second capacitance. In this way, the power amplifier circuit has a simple structure and a small occupied area.

In one possible implementation, the value of the second inductance is 0.1NH-2NH. Thus, the third impedance matching network can have better performance.

In one possible implementation, the second capacitor has a value of 0.2PF-5PF. Thus, the fourth impedance matching network can have better performance.

In one possible implementation, the phases of the second combining point and the third combining point are the same. In one possible implementation, the second combining point and the third combining point are coupled by a trace, or the second combining point and the third combining point coincide. Therefore, an impedance converter is not required to be arranged between the second combining point and the third combining point, and the power amplifier circuit is simple in structure.

In one possible implementation, the phase difference between the third combining point and the first combining point is 60 ° to 120 ° or-60 ° to-120 °. The phase difference between the third combining point and the first combining point affects the impedance transformation capability of the impedance transformer, thereby affecting the complementary effect of the first and second Doherty circuits to affect the output performance of the power amplifier circuit. The value range of the phase difference between the third combining point and the first combining point is limited to 60-120 degrees or-60-120 degrees, so that the first Doherty circuit and the second Doherty circuit have better complementary effects, and the performance of the power amplifier circuit is ensured.

In one possible implementation, the impedance transformer includes a third inductance, a fourth inductance, and a third capacitance; the third inductor and the fourth inductor are connected in series between the first combining point and the third combining point; one end of the third capacitor is coupled with the reference ground voltage end, and the other end of the third capacitor is coupled between the third inductor and the fourth inductor. This is a 1/4 wavelength converter of simple construction.

In one possible implementation, the first power divider further includes a seventh power divider output coupled to the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the second power divider further includes an eighth power divider output coupled to the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the third power divider further includes a ninth power divider output coupled to the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the power amplifier circuit further includes a first resistor coupled between the seventh power division output terminal and the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the power amplifier circuit further includes a second resistor coupled between the eighth power division output terminal and the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the power amplifier circuit further includes a third resistor coupled between the ninth power divider output terminal and the reference ground voltage terminal. This is a structurally simple implementation.

In one possible implementation, the power amplifier circuit further includes a first cascaded power amplifier coupled in series with the first power divider. The power amplifier circuit comprises a multi-stage cascade power amplifier, and can increase the amplification factor of the power amplifier.

In one possible implementation, the first cascaded power amplifier includes a first sub-power amplifier coupled between the first power division output and the first Doherty circuit and a second sub-power amplifier coupled between the second power division output and the second Doherty circuit. Because the first power divider has insertion loss, the required power is high. Therefore, the first cascade power amplifier is arranged at the output end of the first power divider, so that the power requirement of the first cascade power amplifier can be reduced, and the efficiency of the power amplifier circuit is improved.

In one possible implementation, the power amplifier circuit further includes a second cascode power amplifier coupled between the radio frequency input and the first power division input. The power amplifier circuit comprises a multi-stage cascade power amplifier, and can increase the amplification factor of the power amplifier.

In a second aspect of the embodiment of the present application, there is provided a power amplifier chip, including: the radio frequency input end, the first output end, the second output end, the third output end and the fourth output end. The first power divider comprises a first power dividing input end, a first power dividing output end and a second power dividing output end. The second power divider comprises a second power dividing input end, a third power dividing output end and a fourth power dividing output end. The third power divider comprises a third power dividing input end, a fifth power dividing output end and a sixth power dividing output end. The first power division input end is coupled with the radio frequency input end, the first power division output end is coupled with the second power division input end, and the second power division output end is coupled with the third power division input end. The first amplifier is coupled between the third power division output end and the first output end, the second amplifier is coupled between the fourth power division output end and the second output end, the third amplifier is coupled between the fifth power division output end and the third output end, and the fourth amplifier is coupled between the sixth power division output end and the fourth output end.

In one possible implementation, the power amplifier chip further includes a first cascaded power amplifier coupled in series with the first power divider.

In one possible implementation, the first cascaded power amplifier includes a first sub-power amplifier and a second sub-power amplifier, the first sub-power amplifier is coupled between the first power division output terminal and the second power division input terminal, and the second sub-power amplifier is coupled between the second power division output terminal and the third power division input terminal.

In one possible implementation, the power amplifier chip further includes a second cascode power amplifier coupled between the radio frequency input and the first power division input.

In one possible implementation, the phase difference between the first power division output end and the second power division output end is 60 ° to 120 ° or-60 ° to-120 °. The phase difference between the third combining point and the first combining point is the coordination of complementary effects, and the phase difference between the first power division output end and the second power division output end is the compensation of the phase difference between the third combining point and the first combining point, so that the branch where the first Doherty circuit is located and the branch where the second Doherty circuit is located have better combining effect.

In one possible implementation, the first power divider further includes a seventh power divider output coupled to the reference ground voltage terminal.

In one possible implementation, the second power divider further includes an eighth power divider output coupled to the reference ground voltage terminal.

In one possible implementation, the third power divider further includes a ninth power divider output coupled to the reference ground voltage terminal.

In one possible implementation, the power amplifier chip further includes a first resistor coupled between the seventh power division output terminal and the reference ground voltage terminal.

In one possible implementation, the power amplifier chip further includes a second resistor coupled between the eighth power division output terminal and the reference ground voltage terminal.

In one possible implementation, the power amplifier chip further includes a third resistor coupled between the ninth power divider output terminal and the reference ground voltage terminal.

A third aspect of an embodiment of the present application provides a power amplifier module, including a power amplifier chip and a substrate, the power amplifier chip being disposed on the substrate, the power amplifier chip including the power amplifier chip of any one of the first aspects.

In one possible implementation manner, the power amplifier module further includes a first impedance matching network, a second impedance matching network, a third impedance matching network, a fourth impedance matching network, an impedance transformer, a first combining point, a second combining point, a third combining point, and a radio frequency output end; the first impedance matching network is coupled between the first output end and the first combining point; the second impedance matching network is coupled between the second output end and the first combining point; the third impedance matching network is coupled between the third output end and the second combining point; the fourth impedance matching network is coupled between the fourth output end and the second combining point; the impedance transformer is coupled between the first combining point and the third combining point, the second combining point is coupled with the third combining point, and the third combining point is coupled with the radio frequency output end.

In one possible implementation, the power amplifier module further includes a fifth impedance matching network coupled between the third combining point and the rf output terminal.

In one possible implementation, the first impedance matching network comprises a first inductance and the second impedance matching network comprises a first capacitance.

In one possible implementation, the value of the first inductor is 0.1NH-2NH; and/or the value of the first capacitor is 0.2PF-5PF. Thus, the first impedance matching network and the second impedance matching network can have better performance.

In one possible implementation, the third impedance matching network includes a second inductance and the fourth impedance matching network includes a second capacitance.

In one possible implementation, the value of the second inductor is 0.1NH-2NH; and/or the value of the second capacitor is 0.2PF-5PF. Thus, the third impedance matching network and the fourth impedance matching network can have better performance.

In one possible implementation, the phase difference between the third combining point and the first combining point is 60 ° to 120 ° or-60 ° to-120 °.

In one possible implementation, the impedance transformer includes a third inductance, a fourth inductance, and a third capacitance; the third inductor and the fourth inductor are connected in series between the first combining point and the third combining point; one end of the third capacitor is coupled with the reference ground voltage end, and the other end of the third capacitor is coupled between the third inductor and the fourth inductor.

In one possible implementation, the substrate includes a first region and a second region, the power amplifier chip is located in the first region, and at least one of the first impedance matching network, the second impedance matching network, the third impedance matching network, the fourth impedance matching network, and the impedance transformer is located in the second region. This is a technically simple layout.

In a fourth aspect of the embodiment of the present application, there is provided a radio frequency front end module, including: a filter, and a power amplifier chip as in any of the second aspects, or a power amplifier module as in any of the third aspects, or a power amplifier circuit as in any of the first aspects, coupled to the filter.

A fifth aspect of an embodiment of the present application provides a communication device, including a radio frequency front end module as in the fourth aspect, and an antenna, where the antenna is coupled to the radio frequency front end module.

Drawings

Fig. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an RF front-end module according to an embodiment of the present disclosure;

Fig. 3 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present application;

fig. 5 is a schematic topology diagram of a power amplifier circuit according to an embodiment of the present application;

fig. 6A to fig. 6D are schematic topology diagrams of a first Doherty circuit according to an embodiment of the present application;

Fig. 7A and fig. 7B are schematic diagrams of a topology of another power amplifier circuit according to an embodiment of the present application;

Fig. 8 is a schematic diagram of a topology of a power amplifier circuit according to another embodiment of the present application;

fig. 9A-9D are schematic diagrams illustrating the rf performance of a power amplifier circuit according to an embodiment of the present application;

fig. 10 is a layout diagram of a power amplifier module according to an embodiment of the application.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "second," "first," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "second," "first," etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Furthermore, in embodiments of the present application, the terms "upper," "lower," "left," "right," and the like may be defined by, but are not limited to, orientations relative to the component illustrated in the figures, it being understood that the directional terms may be used for relative description and clarity, and may be modified accordingly in response to changes in the orientation of the component illustrated in the figures.

In embodiments of the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either a fixed connection, a removable connection, or an integral unit; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "coupled" may be a direct electrical connection, or an indirect electrical connection via an intermediary. The term "contact" may be direct contact or indirect contact through an intermediary.

In the embodiment of the present application, "and/or" describes the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The technical scheme of the application can be applied to various communication equipment comprising a power amplifier. The communication device may be deployed on land, including indoors or outdoors, hand held or vehicle mounted. Can also be deployed on the water surface (such as a ship, etc.). But may also be deployed in the air (e.g., on aircraft, balloon, satellite, etc.). The channel device may be a terminal or a base station, for example. For example, the terminal includes, but is not limited to: a mobile phone, a tablet, a notebook, a palm, a mobile internet device (mobile INTERNET DEVICE, MID), a wearable device (e.g., a smart watch, a smart bracelet, a pedometer, etc.), a vehicle-mounted device (e.g., an automobile, a bicycle, an electric car, an airplane, a ship, a train, a high-speed rail, etc.), a Virtual Reality (VR) device, an augmented reality (augmented reality, AR) device, a wireless terminal in an industrial control (industrial control), a smart home device (e.g., a refrigerator, a television, an air conditioner, an electric meter, etc.), a smart robot, a workshop device, a wireless terminal in an unmanned aerial vehicle (self-driving), a wireless terminal in a teleoperation (remote medical surgery), a wireless terminal in a smart grid (SMART GRID), a wireless terminal in a transportation security (transportation safety), a wireless terminal in a smart city (SMART CITY), or a wireless terminal in a smart home (smart home), a flight device (e.g., a smart robot, a balloon, a drone, an airplane), a radio frequency front end, etc.

Fig. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application, where the communication device is illustrated by using a mobile phone as an example. The communication device includes: a Radio Frequency (RF) front end module 101, a memory 102, a processor 103, a sensor component 104, a multimedia component 105, a power supply component 106, and an input/output interface 107.

The following describes the components of the mobile phone in detail with reference to fig. 1:

The RF front-end module 101 may be used for receiving and transmitting signals during a message or a call, and in particular, after receiving downlink information of a communication device, the RF front-end module is processed by the processor 103, and uplink data is transmitted to the communication device.

The memory 102 may be used to store data, software programs, and modules, and the handset may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state memory device.

The processor 103 is a control center of the mobile phone, connects various parts of the entire device using various interfaces and lines, and performs various functions and processes data of the mobile phone by running or executing software programs and/or modules stored in the memory 102 and calling data stored in the memory 102, thereby performing overall monitoring of the mobile phone.

The sensor assembly 104 includes one or more sensors for providing status assessment of various aspects of the handset. The sensor assembly 104 may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor, and acceleration/deceleration, azimuth, on/off status of the cell phone, relative positioning of the assembly, or temperature change of the cell phone may be detected by the sensor assembly 104. In addition, the sensor assembly 104 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications.

The multimedia component 105 provides a screen of output interface between the handset and the user, which may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. In addition, the multimedia assembly 105 may include at least one camera, for example, the multimedia assembly 105 may include a front-facing camera and/or a rear-facing camera.

The power supply component 106 is configured to provide power to various components of the handset, and the power supply component 106 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the handset.

The input/output interface 107 provides an interface between the processor 103 and a peripheral interface module, such as a keyboard, mouse, etc.

Although not shown, the mobile phone may further include an audio component and a communication module, such as the audio component includes a microphone, a speaker, etc., and the communication module may include one or more of a wireless fidelity (WIRELESS FIDELITY, wiFi) module, a bluetooth module, a Near Field Communication (NFC) module, a global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS) module, or a frequency modulation (frequency modulation, FM) module, which are not described herein. Those skilled in the art will appreciate that the handset configuration shown in fig. 1 is not limiting of the handset and may include more or fewer components than shown, or may combine certain components, or may be arranged in a different arrangement of components.

Fig. 2 is a schematic structural diagram of an RF front-end module 101 according to an embodiment of the present application.

Typically, the RF front-end module 101 includes, but is not limited to, a radio frequency switch, a duplexer, a filter, a Power Amplifier (PA), a low noise amplifier (low noise amplifier, LNA), and the like. Illustratively, as shown in fig. 2, the RF front-end module 101 may include: radio frequency switches, diplexers, filters, PA and LNA.

The RF front-end module 101 may include a transmit path including a PA and a transmit path filter, a radio frequency output of the PA coupled to an input of the transmit path filter, and a receive path including an LNA and a receive path filter, an output of the receive path filter coupled to a radio frequency input of the LNA.

The duplexer is responsible for duplex switching of the frequency division duplex system and radio frequency signal filtering of the receiving channel/transmitting channel, and the radio frequency switch is responsible for switching between the receiving channel and the transmitting channel.

The baseband signal is transmitted to a transmitting channel through a transceiver, and the transmitting channel amplifies the received radio frequency signal and outputs the amplified radio frequency signal to an antenna and transmits the amplified radio frequency signal through the antenna. The PA is responsible for amplifying the radio frequency signal of the transmit channel, and the transmit channel filter is responsible for filtering the radio frequency signal of the transmit channel.

It should be noted that, in the case where the electronic device includes multiple antennas, one antenna may correspond to one PA, one antenna may correspond to multiple PAs, or multiple antennas may share one PA, which is suitable for application scenarios in the related art in the embodiments of the present application.

The receiving channel receives the radio frequency signal from the antenna, and the radio frequency signal is amplified by the receiving channel, output and transmitted to the baseband by the transceiver. The LNA is responsible for amplifying the radio frequency signal of the receiving channel, and the receiving channel filter is responsible for filtering the radio frequency signal of the receiving channel. In addition, the antenna frequency suitable for the embodiment of the application can comprise frequency bands with relatively high bandwidth requirements such as sub6G frequency bands. Of course, the method can also be applied to other frequency bands such as sub3G frequency bands, WIFI frequency bands (e.g., 2.4G frequency bands, 5G frequency bands, 6G frequency bands), and the like.

With the advent of the fifth generation mobile communication technology (5th generation mobile communication technology,5G), in recent years, the requirements of terminal equipment on the efficiency of PA are higher and higher, and Doherty (Doherty) technology is a circuit architecture for improving the efficiency of PA under the back-off power, but the performance of PA adopting Doherty technology is greatly affected by the load impedance change, so that the application of Doherty technology in terminal equipment is limited.

Taking the RF front-end module 101 shown in fig. 2 as an example, a transmit channel filter in a transmit channel is used as a load of the PA, and the change of the load has a direct effect on the performance of the PA adopting the Doherty technique.

In the base station scenario, a PA (also referred to as a Doherty power amplifier circuit in industry) of the Doherty technology generally works in cooperation with an isolator or a circulator, so as to avoid the influence of load impedance variation. Aiming at the problem of the load sensitivity of the Doherty power amplifier circuit, the method mainly comprises the following steps of combining two Doherty PA bridges, matching load impedance adjustment by load impedance closed-loop detection, and matching the mode of switching the Doherty PA series-parallel mode by load impedance closed-loop detection.

The solution described above, although able to reduce to some extent the sensitivity of the Doherty power amplifier circuit to load impedance variations, still has the following drawbacks: the use of the isolator and the bridge can increase the area of the matching circuit and the output loss, the closed loop detection needs to be added with a detection and adjustment circuit, and the scheme is complex and is not suitable for the use scene of the terminal.

Fig. 3 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present application.

As illustrated in fig. 3, the power amplifier circuit includes a radio frequency input terminal RFI, a radio frequency output terminal RFO, a power divider PS, a main power amplifier M, a peak power amplifier P, a first 90 ° phase delay line, a second 90 ° phase delay line, a third 90 ° phase delay line, an impedance detection module, and an impedance tuning module.

The power divider PS, the main power amplifier M, the peak power amplifier P, the first 90-degree phase delay line, the second 90-degree phase delay line and the third 90-degree phase delay line form a Doherty circuit, signals input by the RFI are received and amplified, the impedance detection module is used for detecting impedance changes of a load coupled with the RFO, and the impedance tuning module is used for adjusting the load of the Doherty circuit according to the detection result of the impedance detection module so as to reduce the sensitivity of the Doherty to load impedance.

Although the sensitivity of the Doherty circuit to the load impedance can be reduced by the structure shown in fig. 3, the occupied area of the impedance detection module and the impedance tuning module is relatively large, and the circuit complexity is improved. And additional insertion loss is introduced, which reduces the performance of the power amplifier. Especially in terminal devices.

Based on the above, the application provides the power amplifier which is insensitive to load impedance and contains the Doherty circuit, and the power amplifier has the advantages of simple structure, few additionally introduced devices, low insertion loss and easy realization.

Fig. 4 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present application.

As shown in fig. 4, the power amplifier circuit includes: the power divider comprises a radio frequency input end RFI, a radio frequency output end RFO, a first power divider (power divider) PS1, a first Doherty circuit DT1, a second Doherty circuit DT2, an impedance transformer (a first impedance transformer U), a first combining point Q1, a second combining point Q2 and a third combining point Q3.

Before describing the power amplifier circuit provided by the embodiment of the application, the concepts of several terms are briefly described.

The power amplifier, abbreviated as power amplifier, is the main amplifier of the RF front-end module 101, which converts low power signals from communication and radar equipment into high power transmission signals that are sent to the antenna, the goal of the power amplifier is to increase the signal gain to high power levels without degrading the signal quality.

The power divider, called the power divider for short, is a device for dividing one path of input signal energy into two paths or multiple paths of output equal or unequal energy, and can also reversely combine multiple paths of signal energy into one path of output, and at the moment, the power divider can also be called a combiner.

The Doherty circuit requires two amplifiers for efficient operation and all optimization of splitting, matching combining and phase to achieve the desired results and to improve efficiency.

Regarding the structure of the power amplifier circuit, in some embodiments, the first power divider PS1 may also be referred to as a first coupler or a first bridge, and the first power divider PS1 includes a first power divider input terminal a1, a first power divider output terminal b1, and a second power divider output terminal b2.

In some embodiments, the first power divider PS1 further comprises a seventh power divider output b7.

For example, the phases of the first power division input end a1 and the first power division output end b1 are the same, the first power division output end b1 and the second power division output end b2 have a phase difference, and the phases of the second power division output end b2 and the seventh power division output end b7 are the same.

It should be noted that the phases mentioned in the embodiments of the present application are not limited to be the same, but are approximately the same within the process error range (for example, the phase difference of ±5°) and belong to the same phase in the embodiments of the present application.

Of course, the phases of the first power division input terminal a1 and the first power division output terminal b1 may also be different, and then the phases of the corresponding second power division output terminal b2 and the seventh power division output terminal b7 are also different. For example, the phases of the first power division input terminal a1 and the first power division output terminal b1 are different by 10 °,20 °, and the like, and the phases of the corresponding second power division output terminal b2 and the seventh power division output terminal b7 are also different by 10 °,20 °. The embodiment of the application is only illustrated by taking the example that the phases of the first power division input end a1 and the first power division output end b1 are the same, and the phases of the second power division output end b2 and the seventh power division output end b7 are the same, and the application is not limited in any way.

Optionally, the first power division output end b1 and the second power division output end b2 have a phase difference of 60 degrees to 120 degrees or-60 degrees to-120 degrees.

For example, the phase of the first power division output end b1 is advanced relative to the phase of the second power division output end b2, and the first power division output end b1 and the second power division output end b2 have a phase difference of 60 ° to 120 °.

The signal power division of the first power division input end a1 is coupled to the first power division output end b1, and the signal after power division is transmitted to the second power division output end b2 through the phase delay line.

For example, the first power division output b1 and the second power division output b2 have a phase difference of 70 °, 80 °, 90 °, 100 °, 110 °.

Or, for example, the phase of the first power division output end b1 is delayed relative to the phase of the second power division output end b2, and the first power division output end b1 and the second power division output end b2 have a phase difference of-60 degrees to-120 degrees.

The signal power division of the first power division input end a1 is coupled to the second power division output end b2, and the signal after power division is transmitted to the first power division output end b1 through a phase delay line.

For example, the first power split output b1 and the second power split output b2 have a phase difference of-70 °, -80 °, -90 °, -100 °, -110 °.

The first power divider PS1 is configured to distribute a signal received by the radio frequency input terminal RFI to a branch where the first Doherty circuit DT1 is located and a branch where the second Doherty circuit DT2 is located, and the structure of the first power divider PS1 is not limited in the embodiment of the present application, which is just an illustration.

In the following, the first power divider PS1 is a 90 ° power divider, alternatively referred to as a 90 ° coupler, alternatively referred to as a 90 ° bridge, and the phase of the second power divider output b2 is delayed by 90 ° (-90 °) with respect to the phase of the first power divider output b 1. For example, the phase of the first power division output b1 is 0 ° and the phase of the second power division output b2 is-90 °. Of course, the phase shown in the embodiment of the present application is only one example, and is not limited in any way. For example, a phase of the first power division output b1 of 10 ° and a phase of the second power division output b2 of-80 ° is also a possible implementation.

In some embodiments, the first power division input terminal a1 is coupled to the radio frequency input terminal RFI, the first power division output terminal b1 is coupled to the first Doherty circuit DT1, the second power division output terminal b2 is coupled to the second Doherty circuit DT2, and the seventh power division output terminal b7 is coupled to the reference ground voltage terminal GND.

Then, the signal received by the first Doherty circuit DT1 and the signal received by the second Doherty circuit DT2 have the above-described phase difference.

In some embodiments, the power amplifier circuit further includes a first resistor R1, and the first resistor R1 is coupled between the seventh power division output terminal b7 and the reference ground voltage terminal GND.

The first Doherty circuit DT1 is coupled between the first power dividing output terminal b1 and the first combining point Q1, the input terminal of the first Doherty circuit DT1 is coupled to the first power dividing output terminal b1, and the output terminal of the first Doherty circuit DT1 is coupled to the first combining point Q1.

The second Doherty circuit DT2 is coupled between the second power dividing output terminal b2 and the second combining point Q2, the input terminal of the second Doherty circuit DT2 is coupled to the second power dividing output terminal b2, and the output terminal of the second Doherty circuit DT2 is coupled to the second combining point Q2.

If the second power division output b2 is phase-delayed by 90 ° (-90 °) with respect to the first power division output b1, the second combining point Q2 is phase-delayed by 90 ° (-90 °) with respect to the first combining point Q1. Alternatively, the phase of the first power division output b1 is advanced by 90 ° (+90°) with respect to the phase of the second power division output b2, and then the first combining point Q1 is advanced by 90 ° (+90°) with respect to the second combining point Q2.

The first impedance transformer U is coupled between the first combining point Q1 and the third combining point Q3, and is used for reversely counteracting the phase advance of the first combining point Q1 relative to the second combining point Q2 or reversely compensating the phase lag of the first combining point Q1 relative to the second combining point Q2. After the signal of the first combining point Q1 is converted by the first impedance converter U, the phase of the signal transmitted to the third combining point Q3 is the same as the phase of the signal of the second combining point Q2.

The second combining point Q2 is coupled to the third combining point Q3 to implement combining of the signal output by the first Doherty circuit DT1 and the signal output by the second Doherty circuit DT 2.

The third combining point Q3 is coupled to the rf output terminal RFO, and transmits the amplified signal from the rf output terminal RFO to the load.

The power amplifier circuit provided by the embodiment of the application comprises a first Doherty circuit DT1 and a second Doherty circuit DT2 which are connected in parallel, and when the load impedance coupled with a radio frequency output end RFO changes (for example, from 50 ohms to 100 ohms), the load impedance of the second Doherty circuit DT2 becomes 100 ohms. However, since the first Doherty circuit DT1 is connected in series with the first impedance converter U, the load impedance of the first Doherty circuit DT1 is smaller than 100 ohms (the actual value is related to the performance of the first impedance converter U, and the load impedance of the first Doherty circuit DT1 may be smaller than 50 ohms). Then, at this time, the first Doherty circuit DT1 corresponds to a small impedance of less than 50 ohms, and the second Doherty circuit DT2 corresponds to a large impedance of more than 50 ohms. While the smaller the impedance the greater the power, the greater the impedance the lesser the power. Therefore, when the second Doherty circuit DT2 has a power reduced due to a large load impedance, the first Doherty circuit DT1 is synchronized to have a power increased due to a small load impedance. After the first Doherty circuit DT1 and the second Doherty circuit DT2 are combined at the third combining point Q3, the first Doherty circuit DT1 compensates for the performance loss of the second Doherty circuit DT2, and after the branch circuit where the first Doherty circuit DT1 is located and the branch circuit where the second Doherty circuit DT2 is located are complementary, the sensitivity of the power amplifier circuit to load impedance variation can be reduced.

Similarly, when the second Doherty circuit DT2 increases in power due to a decrease in load impedance, the first Doherty circuit DT1 decreases in power due to an increase in load impedance in synchronization. After the first Doherty circuit DT1 and the second Doherty circuit DT2 are combined at the third combining point Q3, the performance excess of the second Doherty circuit DT2 is reduced by the first Doherty circuit DT1, and after the branches of the first Doherty circuit DT1 and the second Doherty circuit DT2 are complementary, the sensitivity of the power amplifier circuit to load impedance variation can be reduced.

Based on this, in the power amplifier circuit provided by the embodiment of the application, since the branch where the first Doherty circuit DT1 is located is provided with the first impedance transformer U, the branch where the first Doherty circuit DT1 is located and the branch where the second Doherty circuit DT2 is located can be used as two complementary branches by the impedance transformation function of the first impedance transformer U. In the case of load impedance mismatch, the first Doherty circuit DT1 is severely degraded on the left side of a smith chart, and the second Doherty circuit DT2 is severely degraded on the right side of the smith chart, and both are just complementary structures. The branch circuit where the first Doherty circuit DT1 and the second Doherty circuit DT2 are connected in parallel performs power synthesis at the third combining point Q3, and the performance loss of the other party can be compensated based on the complementation of the first Doherty circuit DT1 and the second Doherty circuit DT2, so that the performance degradation of the power amplifier caused by the load impedance mismatch is reduced.

In addition, the power amplifier circuit adopts two complementary first Doherty circuits DT1 and second Doherty circuits DT2 to realize load desensitization, and complicated, large-area or high-insertion-loss circuit modules are not required to be introduced, so that the redundancy degree of the circuit is reduced. Therefore, the scheme has the advantages of simple circuit structure, easy realization, small matching circuit area, small insertion loss and high link efficiency, and improves the mismatch resistance of the circuit at lower cost.

Furthermore, the power amplifier circuit comprises a first Doherty circuit DT1 and a second Doherty circuit DT2, so that the efficiency of the power amplifier circuit can be improved, and the working bandwidth of the power amplifier circuit can be widened.

The embodiment of the application does not limit the structures of the first Doherty circuit DT1 and the second Doherty circuit DT2, and the Doherty circuits in the related art are all applicable to the embodiment of the application.

Fig. 5 is a schematic topology diagram of a power amplifier circuit according to an embodiment of the present application.

As shown in fig. 5, in some embodiments, the first Doherty circuit DT1 includes a second power divider PS2, a first amplifier M1, a second amplifier P1, a first impedance matching network W1, and a second impedance matching network W2.

Illustratively, the first Doherty circuit DT1 is a first outphasing technology Doherty circuit, and phases of signals output by the first amplifier M1 and the second amplifier P1 are positive and negative outphasing.

In some embodiments, the first amplifier M1 may be, for example, a Main amplifier (MAIN AMPLIFIER, or referred to as Main PA) or referred to as carrier amplifier, and the second amplifier P1 may be, for example, a Peak amplifier (PEAK AMPLIFIER, or referred to as Peak PA). It should be appreciated that the structure of the main and peak amplifiers may be identical, distinguishing the main and peak amplifiers according to the matching network to which they are coupled.

The second power divider PS2 is configured to divide the received signal equally into a branch where the first amplifier M1 is located and a branch where the second amplifier P1 is located.

In some embodiments, the second power divider PS2 includes a second power divider input a2, a third power divider output b3, and a fourth power divider output b4.

In some embodiments, the second power divider PS2 further comprises an eighth power divider output b8.

For example, the phases of the second power division input end a2 and the third power division output end b3 are the same, the third power division output end b3 and the fourth power division output end b4 have a phase difference, and the phases of the fourth power division output end b4 and the eighth power division output end b8 are the same.

Of course, the phases of the second power division input terminal a2 and the third power division output terminal b3 may also be different, and then the phases of the corresponding fourth power division output terminal b4 and the eighth power division output terminal b8 are also different. For example, the phases of the second power division input terminal a2 and the third power division output terminal b3 differ by 10 °, 20 °, and the like, and the phases of the corresponding fourth power division output terminal b4 and eighth power division output terminal b8 also differ by 10 °, 20 °. The embodiment of the application is only illustrated by taking the example that the phases of the second power division input end a2 and the third power division output end b3 are the same, and the phases of the fourth power division output end b4 and the eighth power division output end b8 are the same, and the application is not limited in any way.

Optionally, the third power division output end b3 and the fourth power division output end b4 have a phase difference of 60 degrees to 120 degrees or-60 degrees to-120 degrees.

For example, the signal power division of the second power division input terminal a2 is coupled to the third power division output terminal b3, and the signal after power division is transmitted to the fourth power division output terminal b4 through the phase delay line.

The third power division output b3 and the fourth power division output b4 have a phase difference of 70 °, 80 °, 90 °, 100 °, 110 °.

In the following, the second power divider PS2 is taken as a 90 ° power divider, and the phase delay of the fourth power divider output b4 with respect to the third power divider output b3 by 90 ° (-90 °) is schematically illustrated.

In some embodiments, the second power division input terminal a2 is coupled to the first power division output terminal b1, the third power division output terminal b3 is coupled to the input terminal of the first amplifier M1, the fourth power division output terminal b4 is coupled to the input terminal of the second amplifier P1, and the eighth power division output terminal b8 is coupled to the reference ground voltage terminal GND.

In some embodiments, the power amplifier circuit further includes a second resistor R2, and the second resistor R1 is coupled between the eighth power division output terminal b8 and the reference ground voltage terminal GND.

The structure of the first amplifier M1 and the second amplifier P1 is not limited in the embodiment of the present application, and the structure of the power amplifier and the power amplifier in the related art are applicable to the embodiment of the present application.

The first impedance matching network W1 is coupled between the output terminal of the first amplifier M1 and the first combining point Q1, and the second impedance matching network W2 is coupled between the output terminal of the second amplifier P1 and the first combining point Q1.

That is, the output branch of the first impedance matching network W1 and the output branch of the second impedance matching network W2 are combined at the first combining point Q1. Then, the phase of the signal output from the first impedance matching network W1 is the same as the phase of the signal output from the second impedance matching network W2.

For example, the second power divider PS2 is a 90 ° power divider, the phase of the signal received at the second power divider input a2 is 0 °, the phase of the signal coupled to the third power divider output b3 is 0 °, and the phase of the signal received at the fourth power divider output b4 is-90 °. Of course, the phase shown in the embodiment of the present application is only one example, and is not limited in any way.

In some embodiments, the second impedance matching network W2 and the first impedance matching network W1 are out of phase by 60 ° to 120 °.

In some embodiments, the phase difference between the third power division output terminal b3 and the fourth power division output terminal b4 is the same as the phase difference between the second impedance matching network W2 and the first impedance matching network W1.

Optionally, the second impedance matching network W2 and the first impedance matching network W1 are 90 ° out of phase.

For example, the first impedance matching network W1 is a-30 ° phase delay line, the second impedance matching network W2 is a +60° phase compensation line, and the phase of the first combining point Q1 is-30 °.

Or, for example, the first impedance matching network W1 is a-45 ° phase delay line, the second impedance matching network W2 is a +45° phase compensation line, and the phase of the first combining point Q1 is-45 °.

Or, for example, the first impedance matching network W1 is a-60 ° phase compensation line, the second impedance matching network W2 is a +30° phase compensation line, and the phase of the first combining point Q1 is-60 °.

Of course, the structures of the second impedance matching network W2 and the first impedance matching network W1 are not limited in the embodiment of the present application, and the phase difference between the two is only required to be 60 ° to 120 °.

Optionally, the first impedance matching network W1 comprises an inductive network and the second impedance matching network W2 comprises a capacitive network.

With continued reference to fig. 5, for example, the first impedance matching network W1 includes a first inductance L1 and the second impedance matching network W2 includes a first capacitance C1.

In this way, the circuit structures of the first impedance matching network W1 and the second impedance matching network W2 are simple, and the area of the power amplifier can be reduced.

In some embodiments, the first inductance L1 has a value of 0.1NH-2NH.

For example, the value of the first inductance L1 is 0.2NH、0.3NH、0.4NH、0.5NH、0.6NH、0.4NH、0.7NH、0.9NH、1.0NH、1.1NH、1.2NH、1.3NH、1.4NH、1.5NH、1.5NH、1.7NH、1.8NH or 1.9NH.

In some embodiments, the first capacitance C1 and the first inductance L1 are sized to provide a 90 ° phase difference at or near the center frequency point of the operating bandwidth.

By limiting the value of the first inductance L1 to 0.1NH-2NH, the first impedance matching network W1 can have better performance.

In some embodiments, the frequency band applicable to the power amplifier circuit provided by the embodiment of the application is sub6G, and the applicable frequency band comprises at least a part of 3.3GHz-5 GHz. In one embodiment, the relative bandwidth=interval difference/center frequency point=1.7/4.15≡41% of the working frequency band used by the power amplifier circuit provided by the embodiment of the application.

Of course, the embodiment of the application is not limited to the power amplifier circuit being applicable to the sub6G frequency band, the sub3G frequency band, the WIFI frequency band (for example, 2.4G frequency band, 5G frequency band, 6G frequency band) and other frequency bands.

In some embodiments, the first capacitor C1 has a value of 0.2PF-5PF.

For example, the first capacitor C1 has a value 0.3PF、0.5PF、0.7PF、1.0PF、1.3PF、1.5PF、1.7PF、2.1PF、2.3PF、2.5PF、2.7PF、3.0PF、3.3PF、3.5PF、3.7PF、4.0PF、4.3PF、4.5PF or 4.7PF.

In some embodiments, the first capacitance C1 is sized to provide a +45° phase shift at or near the center frequency point of the operating bandwidth.

By limiting the value of the first capacitor C1 to 0.2PF-5PF, the second impedance matching network W2 can have better performance.

The embodiment of the application does not limit the structures of the first impedance matching network W1 and the second impedance matching network W2, and can make the phase of the signal output by the first impedance matching network W1 identical to the phase of the signal output by the second impedance matching network W2.

Fig. 6A to fig. 6D are schematic topology diagrams of a first Doherty circuit DT1 according to an embodiment of the present application.

As shown in fig. 6A, in other embodiments, the first Doherty circuit DT1 includes a second power divider PS2, a first amplifier M1, a second amplifier P1, and a sixth impedance matching network W6.

The sixth impedance matching network W6 is coupled between the first amplifier M1 and the first node Q1, and the sixth impedance matching network W6 is a 90 ° phase delay line (-90 °).

For example, as shown in fig. 6A, the sixth impedance matching network W6 is a "T" network structure with two inductors L and a capacitor C, the two inductors L are connected in series between the output end of the first amplifier M1 and the first combining point Q1, one end of the capacitor C is coupled between the two inductors L, and the other end of the capacitor C is coupled to the reference ground voltage end GND.

Alternatively, as shown in fig. 6B, the sixth impedance matching network W6 is a pi-type network structure of two capacitors C of an inductor L, the inductor L is connected in series between the output end of the first amplifier M1 and the first combining point Q1, one end of one capacitor C is coupled between the output end of the first amplifier M1 and the inductor L, and the other end is coupled with the reference ground voltage GND. One end of the other capacitor is coupled between the first combining point Q1 and the inductor L, and the other end is coupled to the ground voltage GND.

In this case, as shown in fig. 6A and 6B, the third power split output B3 and the fourth power split output B4 have a phase difference of 60 ° to 120 °.

As shown in fig. 6C, in further embodiments, the first Doherty circuit DT1 includes a second power divider PS2, a first amplifier M1, a second amplifier P1, and a seventh impedance matching network W7.

The seventh impedance matching network W7 is coupled between the first amplifier M1 and the first node Q1, and the seventh impedance matching network W7 is a 90 ° phase compensation line (+90°).

For example, as shown in fig. 6C, the seventh impedance matching network W7 is a "T" network structure with two capacitors C and an inductor L, wherein the two capacitors C are connected in series between the output end of the first amplifier M1 and the first combining point Q1, one end of the inductor L is coupled between the two inductors L, and the other end is coupled to the reference ground voltage GND.

Or as shown in fig. 6D, the seventh impedance matching network W7 is a pi-type network structure with two inductors L and a capacitor C, the capacitor C is connected in series between the output end of the first amplifier M1 and the first combining point Q1, one end of one inductor L is coupled between the output end of the first amplifier M1 and the capacitor C, and the other end is coupled with the reference ground voltage GND. One end of the other inductor L is coupled between the capacitor and the first junction Q1, and the other end is coupled to the ground voltage GND.

In this case, as shown in fig. 6C and 6D, the third power split output b3 and the fourth power split output b4 have a phase difference of-60 ° to-120 °.

Returning to fig. 5, in some embodiments, the second Doherty circuit DT2 includes a third power divider PS3, a third impedance matching network W3, and a fourth impedance matching network W4.

The third power divider PS3 includes a third power dividing input terminal a3, a fifth power dividing output terminal b5, and a sixth power dividing output terminal b6.

In some embodiments, the third power divider PS3 further comprises a ninth power divider output b9.

For example, the third power division input terminal a3 and the fifth power division output terminal b5 have the same phase, the fifth power division output terminal b5 and the sixth power division output terminal b6 have the same phase, and the sixth power division output terminal b6 and the ninth power division output terminal b9 have the same phase.

Of course, the phases of the third power division input terminal a3 and the fifth power division output terminal b5 may also be different, and then the phases of the corresponding sixth power division output terminal b6 and the ninth power division output terminal b9 are also different. For example, the third power division input terminal a3 and the fifth power division output terminal b5 are different in phase by 10 °, 20 °, and the like, and the corresponding sixth power division output terminal b6 and the ninth power division output terminal b9 are also different in phase by 10 °, 20 °. The embodiment of the application is only illustrated by taking the phase of the third power division input end a3 and the phase of the fifth power division output end b5 as the same, and the phase of the sixth power division output end b6 and the phase of the ninth power division output end b9 as the same, and the application is not limited in any way.

Optionally, the fifth power division output end b5 and the sixth power division output end b6 have a phase difference of 60 ° to 120 °.

It should be noted that the phase of the fifth power division output terminal b5 may be delayed by 60 ° to 120 ° with respect to the phase of the sixth power division output terminal b6, or the phase of the sixth power division output terminal b6 may be delayed by 60 ° to 120 ° with respect to the phase of the fifth power division output terminal b5, which is not limited by the embodiment of the present application, and fig. 5 is only a schematic diagram.

For example, the signal power division of the third power division input terminal a3 is coupled to the fifth power division output terminal b5, and the signal after power division is transmitted to the sixth power division output terminal b6 through the phase delay line.

The fifth power division output b5 and the sixth power division output b6 have a phase difference of 70 °, 80 °, 90 °, 100 °, 110 °.

In the following, the third power divider PS3 is taken as a 90 ° power divider, and the phase delay of the sixth power divider output b6 with respect to the fifth power divider output b5 by 90 ° (-90 °) is schematically illustrated.

In some embodiments, the third power division input terminal a3 is coupled to the second power division output terminal b2, the fifth power division output terminal b5 is coupled to the input terminal of the third amplifier M2, the sixth power division output terminal b6 is coupled to the input terminal of the fourth amplifier P2, and the ninth power division output terminal b9 is coupled to the reference ground voltage terminal GND.

In some embodiments, the power amplifier circuit further includes a third resistor R3, and the third resistor R3 is coupled between the ninth power division output terminal b9 and the reference ground voltage terminal GND.

The third impedance matching network W3 is coupled between the output end of the third amplifier M2 and the second combining point Q2, and the fourth impedance matching network W4 is coupled between the output end of the fourth amplifier P2 and the second combining point Q2.

That is, the output branch of the third impedance matching network W3 and the output branch of the fourth impedance matching network W4 are combined at the second combining point Q2. Then, the phase of the signal output from the third impedance matching network W3 is the same as the phase of the signal output from the fourth impedance matching network W4.

For example, the third power divider PS3 is a 90 ° power divider, the phase of the signal received by the third power divider input a3 is-90 °, the phase of the signal coupled to the fifth power divider output b5 is-90 °, and the phase of the signal received by the sixth power divider output b6 is-180 °. Of course, the phase shown in the embodiment of the present application is only one example, and is not limited in any way.

In some embodiments, the fourth and third impedance matching networks W4, W3 are 60 ° to 120 ° out of phase.

In some embodiments, the phase difference between the fifth power division output b5 and the sixth power division output b6 is the same as the phase difference between the fourth impedance matching network W4 and the third impedance matching network W3.

Optionally, the fourth impedance matching network W4 and the third impedance matching network W3 are 90 ° out of phase.

For example, the third impedance matching network W3 is a-30 ° phase delay line, the fourth impedance matching network W4 is a +60° phase compensation line, and the phase of the first combining point Q1 is-30 °.

Or, for example, the third impedance matching network W3 is a-45 ° phase delay line, the fourth impedance matching network W4 is a +45° phase compensation line, and the phase of the first combining point Q1 is-45 °.

Or, for example, the third impedance matching network W3 is a-60 ° phase compensation line, the fourth impedance matching network W4 is a +30° phase compensation line, and the phase of the first combining point Q1 is-60 °.

Of course, the structures of the fourth impedance matching network W4 and the third impedance matching network W3 are not limited in the embodiment of the present application, and the phase difference between them may be 60 ° to 120 °.

Optionally, the third impedance matching network W3 comprises an inductive network and the fourth impedance matching network W4 comprises a capacitive network.

With continued reference to fig. 5, for example, the third impedance matching network W3 includes a second inductance L2 and the fourth impedance matching network W4 includes a second capacitance C2.

In some embodiments, the second inductance L2 has a value of 0.1NH-2NH.

For example, the value of the second inductance L2 is 0.2NH、0.3NH、0.4NH、0.5NH、0.6NH、0.4NH、0.7NH、0.9NH、1.0NH、1.1NH、1.2NH、1.3NH、1.4NH、1.5NH、1.5NH、1.7NH、1.8NH or 1.9NH.

By limiting the value of the second inductance L2 to 0.1NH-2NH, the third impedance matching network W3 can have better performance.

In some embodiments, the second capacitor C2 has a value of 0.2PF-5PF.

For example, the second capacitor C2 has a value 0.3PF、0.5PF、0.7PF、1.0PF、1.3PF、1.5PF、1.7PF、2.1PF、2.3PF、2.5PF、2.7PF、3.0PF、3.3PF、3.5PF、3.7PF、4.0PF、4.3PF、4.5PF or 4.7PF.

In some embodiments, the second capacitance C2 and the second inductance L2 are sized to provide a 90 ° phase difference at or near the center frequency point of the operating bandwidth.

By limiting the value of the second capacitor C1 to 0.2PF-5PF, the fourth impedance matching network W4 can have better performance.

The structure of the third impedance matching network W3 and the fourth impedance matching network W4 is not limited in the embodiment of the present application, and the phase of the signal output by the third impedance matching network W3 may be the same as the phase of the signal output by the fourth impedance matching network W4.

In other embodiments, the second Doherty circuit DT1 includes a third power divider PS3, a third amplifier M2, a fourth amplifier P2, and an eighth impedance matching network.

The eighth impedance matching network is coupled between the third amplifier M2 and the second node Q2, for example, the eighth impedance matching network is a 90 ° phase delay line (-90 °).

The structure of the eighth impedance matching network may be, for example, the same as that of the sixth impedance matching network W6 described above, and reference is made to the above description.

In this case, the fifth power division output b5 and the sixth power division output b6 have a phase difference of 60 ° to 120 °.

In further embodiments, the second Doherty circuit DT1 comprises a third power divider PS3, a third amplifier M2, a fourth amplifier P2, and a ninth impedance matching network.

The ninth impedance matching network is coupled between the third amplifier M2 and the second node Q2, for example, the ninth impedance matching network is a 90 ° phase compensation line (+90°).

The structure of the ninth impedance matching network may be, for example, the same as that of the seventh impedance matching network W7 described above, and reference is made to the above-described related description.

In this case, the fifth power division output b5 and the sixth power division output b6 have a phase difference of-60 ° to-120 °.

In the embodiment of the present application, the structure of the first Doherty circuit DT1 and the structure of the second Doherty circuit DT2 may be the same, and of course, the structures of the two may be different.

When the load impedance changes, the impedance changes received by the first and third amplifiers M1 and M2 are opposite, and the impedance changes received by the second and fourth amplifiers P1 and P2 are opposite. Thus, under various mismatch conditions, the performance of the power saturation point and the rollback high-efficiency point can be kept stable, so that performance fluctuation caused by mismatch is reduced.

With continued reference to fig. 5, in some embodiments, the first impedance transformer U is coupled between the first combining point Q1 and the third combining point Q3, the second combining point Q2 is coupled to the third combining point Q3, and the third combining point Q3 is coupled to the rf output terminal RFO.

For example, the first combining point Q1 is coupled to the third combining point Q3 after passing through the first impedance transformer U, the second combining point Q2 is coupled to the third combining point Q3 through a trace, or the second combining point Q2 coincides with the third combining point Q3, so as to implement the combination of the signal of the branch where the first Doherty circuit DT1 is located and the signal of the branch where the second Doherty circuit DT2 is located at the third combining point Q3, and the combined signal is transmitted to the radio frequency output end RFO.

In some embodiments, the phases of the second combining point Q2 and the third combining point Q3 are the same.

In some embodiments, the phase difference between the third combining point Q3 and the first combining point Q1 is 60 ° to 120 ° or-60 ° to-120 °.

Illustratively, the phase change of the first impedance transformer U matches the phase difference between the first power division output b1 and the second power division output b2 in the first power divider PS 1.

Optionally, the phase difference between the third combining point Q3 and the first combining point Q1 is 70 °, 80 °, 90 °, 100 °, 110 °.

For example, the second power division output b2 is phase-delayed by 90 ° (-90 °) with respect to the first power division output b1, and then the third combining point Q3 at both ends of the first impedance transformer U is phase-delayed by 90 ° (-90 °) with respect to the first combining point Q1.

For example, the phase difference between the third combining point Q3 and the first combining point Q1 may be a phase difference between the third combining point Q3 and the first combining point Q1 at a center frequency point of an operation bandwidth of the power amplifier circuit.

The phase difference between the third combining point Q3 and the first combining point Q1 affects the impedance transformation capability of the impedance transformer, thereby affecting the complementary effect of the first Doherty circuit DT1 and the second Doherty circuit DT2 to affect the output performance of the power amplifier circuit. The value range of the phase difference between the third combining point Q3 and the first combining point Q1 is limited to 60-120 degrees or-60-120 degrees, so that the first Doherty circuit DT1 and the second Doherty circuit DT2 have better complementary effects, and the performance of the power amplifier circuit is ensured.

In some embodiments, the first impedance transformer U is a 1/4 wavelength transformer, alternatively referred to as a 90 delay line.

In some embodiments, the "1/4 wavelength" corresponding to the first impedance transformer U is 1/4 of the wavelength corresponding to the center frequency point of the operating bandwidth.

As shown in fig. 5, for example, the first impedance transformer U has a "T" type network structure including a third inductance L3, a fourth inductance L4, and a third capacitance C3. The third inductor L3 and the fourth inductor L4 are connected in series between the first combining point Q1 and the third combining point Q3, one end of the third capacitor C3 is coupled to the ground voltage GND, and the other end is coupled between the third inductor L3 and the fourth inductor L4.

Or for example, the first impedance transformer U is a "pi" network structure comprising two capacitors and one inductor.

Or, for example, the first combining point Q1 is coupled to the third combining point Q3 after passing through the first impedance transformer U, and the second combining point Q2 is coupled to the third combining point Q3 through the second impedance transformer, so as to implement combining of the signal of the branch where the first Doherty circuit DT1 is located and the signal of the branch where the second Doherty circuit DT2 is located at the third combining point Q3, and the combined signal is transmitted to the radio frequency output end RFO.

In some embodiments, the power amplifier module further includes a second impedance transformer coupled between the second combining point Q2 and the third combining point Q3, and the second impedance transformer is configured to adjust a phase difference between the second combining point Q2 and the third combining point Q3.

In some embodiments, the phase of the signal output by the first Doherty circuit DT1 after passing through the first impedance transformer U is the same as the phase of the signal output by the second Doherty circuit DT2 after passing through the second impedance transformer.

In other embodiments, the phase of the signal output by the first Doherty circuit DT1 after passing through the first impedance transformer U may be different from the phase of the signal output by the second Doherty circuit DT2 after passing through the second impedance transformer.

As shown in fig. 5, in some embodiments, the power amplifier module further includes a fifth impedance matching network W5, and the fifth impedance matching network W5 is coupled between the third combining point Q3 and the rf output terminal RFO.

The fifth impedance matching network W5 is used to impedance match the load 50ohm to a desired impedance point to improve the efficiency of the power amplifier circuit.

Fig. 7A and fig. 7B are schematic diagrams of a topology of another power amplifier circuit according to an embodiment of the present application.

In some embodiments, as shown in fig. 7A, the power amplifier circuit includes two cascaded power amplifiers, shown in fig. 5 as a cascaded power amplifier at the second stage, and further includes a first cascaded power amplifier PA1 at the first stage.

The power amplifier circuit comprises a multi-stage cascade power amplifier, and can increase the amplification factor of the power amplifier.

Wherein the first cascaded power amplifier PA1 is coupled in series with the first power divider PS 1.

For example, as shown in fig. 7A, the first cascaded power amplifier PA1 is coupled between the radio frequency input RFI and the first power divider PS 1. That is, the first cascaded power amplifier PA1 is located before the input of the first power divider PS 1.

Alternatively, as shown in fig. 7B, the first cascade power amplifier PA1 includes a first sub power amplifier PA1 and a second sub power amplifier PA2, the first sub power amplifier PA1 is coupled between the first power division output terminal B1 and the second power division input terminal a2, and the second sub power amplifier PA2 is coupled between the second power division output terminal B2 and the third power division input terminal a 3.

That is, the first cascaded power amplifier PA1 is located at the output end of the first power divider PS 1.

Since the first power divider PS1 itself has an insertion loss, the required power is high. Therefore, the first cascade power amplifier PA1 is placed at the output end of the first power divider PS1, so that the power requirement of the first cascade power amplifier PA1 can be reduced, and the efficiency of the power amplifier circuit can be improved.

Fig. 8 is a schematic diagram of a topology of another power amplifier circuit according to an embodiment of the present application.

In some embodiments, as shown in fig. 8, the power amplifier circuit includes three cascaded power amplifiers, and as shown in fig. 5, the cascaded power amplifiers are located in a third stage, and the power amplifier circuit further includes a second cascaded power amplifier PA1 located in a first stage and a first cascaded power amplifier PA1 located in a second stage.

The second cascade power amplifier PA2 is coupled between the radio frequency input terminal RFI and the first power division input terminal a 1. In some embodiments, where the power amplifier circuit further comprises a first cascaded power amplifier PA1, the second cascaded power amplifier PA2 is coupled between the radio frequency input RFI and the first cascaded power amplifier PA 1.

It will be appreciated that the first cascaded power amplifier PA1 may be configured as shown in fig. 7A or fig. 7B, and is shown in fig. 8 by way of illustration only and not limitation.

In some embodiments, the second cascade power amplifier PA2 may further include a third sub power amplifier between the first power division output b1 and the first sub power amplifier PA1 and a fourth sub power amplifier between the second power division output b2 and the second sub power amplifier PA 2.

Fig. 9A-9C are schematic diagrams of a radio frequency performance according to an embodiment of the present application.

In fig. 9A, the abscissa indicates the output power, and the ordinate indicates the gain. In fig. 9B, the abscissa indicates the output power, and the ordinate indicates the backoff efficiency. According to simulation, compared with a power amplifier circuit comprising a single Doherty, the power amplifier circuit comprising the three-stage cascade power amplifier provided by the embodiment of the application has the advantages that under the conditions that the load is 50 ohms and the frequency bandwidth is 3300MHz-5000MHz, the output power of gain compression 3dB (P-3 dB) is more than 35.5dBm, and the rollback efficiency is more than 32%.

In fig. 9C, the abscissa indicates the output power, and the ordinate indicates the gain. In fig. 9D, the abscissa indicates the output power, and the ordinate indicates the backoff efficiency. Simulation shows that the amplitude of the Voltage STANDING WAVE Ratio (VSWR) of the power amplifier circuit provided by the embodiment of the application is equal to 2.33, the radio frequency performance of the phase (Theta) scanned (stepped to 45 DEG) within a 360 DEG range is analyzed, the saturated power (P-1 dB compression) is deteriorated by <1.5dB, and the efficiency is deteriorated by <7% (the rollback efficiency is 32 dBm).

The foregoing is a schematic description of the topology structure of the power amplifier circuit provided by the embodiment of the present application, and the schematic description of the power amplifier module provided by the embodiment of the present application is based on the topology structure of the power amplifier circuit, where the power amplifier circuit is integrated in the power amplifier module.

An embodiment of the present application provides a power amplifier module, which may be used as a PA in the rf front-end module 101 shown in fig. 2, for example.

As shown in fig. 10, the power amplifier module includes a power amplifier chip and a substrate, the power amplifier chip being disposed on the substrate.

The power amplifier chip in the embodiment of the application may be a bare chip (die) or a chip (chip) after packaging, which is not limited in the embodiment of the application.

In some embodiments, as shown in fig. 10, the power amplifier chip includes a radio frequency input terminal RFI, a first output terminal O1, a second output terminal O2, a third output terminal O3, and a fourth output terminal O4, the radio frequency input terminal RFI is configured to receive a signal, and the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 are configured to output the signal.

It should be noted that the rf input terminal RFI, the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 may be ports formed by one pad, or may be ports formed by a plurality of pads.

On this basis, as shown in fig. 8, the power amplifier chip further includes a first power divider PS1, a second power divider PS2, a third power divider PS3, a first amplifier M1, a second amplifier P1, a third amplifier M2, and a fourth amplifier P2 in the power amplifier circuit.

The output end of the first amplifier M1 is coupled to the first output end O1, the output end of the second amplifier P1 is coupled to the second output end O2, the output end of the third amplifier M2 is coupled to the third output end O3, and the output end of the fourth amplifier P2 is coupled to the fourth output end O4.

In some embodiments, the substrate includes a first region and a second region, the power amplifier chip is located in the first region, and at least one of the first impedance matching network W1, the second impedance matching network W2, the third impedance matching network W3, the fourth impedance matching network W4, and the impedance transformer U is located in the second region.

Alternatively, it is understood that the first, second, third, fourth and impedance matching networks W1, W2, W3, W4 and the impedance transformer U are not integrated in the power amplifier chip.

In some embodiments, the first region and the second region of the substrate are different regions on the same side of the substrate. In some embodiments, the first and second regions of the substrate are regions on different sides of the substrate (e.g., one side and the other side of the substrate).

For example, the first inductor L1, the first capacitor C1, the second inductor L2, and the second capacitor C2 are all discrete devices, the first output terminal O1 is coupled to the first inductor L1 through a bonding wire (also referred to as a bonding wire), the second output terminal O2 is coupled to the first capacitor C1 through a bonding wire, the third output terminal O3 is coupled to the second inductor L2 through a bonding wire, and the fourth output terminal O4 is coupled to the second capacitor C2 through a bonding wire.

Or, for example, the first capacitor C1 and the second capacitor C2 are discrete devices, and the bonding wire is directly used as the first inductor L1 and the second inductor L2.

Or, for example, the first capacitor C1 and the second capacitor C2 are discrete devices, and traces in the substrate, such as transmission lines and microstrip lines, are used as the first inductor L1 and the second inductor L2. In one embodiment, the traces in the substrate include bond wires.

Of course, the embodiments of the present application are not limited thereto, and the above is merely illustrative.

With continued reference to fig. 8, in the case where the power amplifier circuit further includes a first cascaded power amplifier and a second cascaded power amplifier, the first cascaded power amplifier and the second cascaded power amplifier are also located in the power amplifier chip.

The first impedance matching network W1, the second impedance matching network W2, the third impedance matching network W3, the fourth impedance matching network W4, and the first impedance transformer U in the power amplifier circuit are all disposed on the substrate or at least part of the devices are integrated in the substrate.

The power amplifier circuit further comprises a fifth impedance matching network W5, and the fifth impedance matching network W5 is disposed on the substrate.

It should be noted here that the above description is given by taking an example in which a part of devices in the power amplifier circuit are located in the power amplifier chip and a part of devices are located on the substrate. Of course, all devices in the power amplifier circuit provided by the embodiment of the application can also be arranged in the power amplifier chip. In addition, some devices may be located in the power amplifier chip, and some devices may be located on the substrate, but the components located in the power amplifier chip are different from those shown in the above embodiments. The embodiment of the application does not limit the layout of devices in the power amplifier circuit, and the illustration in the embodiment is only one illustration.

The present application is not limited to the above embodiments, and any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A power amplifier chip, comprising:

A radio frequency input terminal (RFI), a first output terminal (O1), a second output terminal (O2), a third output terminal (O3) and a fourth output terminal (O4);

A first power divider (PS1), comprising a first power divider input terminal (a1), a first power divider output terminal (b1) and a second power divider output terminal (b2);

A second power divider (PS2), comprising a second power divider input terminal (a2), a third power divider output terminal (b3) and a fourth power divider output terminal (b4);

A third power divider (PS3), comprising a third power divider input terminal (a3), a fifth power divider output terminal (b5) and a sixth power divider output terminal (b6);

The first power division input terminal (a1) is coupled to the radio frequency input terminal (RFI), the first power division output terminal (b1) is coupled to the second power division input terminal (a2), and the second power division output terminal (b2) is coupled to the third power division input terminal (a3);

A first amplifier (M1), coupled between the third power division output terminal (b3) and the first output terminal (O1);

A second amplifier (P1) coupled between the fourth power division output terminal (b4) and the second output terminal (O2);

A third amplifier (M2), coupled between the fifth power division output terminal (b5) and the third output terminal (O3);

The fourth amplifier (P2) is coupled between the sixth power division output terminal (b6) and the fourth output terminal (O4).

2. The power amplifier chip according to claim 1, characterized in that the power amplifier chip also includes a first cascade power amplifier (PA1), and the first cascade power amplifier (PA1) is coupled in series with the first power divider (PS1).

3. The power amplifier chip according to claim 2 is characterized in that the first cascade power amplifier (PA1) includes a first sub-power amplifier (pa1) and a second sub-power amplifier (pa2), the first sub-power amplifier (pa1) is coupled between the first power division output terminal (b1) and the second power division input terminal (a2), and the second sub-power amplifier (pa2) is coupled between the second power division output terminal (b2) and the third power division input terminal (a3).

4. The power amplifier chip according to claim 2 or 3 is characterized in that the power amplifier chip also includes a second cascade power amplifier (PA2), and the second cascade power amplifier (PA2) is coupled between the radio frequency input terminal (RFI) and the first power divider input terminal (a1).

5. The power amplifier chip according to any one of claims 1 to 4, characterized in that the phase difference between the first power division output terminal (b1) and the second power division output terminal (b2) is 60° to 120° or -60° to -120°.

6. The power amplifier chip according to any one of claims 1 to 5, characterized in that:

The first power divider (PS1) further comprises a seventh power divider output terminal (b7), wherein the seventh power divider output terminal (b7) is coupled to a reference ground voltage terminal (GND);

and/or,

The second power divider (PS2) further comprises an eighth power divider output terminal (b8), wherein the eighth power divider output terminal (b8) is coupled to a reference ground voltage terminal (GND);

and/or,

The third power divider (PS3) further comprises a ninth power divider output terminal (b9), and the ninth power divider output terminal (b9) is coupled to the reference ground voltage terminal (GND).

7. A power amplifier module, characterized in that it comprises a power amplifier chip and a substrate, wherein the power amplifier chip is arranged on the substrate, and the power amplifier chip comprises the power amplifier chip according to any one of claims 1 to 6.

8. The power amplifier module according to claim 7, characterized in that the power amplifier module further comprises a first impedance matching network (W1), a second impedance matching network (W2), a third impedance matching network (W3), a fourth impedance matching network (W4), an impedance converter (U), a first combining point (Q1), a second combining point (Q2), a third combining point (Q3) and a radio frequency output terminal (RFO);

The first impedance matching network (W1) is coupled between the first output terminal (O1) and the first junction point (Q1);

The second impedance matching network (W2) is coupled between the second output terminal (O2) and the first junction point (Q1);

The third impedance matching network (W3) is coupled between the third output terminal (O3) and the second junction point (Q2);

The fourth impedance matching network (W4) is coupled between the fourth output terminal (O4) and the second junction point (Q2);

The impedance converter (U) is coupled between the first combining point (Q1) and the third combining point (Q3), the second combining point (Q2) is coupled to the third combining point (Q3), and the third combining point (Q3) is coupled to the radio frequency output terminal (RFO).

9. The power amplifier module according to claim 8 is characterized in that the power amplifier module also includes a fifth impedance matching network (W5), and the fifth impedance matching network (W5) is coupled between the third combining point (Q3) and the radio frequency output terminal (RFO).

10. The power amplifier module according to claim 8 or 9, characterized in that:

The first impedance matching network (W1) includes a first inductor (L1), and the second impedance matching network (W2) includes a first capacitor (C1);

and/or;

The third impedance matching network (W3) includes a second inductor (L2), and the fourth impedance matching network (W4) includes a second capacitor (C2).

11. The power amplifier module according to claim 10, characterized in that:

The value of the first inductor (L1) and/or the second inductor (L2) is 0.1NH-2NH;

and/or,

The value of the first capacitor (C1) and/or the second capacitor (C2) is 0.2PF-5PF.

12. The power amplifier module according to any one of claims 8 to 11, characterized in that the second combining point (Q2) and the third combining point (Q3) are coupled by routing, or the second combining point (Q2) and the third combining point (Q3) coincide with each other.

13. The power amplifier module according to any one of claims 8 to 12, characterized in that the phase difference between the third combining point (Q3) and the first combining point (Q1) is 60° to 120° or -60° to -120°.

14. The power amplifier module according to any one of claims 8 to 13, characterized in that the impedance converter (U) comprises a third inductor (L3), a fourth inductor (L4) and a third capacitor (C3);

The third inductor (L3) and the fourth inductor (L4) are connected in series between the first junction point (Q1) and the third junction point (Q3); one end of the third capacitor (C3) is coupled to the reference ground voltage terminal (GND), and the other end is coupled between the third inductor (L3) and the fourth inductor (L4).

15. The power amplifier module according to any one of claims 8 to 14, characterized in that the substrate comprises a first area and a second area, the power amplifier chip is located in the first area, and at least one of the first impedance matching network (W1), the second impedance matching network (W2), the third impedance matching network (W3), the fourth impedance matching network (W4) and the impedance converter (U) is located in the second area.

16. A power amplifier circuit, comprising:

A radio frequency input terminal (RFI), a radio frequency output terminal (RFO), a first power divider (PS1), a first Doherty circuit (DT1), a second Doherty circuit (DT2), an impedance converter (U), a first combining point (Q1), a second combining point (Q2), and a third combining point (Q3);

A first power divider (PS1), comprising a first power divider input terminal (a1), a first power divider output terminal (b1) and a second power divider output terminal (b2); the first power divider input terminal (a1) is coupled to the radio frequency input terminal (RFI);

The first Doherty circuit (DT1) is coupled between the first power division output terminal (b1) and the first combining point (Q1);

The second Doherty circuit (DT2) is coupled between the second power division output terminal (b2) and the second combining point (Q2);

17. The power amplifier circuit according to claim 16, characterized in that the first Doherty circuit (DT1) comprises a second power divider (PS2), a first amplifier (M1), a second amplifier (P1), a first impedance matching network (W1) and a second impedance matching network (W2);

The second power divider (PS2) comprises a second power divider input terminal (a2), a third power divider output terminal (b3) and a fourth power divider output terminal (b4); the second power divider input terminal (a2) is coupled to the first power divider output terminal (b1), the third power divider output terminal (b3) is coupled to the first amplifier (M1), and the fourth power divider output terminal (b4) is coupled to the second amplifier (P1);

The first impedance matching network (W1) is coupled between the output end of the first amplifier (M1) and the first junction (Q1);

The second impedance matching network (W2) is coupled between the output end of the second amplifier (P1) and the first combining point (Q1).

18. The power amplifier circuit according to claim 16 or 17, characterized in that the second Doherty circuit (DT2) comprises a third power divider (PS3), a third amplifier (M2), a fourth amplifier (P2), a third impedance matching network (W3) and a fourth impedance matching network (W4);

The third power divider (PS3) comprises a third power divider input terminal (a3), a fifth power divider output terminal (b5) and a sixth power divider output terminal (b6); the third power divider input terminal (a3) is coupled to the second power divider output terminal (b2), the fifth power divider output terminal (b5) is coupled to the third amplifier (M2), and the sixth power divider output terminal (b6) is coupled to the fourth amplifier (P2);

The third impedance matching network (W3) is coupled between the output end of the third amplifier (M2) and the second junction (Q2);

The fourth impedance matching network (W4) is coupled between the output end of the fourth amplifier (P2) and the second combining point (Q2).

19. The power amplifier circuit according to any one of claims 16-18 is characterized in that the power amplifier circuit also includes a fifth impedance matching network (W5), and the fifth impedance matching network (W5) is coupled between the third junction (Q3) and the radio frequency output terminal (RFO).

20. The power amplifier circuit according to any one of claims 16-19, characterized in that the second combining point (Q2) and the third combining point (Q3) are coupled by routing, or the second combining point (Q2) and the third combining point (Q3) coincide with each other.

21. The power amplifier circuit according to any one of claims 16 to 20, characterized in that a phase difference between the third combining point (Q3) and the first combining point (Q1) is 60° to 120° or -60° to -120°.

22. The power amplifier circuit according to any one of claims 16 to 21, characterized in that the impedance converter (U) comprises a third inductor (L3), a fourth inductor (L4) and a third capacitor (C3);

23. The power amplifier circuit according to any one of claims 16 to 22, characterized in that the power amplifier circuit further comprises a first cascade power amplifier (PA1), and the first cascade power amplifier (PA1) is coupled in series with the first power divider (PS1).

24. The power amplifier circuit according to claim 23 is characterized in that the first cascade power amplifier (PA1) includes a first sub-power amplifier (pa1) and a second sub-power amplifier (pa2), the first sub-power amplifier (pa1) is coupled between the first power divider output terminal (b1) and the first Doherty circuit (DT1), and the second sub-power amplifier (pa2) is coupled between the second power divider output terminal (b2) and the second Doherty circuit (DT2).

25. The power amplifier circuit according to claim 23 or 24 is characterized in that the power amplifier circuit also includes a second cascade power amplifier (PA2), and the second cascade power amplifier (PA2) is coupled between the radio frequency input terminal (RFI) and the first power divider input terminal (a1).

26. The power amplifier circuit according to claim 18, characterized in that

and/or,

27. A radio frequency front-end module, characterized in that it comprises: a filter and a power amplifier circuit; the power amplifier circuit comprises the power amplifier circuit according to any one of claims 16 to 26;

A radio frequency output (RFO) of the power amplifier circuit is coupled to an input of the filter.

28. A communication device, characterized in that it comprises the radio frequency front-end module and the antenna according to claim 27, wherein the antenna is coupled to the radio frequency front-end module.