CN118676017B - Testing and preparing method, testing structure and preparing method of superconducting quantum chip - Google Patents
Testing and preparing method, testing structure and preparing method of superconducting quantum chip Download PDFInfo
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- CN118676017B CN118676017B CN202410782257.0A CN202410782257A CN118676017B CN 118676017 B CN118676017 B CN 118676017B CN 202410782257 A CN202410782257 A CN 202410782257A CN 118676017 B CN118676017 B CN 118676017B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
本发明适用于超导量子技术领域，尤其涉及一种超导量子芯片的测试和制备方法、测试结构及制备方法。测试方法包括：提供超导量子芯片；将导电胶覆盖在超导量子芯片边缘四周或者局部的金属导电膜上，且导电胶与若干约瑟夫森结不接触；通过测试设备对覆盖导电胶的超导量子芯片进行约瑟夫森结的电阻测试，测试设备为覆盖导电胶的超导量子芯片提供电压，测试设备的第一端与某个约瑟夫森结的结区上表面接触，且该端与该约瑟夫森结的结区电连接，测试设备的第二端与导电胶电连接。本发明实现了低电流，高精度测试，电流级别在pA甚至fA级别，解决了约瑟夫森结测试中易损坏或击穿结的问题。
The present invention is applicable to the field of superconducting quantum technology, and in particular, relates to a test and preparation method, test structure and preparation method of a superconducting quantum chip. The test method comprises: providing a superconducting quantum chip; covering the metal conductive film around the edge of the superconducting quantum chip or locally with conductive glue, and the conductive glue is not in contact with a number of Josephson junctions; performing a resistance test of the Josephson junction on the superconducting quantum chip covered with conductive glue by a test device, the test device provides voltage to the superconducting quantum chip covered with conductive glue, the first end of the test device contacts the upper surface of the junction region of a Josephson junction, and the end is electrically connected to the junction region of the Josephson junction, and the second end of the test device is electrically connected to the conductive glue. The present invention realizes low current and high precision testing, and the current level is at the pA or even fA level, which solves the problem of easily damaged or broken junctions in Josephson junction testing.
Description
Technical Field
The invention is suitable for the technical field of superconducting quanta, and particularly relates to a testing and preparing method, a testing structure and a preparing method of a superconducting quanta chip.
Background
Josephson junctions are key structures of superconducting qubits, relating to the computational performance of superconducting quantum chips, or even all-solid-state superconducting quantum computers. In order to ensure the performance of the superconducting quantum chip, the frequency parameter of superconducting quantum bits must be strictly controlled, and the characterization of the room temperature resistance of the Josephson junction is an important means of reaction frequency parameter, so that accurate measurement of the room temperature resistance of the Josephson junction is required.
At present, the resistance measurement of the superconducting quantum chip mostly adopts a mode of leading out the Pad structures at two ends of a probe-pricking device to carry out electric contact to measure the resistance, but the probe test mode is easy to damage even break down the Josephson junction due to larger current.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a testing and preparing method, a testing structure and a preparing method of a superconducting quantum chip, so as to solve the problem that the conventional detection process is easy to damage a Josephson junction.
The application provides a testing method of a superconducting quantum chip, which comprises the following steps:
providing a superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions growing on the metal conductive film;
covering conductive adhesive on the periphery of the edge of the superconducting quantum chip or on a partial metal conductive film, wherein the conductive adhesive is not contacted with a plurality of Josephson junctions;
And carrying out resistance test on the Josephson junction by using a testing device, wherein the testing device provides voltage for the conductive glue covered superconducting quantum chip, a first end of the testing device is contacted with the upper surface of a junction region of a certain Josephson junction, the end is electrically connected with the junction region of the Josephson junction, and a second end of the testing device is electrically connected with the conductive glue.
In addition, the application also provides a preparation method of the superconducting quantum chip, which comprises the testing method of the superconducting quantum chip, and after the testing is finished, the conductive adhesive is removed by using the adhesive removing agent to obtain the superconducting quantum chip.
Compared with the prior art, the method for testing and preparing the superconducting quantum chip has the advantages that the superconducting quantum chip is subjected to conductive treatment before testing, low-current and high-precision testing is realized, the current level is at the pA level or even the fA level, the problem of damage or junction breakdown in the Josephson junction testing is solved, the damage in the testing process is reduced, and the product yield and the production efficiency are improved. Meanwhile, if the periphery of the conductive adhesive is covered, the electrical environment is balanced, and the problem of non-uniform global Josephson junction test in the preparation process of a large-scale superconducting quantum bit chip is avoided.
Further, the process of covering the periphery or part of the edge of the superconducting quantum chip with the conductive adhesive comprises the following steps:
providing a metal gasket;
Dropping conductive adhesive on the upper surface of the metal gasket;
And pressing the back surface of the superconducting quantum chip on the conductive adhesive, so that the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the periphery or local metal conductive film of the edge of the superconducting quantum chip.
Further, the width of the conductive adhesive covering the metal conductive film is more than or equal to 1mm.
Further, the testing equipment is an atomic force microscope, a first end of the atomic force microscope is a conductive probe, a second end of the atomic force microscope is an electrified magnetic attraction point of the sample carrier, and the resistance of the Josephson junction is determined through testing bias voltage and a surface current value.
Further, the conductive adhesive is a mixed solution of silver paste and photoresist, wherein the mass ratio of the silver paste to the photoresist is 1:1, or the types of the conductive adhesive are AR-PC5090 and AR-PC5091.
Further, the open-circuit defect of the Josephson junction can be determined according to a surface height diagram, a Z-axis sensing diagram and an amplitude diagram output by the atomic force microscope.
In addition, the application also provides a test structure of the superconducting quantum chip, which comprises the following steps:
A superconducting quantum chip comprising a metal conductive film and a plurality of josephson junctions grown on the metal conductive film;
The conductive adhesive is covered on the periphery of the edge of the superconducting quantum chip or a partial metal conductive film and is not contacted with a plurality of Josephson junctions;
The upper surface of the junction region of the Josephson junction is used for being contacted with a first end of test equipment, the end is electrically connected with the junction region of the Josephson junction, the conductive adhesive is used for being electrically connected with a second end of the test equipment, and the test equipment provides voltage for the superconducting quantum chip covered by the conductive adhesive.
Further, the superconducting quantum chip further comprises a metal gasket, wherein the upper surface of the metal gasket is fixed with the back surface of the superconducting quantum chip covered with the conductive adhesive through the conductive adhesive.
In addition, the application also provides a preparation method of the test structure of the superconducting quantum chip, which comprises the following steps:
providing a superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions growing on the metal conductive film;
covering conductive adhesive on the periphery of the edge of the superconducting quantum chip or on a partial metal conductive film, wherein the conductive adhesive is not contacted with a plurality of Josephson junctions;
The upper surface of the junction region of the Josephson junction is used for being contacted with a first end of test equipment, the end is electrically connected with the junction region of the Josephson junction, the conductive adhesive is used for being electrically connected with a second end of the test equipment, and the test equipment provides voltage for the superconducting quantum chip covered by the conductive adhesive.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of testing a superconducting quantum chip of the present invention;
FIG. 2 is a cross-sectional view of a superconducting quantum chip of the present invention;
FIG. 3 is a flow chart of the fabrication of the test structure of the superconducting quantum chip of the present invention;
FIG. 4 is a cross-sectional block diagram of a test structure of a superconducting quantum chip of the present invention;
FIG. 5 is a schematic illustration of placement of a test structure of a superconducting quantum chip of the present invention;
FIG. 6 is a test connection diagram of a test structure of a superconducting quantum chip of the present invention;
FIG. 7a is a surface elevation plot in test data of the present invention;
FIG. 7b is a graph of Z-axis sensing in test data of the present invention;
FIG. 7c is a surface current plot in test data of the present invention;
FIG. 7d is a graph of amplitude in test data for the present invention;
fig. 8a is a surface current diagram of a josephson junction according to the invention;
Fig. 8b is a graph of the current at a particular location of the josephson junction of the present invention;
fig. 9a is a surface elevation view of a josephson junction of the present invention;
fig. 9b is a high profile of a particular location of the josephson junction according to the invention;
fig. 10a is a surface elevation view of the josephson junction of the present invention under normal conditions;
fig. 10b is a Z-axis sense plot of the josephson junction of the invention under normal conditions;
Fig. 10c is a graph of the amplitude of the josephson junction of the invention under normal conditions;
fig. 11a is a surface elevation view of the josephson junction of the present invention in the case of a break defect;
fig. 11b is a Z-axis sense plot of the present invention with josephson junction break defects;
Fig. 11c is an amplitude plot in the case of josephson junction break defects of the present invention;
in the figure, 1 is a metal gasket, 2 is a conductive adhesive, 3 is a superconducting quantum chip, 31 is a metal conductive film, 32 is a Josephson junction, 33 is a substrate, 4 is a conductive probe, 5 is a sample carrier, 6 is a dropper, 7 is a test structure, 8 is a voltage output circuit, and 9 is a voltage input circuit.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
It should be understood that the sequence numbers of the steps in the following embodiments do not mean the order of execution, and the execution order of the processes should be determined by the functions and the internal logic, and should not be construed as limiting the implementation process of the embodiments of the present invention.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Test method embodiment of superconducting quantum chip:
In order to avoid the damage to the Josephson junction caused by the current and the breakdown of the Josephson junction, the invention covers the conductive adhesive on the metal conductive film in the superconducting quantum chip, and the conductive adhesive is not contacted with the Josephson junctions, so that one of the two ends of the testing device is electrically connected with the Josephson junction, and the other end is electrically connected with the conductive adhesive, thereby realizing the resistance detection of the Josephson junction.
Specifically, as shown in fig. 1, the testing method of the superconducting quantum chip comprises the following steps:
1) A superconducting quantum chip is provided.
The structure of the superconducting quantum chip is shown in fig. 2, and includes a substrate 33, a metal conductive film 31, and a plurality of josephson junctions 32, the plurality of josephson junctions 32 being grown on the metal conductive film 31. The structure of the superconducting quantum chip is 10mm by 10mm bare chip (die).
The metal conductive film 31 and the josephson junction 32 are not in a vertical structure relationship, but the metal conductive film 31 is a layer basis, the josephson junction 32 is grown on the metal conductive film 31, and the metal conductive film 31 is arranged around the josephson junction 32.
2) And preparing a test structure of the superconducting quantum chip.
The process of preparing the test structure of the superconducting quantum chip is shown in fig. 3, and comprises the following steps:
S201. providing a metal gasket 1.
S202, dripping conductive adhesive 2 on the upper surface of the metal gasket 1 by using a dropper 6, wherein the conductive adhesive 2 is a mixed solution of silver paste and photoresist, the mass ratio of the silver paste to the photoresist is 1:1, for example, particles (micron-diameter silver particles) of high-purity (99.99%) metal silver are added into the photoresist S1813 in a mass ratio of 1:1, and stirring is carried out uniformly to prepare the conductive adhesive 2;
or the conductive adhesive 2 is of the types AR-PC5090 and AR-PC5091.
And S203, pressing the back surface of the superconducting quantum chip 3 on the conductive adhesive 2, so that the conductive adhesive 2 diffuses to the front surface of the superconducting quantum chip 3 and covers the periphery or local metal conductive film 31 of the edge of the superconducting quantum chip 3.
S204, drying by using a heating plate.
The drying temperature is 80 ℃ and the drying time is 1h.
Finally, as shown in fig. 4, the section of the test structure of the obtained superconducting quantum chip 3 is that the conductive adhesive 2 is covered on the periphery or part (the periphery is covered to ensure the electrical uniformity during all the position tests, so as to ensure the same test precision) of the edge of the superconducting quantum chip 3, and the conductive adhesive 2 is not contacted with a plurality of josephson junctions 32. The width of the conductive adhesive 2 covering the metal conductive film 31 is not less than 1mm. The upper surface of the metal pad 1 is fixed with the back surface of the superconducting quantum chip 3 covered with the conductive paste 2 by the conductive paste 2, and it can be seen that the metal conductive film 31 is in conductive communication with the metal pad 1.
3) Parameters of an atomic force microscope were set.
The parameter setting process is as follows:
S301, selecting a conductive mode (ORCA) of an atomic force microscope, and installing a conductive Z-axis scanner and a conductive probe 4, wherein the type of the conductive probe 4 is ASYELEC.01-R2;
s302, shifting a carrier Bias selection knob at the rear side of an atomic force microscope carrier to a Bias position;
S303, before testing, a universal meter is used for testing the resistance value from a machine carrier (Holder) to a electrified magnetic attraction point of the sample carrier 5, the measured resistance value is input into a software interface to adjust Voltage offset (S. Voltage offset) until the Voltage offset is reset to zero, and the influence of resistance values of other components in a circuit is counteracted.
4) Test preparation.
The preparation process is as shown in fig. 5 and 6:
S401, sample injection, namely placing the test structure 7 of the superconducting quantum chip 3 prepared in the step 2) to an electrified magnetic attraction point (the electrified magnetic attraction point is arranged in the sample carrier 5 and is not shown in the drawing) of the sample carrier 5 of the atomic force microscope, and controlling the sample carrier 5 to enable the test structure 7 of the superconducting quantum chip 3 to be moved to the position right below the conductive probe 4.
S402, focusing and positioning, namely lowering the conductive probe 4 to about 1 mm on the upper surface of the test structure 7 of the prepared superconducting quantum chip 3, so that an atomic force microscope can focus and position the junction region of the Josephson junction 32.
S403, setting the test bias voltage to be 0-5V.
5) And (5) scanning and testing.
Specifically, the scanning is started, as shown in fig. 5, the atomic force microscope automatically descends the conductive probe 4 to the upper surface of the junction region of the josephson junction 32 of the test structure 7, and generates good atomic force contact with the upper surface, and the contact force between the conductive probe 4 of the atomic force microscope and the test structure 7 is weak atomic force, and the size is about 10 -8~10-11 N, so that nondestructive detection can be realized.
The test circuit is shown in fig. 6, and comprises a voltage input circuit 9 and a voltage output circuit 8, wherein the voltage input circuit 9 comprises a power supply V bias and a resistor R sample which are connected in series, one end of the voltage input circuit 9 is connected with the second end of the atomic force microscope, the other end of the voltage input circuit 9 is grounded Virtual group, the voltage output circuit 8 is a common signal amplifying circuit, the input end of the voltage output circuit 8 is connected with the first end of the atomic force microscope, and the output end of the voltage output circuit 8 is used for outputting a voltage signal V out. The first end of the atomic force microscope is a conductive probe 4, the second end of the atomic force microscope is an electrified magnetic attraction point of the sample carrier 5, the first end is in contact with the upper surface of the junction region of a certain Josephson junction 32, the first end is electrically connected with the junction region of the Josephson junction 32, the second end is electrically connected with a conductive adhesive 2 through a metal gasket 1, and the circuit is conducted after all connection, so that the measurement can be performed.
During testing, data such as surface current, morphology and the like of the junction region of the Josephson junction 32 can be observed in real time, and the testing bias voltage can be changed in real time according to the data so as to adjust the testing effect.
6) And (5) data analysis.
In the test, the test results such as the surface height map (height) shown in fig. 7a, the Z-axis sensor map (Z sensor) shown in fig. 7b, the current map (current) shown in fig. 7c, and the amplitude map (amplitude) shown in fig. 7d are output, and data analysis is performed by AsylumResearch software, so that the surface topography of the josephson junction 32 can be observed through the surface height map, the Z-axis sensor map, and the amplitude map, and the surface current distribution can be observed through the surface current map.
The specific data were analyzed as follows:
1. The resistance of the josephson junction 32 can be calculated and analysed from the surface current map in combination with the test bias data.
Fig. 8a is a surface current diagram of the josephson junction 32, fig. 8b is a current diagram of a specific position of the josephson junction 32, and the resistance is calculated by using an ohmic formula resistor r=v/I, V is a test bias voltage, I is a surface current in an AFM output data diagram, and the resistor R can be obtained by taking the surface current into the formula.
For example, the measured surface current at a point is 75 pA, at which time the applied test bias is 0.65 μV, brought into the ohmic formula, resulting in a junction resistance of 8666 Ω for the josephson junction 32 at that point.
2. The surface topography and surface relief of the josephson junction 32 can be analyzed by observation from the surface height map, the Z-axis sensor map and the amplitude map, from which the open defects of the josephson junction 32 are determined.
Fig. 9a is a surface elevation view of a josephson junction 32 and fig. 9b is a elevation view of a particular location of the josephson junction 32.
The break defect of the josephson junction 32 can be determined according to the surface height map, the Z-axis sensing map and the amplitude map, for example, fig. 10a is the surface height map of the josephson junction 32 in the normal condition, fig. 10b is the Z-axis sensing map of the josephson junction 32 in the normal condition, fig. 10c is the amplitude map of the josephson junction 32 in the normal condition, fig. 11a is the surface height map of the josephson junction 32 in the broken defect condition (fig. d), fig. 11b is the Z-axis sensing map of the josephson junction 32 in the broken defect condition (fig. e), and fig. 11c is the amplitude map of the josephson junction 32 in the broken defect condition (fig. f), as can be seen that the surface height map, the Z-axis sensing map and the amplitude map of the broken defect are significantly different from those of the conventional josephson junction 32.
3. The surface height and surface current distribution of the josephson junction 32 can be compared with each other and specific data can be read.
In the above embodiment, the resistance of the josephson junction 32 is tested by using an atomic force microscope, so that the microscopic characteristic characterization of the josephson junction 32 can be realized, the surface current distribution and the microscopic morphology graph can be simultaneously output, and the microscopic damage position of the dielectric layer can be positioned, thereby performing failure analysis, avoiding the step of characterizing the junction region surface morphology by means of SEM and the like after the test resistance is abnormal, and improving the product test efficiency. As another embodiment, a test device that performs only a resistance test may be used without performing detection of the surface topography.
In the above embodiment, in order to reduce the test current, the test structure 7 includes the metal pad 1, and of course, as other embodiments, it is only necessary to cover the conductive adhesive 2 around the edge of the superconducting quantum chip 3 or on the partial metal conductive film 31, and the conductive adhesive 2 does not contact with the josephson junctions 32, and the manufacturing process may also use the dropper 6 to directly drop on the front surface of the superconducting quantum chip 3.
In the above embodiment, in order to improve the conductive effect, the width of the conductive adhesive 2 covering the metal conductive film 31 is not less than 1mm, and as other embodiments, the width of the conductive adhesive 2 covering the metal conductive film 31 may be less than 1mm, but it is necessary to ensure that the conductive adhesive 2 overlaps the metal conductive film 31.
According to the invention, the superconducting quantum chip 3 is subjected to conductive treatment before testing, so that low-current and high-precision testing is realized, the current level is at pA or even fA level, the problem of damage or junction breakdown in the Josephson junction 32 testing is solved, the damage in the testing process is reduced, the product yield and the production efficiency are improved, and if conductive adhesive is covered on the periphery, the electrical environment is balanced, and the problem of uneven global Josephson junction 32 testing in the large-scale superconducting quantum bit chip preparation process is avoided when junction resistors at all positions of a continuous scanning chip are subjected to global testing. Meanwhile, the conductive adhesive 2 is water-soluble, can be conveniently removed by a common adhesive removing agent (deionized water and the like) at the later stage, has no influence on each position of a sample, and realizes nondestructive measurement of a chip.
Test structure embodiment of superconducting quantum chip:
A test structure of a superconducting quantum chip, comprising:
superconducting quantum chip 3, superconducting quantum chip 3 includes metal conductive film 31 and several josephson junctions 32 grown on metal conductive film 31;
and the conductive adhesive 2 is covered on the periphery of the edge of the superconducting quantum chip 3 or a partial metal conductive film 31, and the conductive adhesive 2 is not contacted with a plurality of Josephson junctions 32;
Wherein the upper surface of the junction region of the josephson junction 32 is adapted to be in contact with a first terminal of a test device, which terminal is electrically connected to the junction region of the josephson junction 32, and the conductive paste 2 is adapted to be electrically connected to a second terminal of the test device, which provides a voltage to the superconducting quantum chip 3 covered with the conductive paste 2.
Further comprises:
The upper surface of the metal gasket 1 and the back surface of the superconducting quantum chip 3 covered with the conductive adhesive 2 are fixed through the conductive adhesive 2.
The specific structure of the test structure 7 of the superconducting quantum chip 3 is described in detail in the above embodiment of the test method of the superconducting quantum chip, and will not be described in detail herein.
Test structure preparation method of superconducting quantum chip example:
the preparation method of the test structure of the superconducting quantum chip comprises the following steps:
providing a superconducting quantum chip 3, wherein the superconducting quantum chip 3 comprises a metal conductive film 31 and a plurality of Josephson junctions 32 grown on the metal conductive film 31;
Covering the periphery of the edge of the superconducting quantum chip 3 or a local metal conductive film 31 with conductive adhesive 2, wherein the conductive adhesive 2 is not contacted with a plurality of Josephson junctions 32;
Wherein the upper surface of the junction region of the josephson junction 32 is adapted to be in contact with a first terminal of a test device, which terminal is electrically connected to the junction region of the josephson junction 32, and the conductive paste 2 is adapted to be electrically connected to a second terminal of the test device, which provides a voltage to the superconducting quantum chip 3 covered with the conductive paste 2.
The method for preparing the test structure of the superconducting quantum chip is described in detail in the above embodiments of the test method of the superconducting quantum chip, and will not be described in detail herein.
Preparation method of superconducting quantum chip example:
the preparation method of the superconducting quantum chip comprises a testing method of the superconducting quantum chip, and after the testing is completed, the conductive adhesive 2 is removed by using an adhesive removing agent to obtain the superconducting quantum chip 3.
The method for testing the superconducting quantum chip is described in detail in the embodiment of the method for testing the superconducting quantum chip, and will not be described in detail herein.
The foregoing embodiments are merely for illustrating the technical solution of the present invention, but not for limiting the same, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solution described in the foregoing embodiments may be modified or substituted for some of the technical features thereof, and that these modifications or substitutions should not depart from the spirit and scope of the technical solution of the embodiments of the present invention and should be included in the protection scope of the present invention.
Claims (8)
1. The testing method of the superconducting quantum chip is characterized by comprising the following steps of:
providing a superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions growing on the metal conductive film;
Covering conductive adhesive on the metal conductive film around the edge of the superconducting quantum chip or covering the conductive adhesive on the metal conductive film on the local edge of the superconducting quantum chip, wherein the conductive adhesive is not contacted with a plurality of Josephson junctions;
Carrying out resistance test on the superconducting quantum chip covered with the conductive adhesive by using test equipment, wherein the test equipment provides voltage for the superconducting quantum chip covered with the conductive adhesive, a first end of the test equipment is contacted with the upper surface of a junction region of a certain Josephson junction, the end is electrically connected with the junction region of the Josephson junction, and a second end of the test equipment is electrically connected with the conductive adhesive;
the process of covering the periphery of the edge of the superconducting quantum chip with the conductive adhesive or covering the local periphery of the superconducting quantum chip with the conductive adhesive comprises the following steps:
providing a metal gasket;
Dropping conductive adhesive on the upper surface of the metal gasket;
And pressing the back surface of the superconducting quantum chip on the conductive adhesive, so that the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film on the local edge of the superconducting quantum chip.
2. The method for testing a superconducting quantum chip according to claim 1, wherein the width of the conductive adhesive covered metal conductive film is not less than 1mm.
3. The method according to claim 1, wherein the testing device is an atomic force microscope, a first end of the atomic force microscope is a conductive probe, a second end of the atomic force microscope is an electrified magnetic attraction point of the sample carrier, and the resistance of the josephson junction is determined by testing the bias voltage and the surface current value.
4. The method for testing the superconducting quantum chip according to claim 1, wherein the conductive adhesive is a mixed solution of silver paste and photoresist, the mass ratio of the silver paste to the photoresist is 1:1, or the types of the conductive adhesives are AR-PC5090 and AR-PC5091.
5. The method for testing a superconducting quantum chip of claim 3, wherein the broken defects of the josephson junction are determined based on a surface height map, a Z-axis sensor map, and an amplitude map output from an atomic force microscope.
6. A test structure of a superconducting quantum chip, comprising:
A superconducting quantum chip comprising a metal conductive film and a plurality of josephson junctions grown on the metal conductive film;
The conductive adhesive is covered on the metal conductive film around the edge of the superconducting quantum chip or on the metal conductive film at the local part of the edge of the superconducting quantum chip, and the conductive adhesive is not contacted with a plurality of Josephson junctions;
The upper surface of the junction region of the Josephson junction is used for being contacted with a first end of test equipment, and the end is electrically connected with the junction region of the Josephson junction;
The superconducting quantum chip comprises a superconducting quantum chip, a metal gasket, a conductive adhesive, a conductive film, a conductive adhesive and a conductive adhesive, wherein the conductive adhesive is dripped on the upper surface of the metal gasket, the back surface of the superconducting quantum chip is pressed on the conductive adhesive, so that the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film on the local edge of the superconducting quantum chip, and the upper surface of the metal gasket and the back surface of the superconducting quantum chip covered with the conductive adhesive are fixed through the conductive adhesive.
7. The preparation method of the test structure of the superconducting quantum chip is characterized by comprising the following steps of:
providing a superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions growing on the metal conductive film;
Covering conductive adhesive on the metal conductive film around the edge of the superconducting quantum chip or covering the conductive adhesive on the metal conductive film on the local edge of the superconducting quantum chip, wherein the conductive adhesive is not contacted with a plurality of Josephson junctions;
The upper surface of the junction region of the Josephson junction is used for being contacted with a first end of test equipment, and the end is electrically connected with the junction region of the Josephson junction;
the process of covering the periphery of the edge of the superconducting quantum chip with the conductive adhesive or covering the local periphery of the superconducting quantum chip with the conductive adhesive comprises the following steps:
providing a metal gasket;
Dropping conductive adhesive on the upper surface of the metal gasket;
And pressing the back surface of the superconducting quantum chip on the conductive adhesive, so that the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive adhesive is diffused to the front surface of the superconducting quantum chip and covers the metal conductive film on the local edge of the superconducting quantum chip.
8. A method for manufacturing a superconducting quantum chip, comprising the method for testing a superconducting quantum chip according to any one of claims 1 to 5, wherein after the testing, the conductive adhesive is removed by using an adhesive remover to obtain the superconducting quantum chip.
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| CN111554798A (en) * | 2020-04-30 | 2020-08-18 | 合肥本源量子计算科技有限责任公司 | A quantum chip test structure, its preparation method and test method |
| CN115697027A (en) * | 2022-10-20 | 2023-02-03 | 合肥本源量子计算科技有限责任公司 | Preparation method of Josephson junction, quantum circuit and quantum chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11581472B2 (en) * | 2019-08-07 | 2023-02-14 | International Business Machines Corporation | Superconductor-semiconductor Josephson junction |
| CN111505478A (en) * | 2020-04-30 | 2020-08-07 | 合肥本源量子计算科技有限责任公司 | Core superconducting Josephson junction testing device and testing method |
| CN112782557B (en) * | 2020-12-29 | 2021-09-07 | 合肥本源量子计算科技有限责任公司 | A quantum chip test structure and its preparation method and test method |
| CN117355205A (en) * | 2022-06-23 | 2024-01-05 | 腾讯科技（深圳）有限公司 | Josephson junction preparation method and system |
| CN117979812A (en) * | 2022-10-21 | 2024-05-03 | 腾讯科技（深圳）有限公司 | Chip preparation method, system and chip |
| CN116759413A (en) * | 2023-06-29 | 2023-09-15 | 本源量子计算科技（合肥）股份有限公司 | Test structure, method for manufacturing quantum bit and quantum chip |
| CN116960017A (en) * | 2023-09-20 | 2023-10-27 | 阿尔伯达(苏州)科技有限公司 | Conductive adhesive test pin card and manufacturing method applied to conductive adhesive test pin card |
| CN117542839A (en) * | 2023-10-25 | 2024-02-09 | 本源量子计算科技（合肥）股份有限公司 | Method for producing superconducting qubits, test junction, and production and use thereof |
| CN117829303A (en) * | 2023-12-26 | 2024-04-05 | 本源量子计算科技（合肥）股份有限公司 | Layout structure, quantum circuit and method for manufacturing quantum circuit and method for extracting manufacturing parameters |
| CN118055686A (en) * | 2024-02-27 | 2024-05-17 | 合肥国家实验室 | Resistance regulating and controlling method and device for superconductive quantum chip Josephson junction resistance |
| CN118201468B (en) * | 2024-05-20 | 2024-08-20 | 天津大学 | Quantum chip and preparation method thereof |
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| CN115697027A (en) * | 2022-10-20 | 2023-02-03 | 合肥本源量子计算科技有限责任公司 | Preparation method of Josephson junction, quantum circuit and quantum chip |
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