CN118672859A - Test method and device of computing unit, electronic equipment and storage medium - Google Patents

Abstract

The present disclosure provides a method for testing a computing unit, which relates to the field of artificial intelligence technology, and in particular to the field of chips, deep learning and testing technology. The specific implementation scheme is: according to the first trigonometric function value sequence, the second trigonometric function value sequence and the third trigonometric function value sequence, the target computing unit is used to obtain the first matrix, the second matrix and the reference matrix respectively, wherein the first vector of the first matrix is obtained by circularly moving the first trigonometric function value sequence along the first direction by the first number of movement bits, and the second vector of the second matrix is obtained by circularly moving the second trigonometric function value sequence along the second direction by the second number of movement bits; the computing unit to be tested is used to multiply the first matrix and the second matrix to obtain the result matrix to be tested; and according to the difference between the result matrix to be tested and the reference matrix, the accuracy test result of the computing unit to be tested is determined. The present disclosure also provides a testing device, an electronic device and a storage medium for a computing unit.

Description

Computing unit testing method, device, electronic device and storage medium

Technical Field

The present disclosure relates to the field of artificial intelligence technology, and in particular to the field of chips, deep learning and testing technology. More specifically, the present disclosure provides a testing method, device, electronic device and storage medium for a computing unit.

Background Art

With the development of artificial intelligence technology, the application of artificial intelligence chips continues to increase.

Summary of the invention

The present disclosure provides a computing unit testing method, apparatus, device and storage medium.

According to one aspect of the present disclosure, a testing method for a computing unit is provided, the method comprising: obtaining a first matrix, a second matrix and a reference matrix respectively using a target computing unit according to a first trigonometric function value sequence, a second trigonometric function value sequence and a third trigonometric function value sequence, wherein the first matrix includes at least one first vector, the first vector is obtained by circularly shifting the first trigonometric function value sequence along a first direction by a first shifting bit number, the second matrix includes at least one second vector, the second vector is obtained by circularly shifting the second trigonometric function value sequence along a second direction by a second shifting bit number, and a phase value of the third trigonometric function value sequence is obtained according to a difference between a phase value of the first trigonometric function value sequence and a phase value of the second trigonometric function value sequence; multiplying the first matrix and the second matrix by the computing unit to be tested to obtain a result matrix to be tested; and determining the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix.

According to another aspect of the present disclosure, a testing device for a computing unit is provided, the device comprising: a target computing unit, configured to obtain a first matrix, a second matrix and a reference matrix according to a first trigonometric function value sequence, a second trigonometric function value sequence and a third trigonometric function value sequence, respectively, wherein the first matrix comprises at least one first vector, the first vector is obtained by circularly shifting the first trigonometric function value sequence along a first direction by a first shifting bit number, the second matrix comprises at least one second vector, the second vector is obtained by circularly shifting the second trigonometric function value sequence along a second direction by a second shifting bit number, and a phase value of the third trigonometric function value sequence is obtained according to a difference between a phase value of the first trigonometric function value sequence and a phase value of the second trigonometric function value sequence; a computing unit to be tested, configured to multiply the first matrix and the second matrix to obtain a result matrix to be tested; and the target computing unit is further configured to determine an accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix.

According to another aspect of the present disclosure, an electronic device is provided, comprising the device provided by the present disclosure.

According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

FIG1 is a flow chart of a method for testing a computing unit according to an embodiment of the present disclosure;

FIG2 is a schematic diagram of a first matrix, a second matrix, and a reference matrix according to an embodiment of the present disclosure;

FIG3 is a block diagram of a test device for a computing unit according to an embodiment of the present disclosure;

FIG4 is a block diagram of an electronic device according to an embodiment of the present disclosure; and

FIG. 5 is a block diagram of an electronic device to which a method for testing a computing unit may be applied according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

In the fields of scientific computing and deep learning, models can include multiple operations involving linear calculations. These operations include general matrix to matrix multiplication (GEMM) operations and convolution (conv) operations. The storage resources of artificial intelligence chips are constantly increasing. The size (shape) of the data involved in these operations is also getting bigger and bigger. Taking the general matrix multiplication operation as an example, the operation involves a first matrix and a second matrix. The first matrix can be an M×K matrix, and the second matrix can be a K×N matrix. The computational complexity of the general matrix multiplication operation can be O(n3), and the corresponding computational time is also O(n3).

During the software or hardware development process, a large number of accuracy tests can be performed on linear computing operations to determine the accuracy of the AI chip or operator.

In some embodiments, the test data (e.g., the first matrix and the second matrix) can be generated by a central computing unit (CPU), and the central computing unit calculates a benchmark (golden) result. Next, the calculation result calculated by the artificial intelligence chip based on the test data is used. The calculation result is compared with the benchmark result to determine the correctness of the operation execution. The calculation time of the artificial intelligence chip is generally short, but the data generation time and calculation time of the central computing unit are both long.

For example, the central computing unit can generate a set of M×K random numbers with a numerical range of (-1.0f, 1.0f) as the first matrix, or a set of N×K random numbers with a numerical range of (-1.0f, 1.0f) as the second matrix. The central computing unit performs a matrix multiplication operation based on the first matrix and the transposed second matrix to obtain a benchmark result. The benchmark result can be an M×N matrix. The artificial intelligence chip performs a matrix multiplication operation based on the first matrix and the second matrix to obtain a matrix of the test result. The matrix of the test result can also be an M×N matrix. The absolute error and/or relative error between each value in the matrix of the test result and the corresponding value in the benchmark result can be calculated. The absolute error and/or relative error is compared with the error threshold to obtain a comparison result. It can be understood that the error threshold is related to the number of columns of the first matrix or the number of rows of the second matrix (K). If K is different, the error threshold needs to be reconfigured. In addition, in the process of generating the first matrix and the second matrix, a large number of random number generation operations need to be performed, and a large number of random numbers need to be written into storage separately, which will take a lot of time. In addition, in the process of performing matrix multiplication operations, the central computing unit is required to perform a large number of calculations and memory access operations, and as the calculation scale grows, the time consumption will also increase.

For example, the first matrix and the second matrix can be generated in advance using a central computing unit, and the benchmark result matrix can be calculated in advance, and the first matrix, the second matrix and the benchmark result matrix can be stored in the corresponding storage unit. During the test, these stored matrix data can be loaded, and the test result matrix can be calculated using an artificial intelligence chip. The absolute error and/or relative error between each value in the test result matrix and the corresponding value in the benchmark result can also be calculated. The absolute error and/or relative error can be compared with the error threshold to obtain a comparison result. It can be understood that the error threshold is still related to the number of columns of the first matrix or the number of rows (K) of the second matrix. If K is different, the error threshold needs to be reconfigured. In addition, storing the first matrix, the second matrix and the benchmark matrix requires a large amount of storage resources. If the matrix size increases or the number of test cases increases, the storage resource overhead will increase further. In addition, when the first matrix and the second matrix are generated in advance, it is difficult to implement random testing, and only some fixed-size matrices can be used for testing, resulting in low test coverage.

Therefore, in order to effectively improve the testing efficiency, the present disclosure provides a testing method for a computing unit, which will be described below.

FIG. 1 is a schematic flowchart of a method for testing a computing unit according to an embodiment of the present disclosure.

As shown in FIG. 1 , the method 100 may include operations S110 to S130 .

In operation S110, a first matrix, a second matrix, and a reference matrix are obtained respectively using a target computing unit according to the first trigonometric function value sequence, the second trigonometric function value sequence, and the third trigonometric function value sequence.

In the embodiment of the present disclosure, the target computing unit may be the above-mentioned central computing unit, or may be a computing unit of a host.

In an embodiment of the present disclosure, the first matrix may include at least one first vector. The first vector may be obtained by cyclically shifting a first trigonometric function value sequence along a first direction by a first shifting bit number. For example, the first trigonometric function value may be a first sine value. The first shifting bit number may be a value greater than or equal to 0.

In the disclosed embodiment, the second matrix may include at least one second vector. The second vector may be obtained by cyclically shifting the second trigonometric function value sequence along the second direction by a second shifting number of bits. For example, the second trigonometric function value may be a second sine value. The second shifting number of bits may be a value greater than or equal to 0.

In the embodiment of the present disclosure, the first direction may be the same as the second direction, or may be different from the second direction.

In the disclosed embodiment, the circular shift may be to change the order of two subsequences in the sequence. For example, taking the sequence "1,2,3,4" as an example, if it is shifted to the right by 2 bits, the sequence "3,4,1,2" can be obtained. The order between the subsequence "1,2" and the subsequence "3,4" is adjusted. Still taking the sequence "1,2,3,4" as an example, if it is shifted to the left by 1 bit, the sequence "2,3,4,1" can be obtained. The order between the subsequence "2,3,4" and the subsequence "1" is adjusted.

In the disclosed embodiment, the phase value of the third trigonometric function value sequence is obtained based on the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value. For example, the first trigonometric function value sequence may include K first trigonometric function values. The second trigonometric function value sequence may include K second trigonometric function values. The third trigonometric function value sequence may include K third trigonometric function values. Each trigonometric function value may be obtained by processing a phase value using a trigonometric function. The difference between the phase value of the first trigonometric function value and the phase value of the corresponding second trigonometric function value may be determined. Based on the difference in the phase values, K phase values may be determined. It can be understood that the product of two trigonometric function values can be converted into a trigonometric function value of a phase difference using a product-to-sum formula.

In operation S120, the first matrix and the second matrix are multiplied by the computing unit to be tested to obtain a result matrix to be tested.

In the embodiment of the present disclosure, the computing unit to be tested may be a matrix computing unit or a vector computing unit in the above-mentioned artificial intelligence chip.

In operation S130, the accuracy test result of the computing unit to be tested is determined according to the difference between the result matrix to be tested and the reference matrix.

In the embodiment of the present disclosure, the accuracy test result can be determined by using at least one of the target computing unit and the computing unit to be tested. For example, the accuracy test result can be determined by using the target computing unit.

In the disclosed embodiment, the absolute error and/or relative error between each value in the test result matrix and the corresponding value in the reference result can be calculated. The absolute error and/or relative error is compared with the error threshold to obtain the accuracy test result.

In the embodiment of the present disclosure, the accuracy test result may indicate whether the accuracy of the computing unit to be tested meets the requirements.

According to the disclosed embodiment, the first matrix and the second matrix each include a plurality of trigonometric function values. The product operation between the trigonometric function values can be converted into the corresponding trigonometric function operation by the product-to-difference formula. The matrix operation involved in the target computing unit is converted into the operation of finding the trigonometric function value. As a result, the computational load of the target computing unit is greatly reduced, random testing can be efficiently implemented, and the test coverage rate is improved.

It can be understood that the method of the present disclosure is described above, and the principle of the present disclosure will be described below.

It can be understood that the product-to-sum-difference formula may include the following formula 1:

(Formula 1)

is a phase value. is another phase value. The principle of the present disclosure will be described below in conjunction with Formula 1.

In some embodiments, the method may further include: using the target calculation unit to generate a first initial phase value, a second initial phase value, and a scale parameter. For example, two phase values may be randomly generated as the first initial phase value φ ₀ and the second initial phase value φ ₁ . A scale parameter K may also be generated. K may be a value greater than or equal to 1.

In some embodiments, the method may further include: generating a first phase sequence according to a preset radian, a scale parameter, and a first initial phase value. For example, the preset radian may be 2π. Using the preset radian and the scale parameter, an angular velocity parameter 2π/K may be determined. Based on the angular velocity parameter and the first initial phase value, K first phase values of the first phase sequence may be determined. The sine value of each first phase value in the first phase sequence may be determined to obtain a first trigonometric function value sequence . The first trigonometric function value sequence It can be expressed as:

(Formula 2)

In some embodiments, the method may further include: generating a second phase sequence according to a preset radian, a scale parameter, and a second initial phase value. For example, the preset radian may be 2π. Using the preset radian and the scale parameter, an angular velocity parameter 2π/K may be determined. Based on the angular velocity parameter and the second initial phase value, K second phase values of the second phase sequence may be determined. The sine value of each second phase value in the second phase sequence may be determined to obtain a second trigonometric function value sequence . The second trigonometric function value sequence It can be expressed as:

(Formula 3)

For example, if the first phase sequence is used as the first row of the first matrix and the second phase sequence is used as the second row of the second matrix, the first row of the first matrix and the second row of the second matrix are multiplied to obtain the reference value X of the first row of the reference matrix:

(Formula 4)

Using the product-to-difference formula, formula 4 can be converted to:

(Formula 5)

Let φ0+φ1=φ, and let , we can get:

(Formula 6)

According to Euler's formula and the geometric series summation formula, Formula 5 can be transformed:

(Formula 7)

Therefore, according to Formula 4 and Formula 6, the reference value X can be determined as:

(Formula 8)

It can be understood that K can be an integer greater than or equal to 3.

It can be understood that the above uses the example that the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third cosine value sequence to illustrate the principle of the present disclosure. The method of the present disclosure will be further illustrated below.

FIG. 2 is a schematic diagram of a first matrix, a second matrix, and a reference matrix according to an embodiment of the present disclosure.

As shown in Figure 2, the target computing unit can be used to generate a first trigonometric function value sequence tri201 and a second trigonometric function value sequence tri202. The first trigonometric function value sequence tri201 can be a first sine value sequence. The second trigonometric function value sequence tri202 can be a second sine value sequence. The first trigonometric function value sequence tri201 can include the 1st first trigonometric function value to the Kth first trigonometric function value. The second trigonometric function value sequence tri202 can include the 1st second trigonometric function value to the Kth second trigonometric function value. K can be an integer greater than 1. As shown in Figure 2, K can be 10. It can be understood that the first trigonometric function value sequence tri201 can be the above-mentioned first trigonometric function value sequence. The second trigonometric function value sequence tri202 may be the first trigonometric function value sequence That is, the K first phase values of the first trigonometric function value sequence tri201 increase sequentially. The K second phase values of the second trigonometric function value sequence tri202 increase sequentially.

In an embodiment of the present disclosure, a third trigonometric function value sequence can be generated using a target computing unit according to a scale parameter, a phase value of a first trigonometric function value sequence, and a phase value difference of a second trigonometric function value sequence. For example, according to the difference in phase values and the above-mentioned angular velocity parameter (2π/K), K third phase values of a third phase sequence can be obtained. The third trigonometric function value sequence can be obtained by processing K third phase values using the above-mentioned formula eight. As shown in FIG2 , a third trigonometric function value sequence tri203 can be generated using a target computing unit. The third trigonometric function value sequence tri203 can be a third cosine value sequence. The third trigonometric function value sequence tri203 can include the first third trigonometric function value to the Kth third trigonometric function value. Through an embodiment of the present disclosure, the third trigonometric function value sequence can be determined based on the difference between the first phase value and the second phase value, which provides a possibility for simplifying calculations and helps to accurately and cost-effectively generate a reference matrix.

In some embodiments, in some implementations of the above operation S110, a first matrix may be obtained using a target computing unit according to the first trigonometric function value sequence. The first matrix may include at least one first vector. The first vector may be obtained by cyclically shifting the first trigonometric function value sequence along a first direction by a first shifting bit number.

In the embodiment of the present disclosure, the first matrix may be an M×K matrix. M may be an integer less than or equal to K. As shown in FIG2 , the first matrix A200 includes M%K rows. Each row may be a first vector. It is understood that in the case of M=K, the first matrix may include K rows.

In the embodiment of the present disclosure, the first shift bit number is i. i may be an integer greater than or equal to 0 and less than K. i may be 0. That is, the first trigonometric function value sequence tri201 may be used as a first vector. The first direction may be a direction that decreases successively along the first phase value. As shown in FIG2 , the first direction may be a direction from the Kth first trigonometric function value to the 1st first trigonometric function value. i may also be 1, and the first trigonometric function value sequence tri201 is circularly shifted by 1 bit along the first direction to obtain a first vector as the 2nd row of the first matrix A200. i may also be 2, and the first trigonometric function value sequence tri201 is circularly shifted by 2 bits along the first direction to obtain a first vector as the 3rd row of the first matrix A200. i may also be 3, and the first trigonometric function value sequence tri201 is circularly shifted by 3 bits along the first direction to obtain a first vector as the 4th row of the first matrix A200.

In the embodiment of the present disclosure, M=i+1. As shown in FIG2 , the first shift bit number corresponding to the second row of the first matrix A200 is 1.

In the embodiment of the present disclosure, when i is greater than or equal to 1, the first vector includes the first preceding subvector and the first succeeding subvector in sequence, the first preceding subvector includes the i+1th to the Kth first trigonometric function values, and the first succeeding subvector includes the 1st to the ith first trigonometric function values. As shown in FIG2 , the first vector corresponding to i=1 serves as the 2nd row of the first matrix. The first vector corresponding to i=1 includes the first preceding subvector and the first succeeding subvector. The first preceding subvector includes the 2nd to the Kth first trigonometric function values. The first succeeding subvector includes the 1st trigonometric function value. As shown in FIG2 , the first vector corresponding to i=2 serves as the 3rd row of the first matrix. The first vector corresponding to i=2 includes the first preceding subvector and the first succeeding subvector. The first preceding subvector includes the 3rd to the Kth first trigonometric function values. The first succeeding subvector includes the 1st to the 2nd first trigonometric function values.

It can be understood that the first matrix of the present disclosure is described above, and the second matrix of the present disclosure will be described below.

In some embodiments, in some implementations of the above operation S110, a second matrix may be obtained using a target computing unit according to the second trigonometric function value sequence. The second matrix may include at least one second vector. The second vector may be obtained by cyclically shifting the second trigonometric function value sequence along the second direction by a second shifting bit number.

In the embodiment of the present disclosure, the second matrix may be an N×K matrix. As shown in FIG2 , the second matrix B200 includes N rows. Each row may be a second vector. N may be an integer less than or equal to K.

In the embodiment of the present disclosure, the second shift bit number is j. j is an integer greater than or equal to 0 and less than K. j can be 0. That is, the second trigonometric function value sequence tri202 can be used as a second vector. The second direction can be a direction in which the second phase value increases successively. As shown in FIG2 , the second direction can be a direction from the 1st second trigonometric function value to the Kth second trigonometric function value. j can also be 1, and the second trigonometric function value sequence tri202 is circularly shifted by 1 bit along the second direction to obtain a second vector as the 2nd row of the second matrix B200. j can also be 2, and the second trigonometric function value sequence tri202 is circularly shifted by 2 bits along the second direction to obtain a second vector as the 3rd row of the second matrix B200. i can also be 3, and the second trigonometric function value sequence tri202 is circularly shifted by 3 bits along the second direction to obtain a second vector as the 4th row of the second matrix B200. Through the embodiments of the present disclosure, by cyclically moving the trigonometric function value sequence along the first direction and the second direction respectively, different rows or columns of the two matrices to be multiplied can be determined, and a matrix of the same scale as the actual application scenario can be generated, which helps to further improve the accuracy of the test.

In the embodiment of the present disclosure, N=j+1. As shown in FIG2 , the second shift bit number corresponding to the second row of the second matrix B200 is 1.

In the embodiment of the present disclosure, when j is greater than or equal to 1, the second vector includes the second preceding subvector and the second succeeding subvector in sequence, the second preceding subvector includes the K-j+1th to the Kth second trigonometric function values, and the first succeeding subvector includes the 1st to the K-jth second trigonometric function values. As shown in FIG2 , the second vector corresponding to j=1 serves as the 2nd row of the second matrix. The second vector corresponding to j=1 includes the second preceding subvector and the second succeeding subvector. The second preceding subvector includes the Kth second trigonometric function value. The second succeeding subvector includes the 1st second trigonometric function value to the K-1th second trigonometric function value. As shown in FIG2 , the second vector corresponding to j=2 serves as the 3rd row of the second matrix. The second vector corresponding to j=2 includes the second preceding subvector and the second succeeding subvector. The first preceding subvector includes the K-1th first trigonometric function value to the Kth first trigonometric function value. The first succeeding subvector includes the 1st first trigonometric function value to the K-2th first trigonometric function value.

It can be understood that the second matrix of the present disclosure is described above, and the reference matrix of the present disclosure will be described below.

In some embodiments, in some implementations of the above operation S110, a reference matrix may also be generated by using a target computing unit according to the third trigonometric function value sequence.

In the embodiment of the present disclosure, the reference matrix may be an M×N matrix. As shown in FIG2 , the reference matrix C200 includes M%K rows and N%K columns.

In the embodiment of the present disclosure, the reference matrix includes a plurality of reference values, and the reference values corresponding to the first vector and the second vector are third trigonometric function values corresponding to the shift parameters in the third trigonometric function value sequence, and the shift parameters are obtained according to the first shift bit number and the second shift bit number. As shown in FIG2 , the reference matrix C200 may include M*N reference values. Through the embodiment of the present disclosure, the shift parameters obtained by using the first shift bit number and the second shift bit number can accurately determine the reference value of the product accumulation of the first vector and the second vector, which can effectively improve the accuracy of the reference matrix and improve the test accuracy.

In the embodiment of the present disclosure, the movement parameter is obtained according to the first movement number, the second movement number and the preset value. For example, the movement parameter z can be determined by the following formula:

(Formula 9)

g is an integer greater than or equal to 1.

In the embodiment of the present disclosure, the reference value is the zth third trigonometric function value in the third trigonometric function value sequence. As shown in FIG2 , the first number of shift bits corresponding to the first row of the first matrix A200 is 0, and the second number of shift bits corresponding to the first row of the second matrix B200 is 0. The multiplication and accumulation result between the first row of the first matrix A200 and the first row of the second matrix B200 can be the first third trigonometric function value in the third trigonometric function value sequence tri203. The first number of shift bits corresponding to the first row of the first matrix A200 is 0, and the second number of shift bits corresponding to the second row of the second matrix B200 is 1. The multiplication and accumulation result between the first row of the first matrix A200 and the second row of the second matrix B200 can be the second third trigonometric function value in the third trigonometric function value sequence tri203.

It can be understood that the number of rows of the first matrix can be any value, and the number of rows of the second matrix can also be any value. The following will take M=N=K as an example to further illustrate the reference matrix of the present disclosure.

In the embodiment of the present disclosure, when the scale of the first matrix, the scale of the second matrix and the scale of the reference matrix are consistent, the reference vector of the reference matrix is obtained by circularly shifting the third trigonometric function value sequence along the first direction by the number of first shift bits. As shown in FIG2, if M=N=K, the first number of shift bits is i. i can be an integer greater than or equal to 0 and less than K. i can be 0. That is, the third trigonometric function value sequence tri203 can be used as a reference vector. The first direction can be a direction in which the first phase value decreases successively. As shown in FIG2, the first direction can be a direction from the Kth third trigonometric function value to the 1st third trigonometric function value. i can also be 1, and the third trigonometric function value sequence tri203 is circularly shifted by 1 bit along the first direction, and a reference vector can be obtained as the second row of the reference matrix A200. i can also be 2, and the third trigonometric function value sequence tri203 is circularly shifted by 2 bits along the first direction, and a reference vector can be obtained as the third row of the reference matrix C200. i can also be 3, and the third trigonometric function value sequence tri203 is circularly shifted by 3 bits along the first direction to obtain a reference vector as the fourth row of the reference matrix C200. Through the embodiments of the present disclosure, test data can be generated efficiently and quickly, thereby improving test efficiency.

It can be understood that the first matrix, the second matrix and the reference matrix of the present disclosure are described above in conjunction with FIG. 2 , and the first matrix, the second matrix and the reference matrix of the present disclosure will be further described below in conjunction with specific matrix examples.

In some embodiments, the first phase sequence corresponding to the first trigonometric function value is an arithmetic progression, and the first tolerance of the first phase sequence is determined according to a preset radian and a scale parameter. For example, the preset radian may be 2π. The scale parameter may be K. Taking K=4 as an example, the first tolerance may be π/2. The first phase sequence may be “0, π/2, π, 3π/2”. The first trigonometric function value sequence may be a first sine value sequence <0, 1, 0, -1>.

In some embodiments, the second phase sequence corresponding to the second trigonometric function value is an arithmetic progression, and the second tolerance of the second phase sequence is determined according to a preset radian and a scale parameter. For example, the preset radian may be 2π. The scale parameter may be K. Taking K=4 as an example, the second tolerance may be π/2. The second phase sequence may be “0, π/2, π, 3π/2”. The second trigonometric function value sequence may be a second sine value sequence <0, 1, 0, -1>.

In some embodiments, the third phase sequence corresponding to the third trigonometric function value is an arithmetic progression, and the third tolerance of the third phase sequence is determined according to a preset radian and a scale parameter. The third initial phase value of the third phase sequence may be obtained according to the difference between the first initial phase value and the second initial phase value. For example, the preset radian may be 2π. The scale parameter may be K. The first initial phase value may be 0. The second initial phase value may be 0. Thus, the third initial phase value is 0. Taking K=4 as an example, the third tolerance may be π/2. The third phase sequence may be "0,π/2,π,3π/2". The third trigonometric function value sequence may be a third cosine value sequence. Based on the above formula seven, the third trigonometric function value sequence may be <2,0,-2,0>.

Next, the first matrix, the second matrix, and the reference matrix can be obtained respectively using the target computing unit according to the first trigonometric function value sequence, the second trigonometric function value sequence, and the third trigonometric function value sequence. As described above, in the process of obtaining the first matrix, the second matrix, and the reference matrix, the trigonometric function value sequence can be cyclically shifted. It can be understood that the cyclic shift can be implemented in various ways. For example, the cyclic shift can be implemented by storing and copying (memcpy) the corresponding values.

In some embodiments, in other implementations of the above operation S110, using the target computing unit to respectively determine the first matrix, the second matrix, and the reference matrix includes: using the target computing unit to respectively copy the i+1th to Kth first trigonometric function values and the 1st to ith first trigonometric function values to obtain the first vector of the first matrix. For example, in the case of i=0, the 1st to Kth first trigonometric function values <0,1,0,-1> can be copied as the 1st row of the first matrix. In the case of i=1, the 2nd to 4th first trigonometric function values <1,0,-1> and the 1st first trigonometric function value <0> can be copied as the 2nd row <1,0,-1,0> of the first matrix. In the case of i=2, the 3rd to 4th first trigonometric function values <0,-1> and the 1st to 2nd first trigonometric function values <0,1> can be copied as the 3rd row <0,-1,0,1> of the first matrix. In the case of i=3, the 4th first trigonometric function value <-1> and the 1st to 3rd first trigonometric function values <0,1,0> can be copied as the 4th row <-1,0,1,0> of the first matrix. Thus, the first matrix can be:

(Formula 10)

In some embodiments, in other implementations of the above operation S110, using the target computing unit to respectively determine the first matrix, the second matrix, and the reference matrix includes: using the target computing unit to respectively copy the K-j+1th to Kth second trigonometric function values and the 1st to K-jth second trigonometric function values to obtain a second vector of the second matrix. For example, in the case of j=0, the 1st to Kth second trigonometric function values <0,1,0,-1> can be copied as the 1st row of the second matrix. In the case of j=1, the 4th second trigonometric function value <-1> and the 1st to 3rd first trigonometric function values <1,0,-1> can be copied as the 2nd row <-1,0,1,0> of the second matrix. In the case of j=2, the 3rd to 4th second trigonometric function values <0,-1> and the 1st to 2nd first trigonometric function values <0,1> can be copied as the 3rd row <0,-1,0,1> of the second matrix. When i=3, the second to fourth second trigonometric function values <1,0,-1> and the first second trigonometric function value <0> can be copied as the fourth row <1,0,-1,0> of the second matrix. Thus, the second matrix can be:

(Formula 11)

In some embodiments, in other implementations of the above operation S110, using the target computing unit to respectively determine the first matrix, the second matrix, and the reference matrix includes: using the target computing unit to copy the third trigonometric function value corresponding to the movement parameter to obtain the reference value of the reference matrix corresponding to the first vector and the second vector. For example, for the 1st row of the first matrix and the 1st row of the second matrix, the 1st trigonometric function value <2> of the third trigonometric function sequence can be copied as the reference value of the 1st row and the 1st column of the reference matrix. For the 2nd row of the first matrix and the 3rd row of the second matrix, the 4th third trigonometric function value <0> can be copied as the reference value of the 2nd row and the 3rd column of the reference matrix. For the 3rd row of the first matrix and the 4th row of the second matrix, the 2nd third trigonometric function value <0> can be copied as the reference value of the 2nd row and the 3rd column of the reference matrix. The reference matrix can be:

(Formula 12)

It can be understood that the multiple first vectors include M first vectors whose first shift bit numbers are different from each other. The multiple second vectors include N second vectors whose second shift bit numbers are different from each other. It can also be understood that in order to implement the test, one or more first vectors can be copied. The reference value corresponding to the first vector can also be determined using the above formula nine. Through the embodiments of the present disclosure, different trigonometric function value sequences are copied multiple times to implement circular shift, further reducing the computing resource and storage resource overhead of the target computing unit, and further improving the test efficiency.

It can be understood that the above description uses M=N=K as an example to explain the present disclosure. However, the present disclosure is not limited to this, and M and N may be less than K. For example, two row vectors may be randomly selected from the first matrix shown in Formula 10, or three row vectors may be randomly selected from the second matrix shown in Formula 11. Multiple reference values of the corresponding reference matrix may also be determined using Formula 9 above.

It can be understood that the shift parameter of the reference value can indicate the position of the reference value in the reference matrix. For example, the reference value determined according to the first shift bit number i and the second shift bit number j can be the reference value of the i+1th row and j+1th column in the reference matrix.

It can be understood that the present disclosure is described above in conjunction with the product-to-sum-difference formula shown in Formula 1. However, the present disclosure is not limited thereto, and the above operation S110 can be implemented by using various product-to-sum-difference formulas, which will be described below.

In some embodiments, the product-to-sum-difference formula may further include:

(Formula 13)

(Formula 14)

(Formula 15)

In some embodiments, the first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third cosine value sequence. For example, based on the above formula 13, the first matrix, the second matrix and the reference matrix can be determined.

In some embodiments, the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third sine value sequence. For example, based on the above formula 14, the first matrix, the second matrix and the reference matrix can be determined.

In some embodiments, the first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third sine value sequence. For example, based on the above formula 15, the first matrix, the second matrix and the reference matrix can be determined.

It can be understood that the above description describes the operations performed by the target computing unit of the present disclosure, and the following description will describe the operations performed by the computing unit to be tested.

In some embodiments, using the computing unit to be tested to multiply the first matrix and the second matrix to obtain the result matrix to be tested includes: using the computing unit to be tested to multiply the first matrix and the transposed second matrix to obtain the result matrix to be tested. For example, the second matrix B200 shown in Figure 2 can be transposed. And the first matrix A200 is multiplied by the transposed second matrix B200 to obtain the result matrix to be tested.

In some other embodiments, using the computing unit to be tested to multiply the first matrix and the second matrix to obtain the result matrix to be tested further includes: using the computing unit to be tested to multiply the transposed first matrix and the second matrix to obtain the result matrix to be tested. For example, the first matrix A200 shown in Figure 2 can be transposed. And the transposed first matrix A200 is multiplied by the second matrix B200 to obtain the result matrix to be tested.

It can be understood that the transposition operation can be performed by the target computing unit, the memory access unit or the computing unit to be tested, and the present disclosure does not limit this.

It can be understood that the above describes the operations performed by the computing unit to be tested, and some methods of determining the accuracy test results of the present disclosure will be described below.

In some embodiments, the difference includes multiple difference values. For example, the reference matrix may include M×N reference values. The test result matrix may include M×N test values. The difference value between the test value and the reference value is determined, and a total of M×N difference values may be determined.

In some embodiments, determining the test result of the computing unit to be tested according to the difference between the test result matrix and the reference matrix includes: in response to determining that at least one difference value is less than or equal to a preset difference threshold, determining the test result of the computing unit to be tested as a first test result. In response to determining that at least one difference value is greater than a preset difference threshold, determining the test result of the computing unit to be tested as a second test result. The first test result is used to indicate that the accuracy of the computing unit to be tested meets the requirements. The second test result is used to indicate that the accuracy of the computing unit to be tested does not meet the requirements.

For example, the number of difference values greater than a preset difference threshold may be determined. If the number is also greater than the preset number threshold, the test result may be determined as the second test result. If the number is less than the preset number threshold, the test result may be determined as the first test result.

It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

FIG. 3 is a schematic block diagram of a testing device for a computing unit according to an embodiment of the present disclosure.

As shown in FIG. 3 , the apparatus 300 may include a target computing unit 310 and a computing unit to be tested 320 .

The target calculation unit 310 may be configured to obtain a first matrix, a second matrix and a reference matrix according to a first trigonometric function value sequence, a second trigonometric function value sequence and a third trigonometric function value sequence, respectively. The first matrix includes at least one first vector, the first vector is obtained by circularly shifting the first trigonometric function value sequence along a first direction by a first shifting bit number, the second matrix includes at least one second vector, the second vector is obtained by circularly shifting the second trigonometric function value sequence along a second direction by a second shifting bit number, and the phase value of the third trigonometric function value sequence is obtained according to the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence;

The calculation unit 320 to be tested is configured to multiply the first matrix and the second matrix to obtain a result matrix to be tested.

The target computing unit 310 is further configured to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix.

In some embodiments, the reference matrix includes multiple reference values, and the reference values corresponding to the first vector and the second vector are third trigonometric function values in the third trigonometric function value sequence corresponding to the shift parameters, and the shift parameters are obtained based on the first shift bit number and the second shift bit number.

In some embodiments, the first trigonometric function value sequence includes first trigonometric function values with a scale parameter, the second trigonometric function value sequence includes second trigonometric function values with a scale parameter, and the third trigonometric function value is obtained based on the scale parameter and the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence.

In some embodiments, when the scales of the first matrix, the second matrix and the reference matrix are consistent, the reference vector of the reference matrix is obtained by cyclically shifting the third trigonometric function value sequence along the first direction by a first shift bit number.

In some embodiments, the scale parameter is K, the first trigonometric function value sequence includes K first trigonometric function values, the second trigonometric function value sequence includes K second trigonometric function values, the third trigonometric function value sequence includes K third trigonometric function values, and K is an integer greater than 1. The first shift bit number is i, i is an integer greater than or equal to 0 and less than K, and the second shift bit number is j, j is an integer greater than or equal to 0 and less than K.

In some embodiments, the first vector includes a first preceding sub-vector and a first succeeding sub-vector in sequence, the first preceding sub-vector including the i+1th to Kth first trigonometric function values, and the first succeeding sub-vector including the 1st to ith first trigonometric function values; the second vector includes K second trigonometric function values, the second vector includes a second preceding sub-vector and a second succeeding sub-vector in sequence, the second preceding sub-vector including the K-j+1th to Kth second trigonometric function values, and the first succeeding sub-vector including the 1st to K-jth second trigonometric function values, i is an integer greater than or equal to 1, and j is an integer greater than or equal to 1.

In some embodiments, the shift parameter is obtained according to the first shift bit number and the second shift bit number by a formula. In the above formula 9, z is the shift parameter, the reference value is the zth third trigonometric function value in the third trigonometric function value sequence, and g is a positive integer.

In some embodiments, the first phase sequence corresponding to the first trigonometric function value is an arithmetic progression, and the first tolerance of the first phase sequence is determined according to a preset radian and scale parameter. The second phase sequence corresponding to the second trigonometric function value is an arithmetic progression, and the second tolerance of the second phase sequence is determined according to a preset radian and scale parameter.

In some embodiments, the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third cosine value sequence. Alternatively, the first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third cosine value sequence. Alternatively, the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third sine value sequence. Alternatively, the first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third sine value sequence.

In some embodiments, the plurality of first vectors include M first vectors whose first shift bit numbers are different from each other, where M is an integer greater than 1 and less than or equal to K. The plurality of second vectors include N second vectors whose second shift bit numbers are different from each other, where N is an integer greater than 1 and less than or equal to K, and the reference matrix includes M×N reference values.

In some embodiments, the target computing unit is further configured to perform the following operations to respectively determine the first matrix, the second matrix, and the reference matrix: respectively copy the i+1th to Kth first trigonometric function values and the 1st to ith first trigonometric function values to obtain the first vector of the first matrix. respectively copy the K-j+1th to Kth second trigonometric function values and the 1st to K-jth second trigonometric function values to obtain the second vector of the second matrix. respectively copy the third trigonometric function value corresponding to the movement parameter to obtain the reference value of the reference matrix corresponding to the first vector and the second vector.

In some embodiments, the computing unit to be tested is further configured to perform at least one of the following operations to multiply the first matrix and the second matrix to obtain a result matrix to be tested: multiply the transposed first matrix and the second matrix by the computing unit to be tested to obtain a result matrix to be tested. Multiply the first matrix and the transposed second matrix by the computing unit to be tested to obtain a result matrix to be tested.

In some embodiments, the difference includes a plurality of difference values, and the target computing unit is further configured to perform the following operations to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix: in response to determining that at least one difference value is less than or equal to a preset difference threshold, determine that the accuracy test result of the computing unit to be tested is a first test result. The first test result is used to indicate that the accuracy of the computing unit to be tested meets the requirement.

In some embodiments, the difference includes a plurality of difference values, and the target computing unit is further configured to perform the following operations to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix: in response to determining that at least one difference value is greater than a preset difference threshold, determine that the accuracy test result of the computing unit to be tested is a second test result. The second test result is used to indicate that the accuracy of the computing unit to be tested does not meet the requirement.

It can be understood that the apparatus of the present disclosure is described above, and the device including the apparatus will be described below.

FIG. 4 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

As shown in Fig. 4, the device 4000 may include a computing unit testing apparatus 400. The apparatus 400 may be the apparatus 300 described above.

In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

FIG5 shows a schematic block diagram of an example electronic device 500 that can be used to implement an embodiment of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and/or required herein.

As shown in FIG5 , the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 to a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input/output (I/O) interface 505 is also connected to the bus 504.

A number of components in the device 500 are connected to the I/O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The computing unit 501 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as the testing method of the computing unit. For example, in some embodiments, the testing method of the computing unit may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 500 via the ROM 502 and/or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the testing method of the computing unit described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to execute the computing unit test method in any other appropriate manner (eg, by means of firmware).

Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions/operations specified in the flow chart and/or block diagram. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims (29)

1. A method for testing a computing unit, comprising: According to the first trigonometric function value sequence, the second trigonometric function value sequence and the third trigonometric function value sequence, a first matrix, a second matrix and a reference matrix are obtained respectively by using a target computing unit, wherein the first matrix includes at least one first vector, the first vector is obtained by circularly shifting the first trigonometric function value sequence along a first direction by a first shifting bit number, the second matrix includes at least one second vector, the second vector is obtained by circularly shifting the second trigonometric function value sequence along a second direction by a second shifting bit number, and the phase value of the third trigonometric function value sequence is obtained according to the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence; Multiplying the first matrix and the second matrix by the computing unit to be tested to obtain a result matrix to be tested; and The accuracy test result of the computing unit to be tested is determined according to the difference between the result matrix to be tested and the reference matrix. 2. The method according to claim 1, wherein the reference matrix includes multiple reference values, the reference values corresponding to the first vector and the second vector are third trigonometric function values in the third trigonometric function value sequence corresponding to shift parameters, and the shift parameters are obtained based on the first shift bit number and the second shift bit number. 3. The method according to claim 1, wherein the first trigonometric function value sequence includes a scale parameter number of first trigonometric function values, the second trigonometric function value sequence includes a scale parameter number of second trigonometric function values, and the third trigonometric function value is obtained based on the scale parameter and the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence. 4. The method according to claim 1, wherein, when the scale of the first matrix, the scale of the second matrix and the scale of the reference matrix are consistent, the reference vector of the reference matrix is obtained by circularly shifting the third trigonometric function value sequence along the first direction by the first shift bit number. 5. The method according to claim 3, wherein the scale parameter is K, the first trigonometric function value sequence includes K first trigonometric function values, the second trigonometric function value sequence includes K second trigonometric function values, the third trigonometric function value sequence includes K third trigonometric function values, and K is an integer greater than 1. The first shift bit number is i, i is an integer greater than or equal to 0 and less than K, and the second shift bit number is j, j is an integer greater than or equal to 0 and less than K. 6. The method according to claim 5, wherein the first vector includes a first preceding sub-vector and a first succeeding sub-vector in sequence, the first preceding sub-vector includes the i+1th to Kth first trigonometric function values, and the first succeeding sub-vector includes the 1st to ith first trigonometric function values; the second vector includes K second trigonometric function values, the second vector includes a second preceding sub-vector and a second succeeding sub-vector in sequence, the second preceding sub-vector includes the K-j+1th to Kth second trigonometric function values, and the first succeeding sub-vector includes the 1st to K-jth second trigonometric function values, i is an integer greater than or equal to 1, and j is an integer greater than or equal to 1. 7. The method according to claim 6, wherein the shift parameter is obtained according to the first shift bit number and the second shift bit number by the following formula: Wherein, z is a movement parameter, the reference value is the zth third trigonometric function value in the third trigonometric function value sequence, and g is a positive integer. 8. The method according to claim 1, wherein the first phase sequence corresponding to the first trigonometric function value is an arithmetic progression, and the first tolerance of the first phase sequence is determined according to a preset radian and the scale parameter; The second phase sequence corresponding to the second trigonometric function value is an arithmetic progression, and the second tolerance of the second phase sequence is determined according to the preset radian and the scale parameter. 9. The method according to claim 1, wherein the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third cosine value sequence; or The first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third cosine value sequence; or The first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third sine value sequence; or The first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third sine value sequence. 10. The method according to claim 5, wherein the plurality of first vectors include M first vectors that are different from each other, and M is an integer greater than 1 and less than or equal to K. The plurality of second vectors include N second vectors that are different from each other, where N is an integer greater than 1 and less than or equal to K, and the reference matrix includes M×N reference values. 11. The method according to claim 6, wherein the determining the first matrix, the second matrix and the reference matrix respectively by using the target computing unit comprises: Using a target computing unit, respectively copy the i+1th to Kth first trigonometric function values and the 1st to ith first trigonometric function values to obtain a first vector of the first matrix; using the target computing unit to copy the second trigonometric function values from K-j+1th to Kth and the second trigonometric function values from 1st to K-jth, respectively, to obtain a second vector of the second matrix; and The third trigonometric function value corresponding to the movement parameter is copied by using the target calculation unit to obtain a reference value of the reference matrix corresponding to the first vector and the second vector. 12. The method according to claim 1, wherein the step of multiplying the first matrix and the second matrix by the computing unit to be tested to obtain a result matrix to be tested comprises at least one of the following: Using the computing unit to be tested, multiplying the transposed first matrix and the second matrix to obtain the result matrix to be tested; The first matrix and the transposed second matrix are multiplied by the computing unit to be tested to obtain the result matrix to be tested. 13. The method of claim 1, wherein the difference comprises a plurality of difference values, Determining the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix includes: In response to determining that at least one of the difference values is less than or equal to a preset difference threshold, determining the accuracy test result of the computing unit to be tested as a first test result, wherein the first test result is used to indicate that the accuracy of the computing unit to be tested meets the requirements. 14. The method of claim 1, wherein the difference comprises a plurality of difference values, Determining the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix includes: In response to determining that at least one of the difference values is greater than a preset difference threshold, determining that the accuracy test result of the computing unit to be tested is a second test result, wherein the second test result is used to indicate that the accuracy of the computing unit to be tested does not meet the requirement. 15. A testing device for a computing unit, comprising: A target calculation unit is configured to obtain a first matrix, a second matrix and a reference matrix respectively according to a first trigonometric function value sequence, a second trigonometric function value sequence and a third trigonometric function value sequence, wherein the first matrix includes at least one first vector, the first vector is obtained by circularly shifting the first trigonometric function value sequence along a first direction by a first shifting bit number, the second matrix includes at least one second vector, the second vector is obtained by circularly shifting the second trigonometric function value sequence along a second direction by a second shifting bit number, and the phase value of the third trigonometric function value sequence is obtained according to the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence; a calculation unit to be tested, configured to multiply the first matrix and the second matrix to obtain a result matrix to be tested; and The target computing unit is further configured to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix. 16. The device according to claim 15, wherein the reference matrix comprises a plurality of reference values, the reference values corresponding to the first vector and the second vector are third trigonometric function values in the third trigonometric function value sequence corresponding to shift parameters, and the shift parameters are obtained based on the first shift bit number and the second shift bit number. 17. The device according to claim 15, wherein the first trigonometric function value sequence includes a scale parameter number of first trigonometric function values, the second trigonometric function value sequence includes a scale parameter number of second trigonometric function values, and the third trigonometric function value is obtained based on the scale parameter and the difference between the phase value of the first trigonometric function value sequence and the phase value of the second trigonometric function value sequence. 18. The apparatus according to claim 15, wherein the scale parameter is K, the first trigonometric function value sequence includes K first trigonometric function values, the second trigonometric function value sequence includes K second trigonometric function values, the third trigonometric function value sequence includes K third trigonometric function values, and K is an integer greater than 1. The first shift bit number is i, i is an integer greater than or equal to 0 and less than K, and the second shift bit number is j, j is an integer greater than or equal to 0 and less than K. 19. The method according to claim 18, wherein the first vector includes a first preceding sub-vector and a first succeeding sub-vector in sequence, the first preceding sub-vector includes the i+1th to Kth first trigonometric function values, and the first succeeding sub-vector includes the 1st to ith first trigonometric function values; the second vector includes K second trigonometric function values, the second vector includes a second preceding sub-vector and a second succeeding sub-vector in sequence, the second preceding sub-vector includes the K-j+1th to Kth second trigonometric function values, and the first succeeding sub-vector includes the 1st to K-jth second trigonometric function values, i is an integer greater than or equal to 1, and j is an integer greater than or equal to 1. 20. The apparatus according to claim 19, wherein the shift parameter is obtained according to the first shift bit number and the second shift bit number by the following formula: Wherein, z is a movement parameter, the reference value is the zth third trigonometric function value in the third trigonometric function value sequence, and g is a positive integer. 21. The apparatus according to claim 15, wherein the first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third cosine value sequence; or The first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third cosine value sequence; or The first trigonometric function value sequence is a first sine value sequence, the second trigonometric function value sequence is a second cosine value sequence, and the third trigonometric function value sequence is a third sine value sequence; or The first trigonometric function value sequence is a first cosine value sequence, the second trigonometric function value sequence is a second sine value sequence, and the third trigonometric function value sequence is a third sine value sequence. 22. The apparatus according to claim 19, wherein the target calculation unit is further configured to perform the following operations to respectively determine the first matrix, the second matrix and the reference matrix: Copy the i+1th to Kth first trigonometric function values and the 1st to ith first trigonometric function values respectively to obtain a first vector of the first matrix; Copy the K-j+1th to Kth second trigonometric function values and the 1st to K-jth second trigonometric function values respectively to obtain a second vector of the second matrix; and The third trigonometric function value corresponding to the movement parameter is copied to obtain a reference value of the reference matrix corresponding to the first vector and the second vector. 23. The apparatus according to claim 15, wherein the calculation unit to be tested is further configured to perform at least one of the following operations to multiply the first matrix and the second matrix to obtain a result matrix to be tested: Using the computing unit to be tested, multiplying the transposed first matrix and the second matrix to obtain the result matrix to be tested; The first matrix and the transposed second matrix are multiplied by the computing unit to be tested to obtain the result matrix to be tested. 24. The apparatus of claim 15, wherein the difference comprises a plurality of difference values, The target computing unit is further configured to perform the following operations to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix: In response to determining that at least one of the difference values is less than or equal to a preset difference threshold, determining the accuracy test result of the computing unit to be tested as a first test result, wherein the first test result is used to indicate that the accuracy of the computing unit to be tested meets the requirements. 25. The apparatus of claim 15, wherein the difference comprises a plurality of difference values, The target computing unit is further configured to perform the following operations to determine the accuracy test result of the computing unit to be tested according to the difference between the result matrix to be tested and the reference matrix: In response to determining that at least one of the difference values is greater than a preset difference threshold, determining that the accuracy test result of the computing unit to be tested is a second test result, wherein the second test result is used to indicate that the accuracy of the computing unit to be tested does not meet the requirement. 26. An electronic device comprising the device according to any one of claims 15 to 25. 27. An electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 14. 28. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 14. 29. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 14.