CN118672779A - Memory multiplexing method, device, equipment and medium - Google Patents

Abstract

The present disclosure provides a memory reuse method, device, equipment and medium, which relates to the field of artificial intelligence technology, especially to the field of deep learning and memory management technology. The implementation scheme is: allocate multiple memory blocks accordingly for multiple first tensors of the first sub-graph that is first executed in multiple sub-graphs; for each second sub-graph executed after the first sub-graph in the multiple sub-graphs, respectively perform the following operations: reset the value of the first tag of each current memory block to a preset value; and for each second tensor of the second sub-graph in turn, perform the following operations: obtain a reusable memory block of the second tensor in the current multiple memory blocks; in response to obtaining the reusable memory block of the second tensor, determine the memory space reused by the second tensor in the reusable memory block; and based on the memory space reused by the second tensor, update the value of the first tag of the reusable memory block.

Description

Memory reuse method, device, equipment and medium

Technical Field

The present disclosure relates to the field of artificial intelligence technology, in particular to the field of deep learning and memory management technology, and specifically to a memory reuse method, device, electronic device, computer-readable storage medium, and computer program product for a computational graph including multiple subgraphs.

Background Art

Artificial intelligence is a discipline that studies how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, as well as machine learning/deep learning, big data processing technology, knowledge graph technology, and other major directions.

Tensor Virtual Machine (TVM) is an open source deep learning compiler stack that allows users to efficiently execute deep learning models on different hardware platforms. An important feature of TVM is BYOC (Bring Your Own Codegen to TVM), which is a framework that allows users to integrate their own AI chip accelerators into TVM to achieve optimized support for specific hardware. The core idea of BYOC is to divide the computation graph of the deep learning model into different subgraphs, which can be customized and optimized based on the characteristics and optimization strategies of the hardware.

The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art.

Summary of the invention

The present disclosure provides a method, apparatus, electronic device, computer-readable storage medium, and computer program product for memory reuse of a computational graph comprising multiple subgraphs.

According to one aspect of the present disclosure, a memory reuse method for a computational graph including multiple subgraphs is provided, comprising: allocating multiple memory blocks accordingly for multiple first tensors of a first subgraph that is first executed among the multiple subgraphs, each of the multiple memory blocks corresponding to respective memory block information and reuse mark information, the memory block information comprising an address range and a memory size of the corresponding memory block, the reuse mark information comprising a first mark for recording a reusable memory size in the corresponding memory block; for each second subgraph executed after the first subgraph among the multiple subgraphs, respectively performing the following first operation: resetting the value of the first mark of each memory block in the current multiple memory blocks to a preset value, the preset value indicates that all memories in the corresponding memory block can be reused; and for each second tensor of the second subgraph, the following second operation is performed in sequence: based on the memory size required by the second tensor and the current value of the first tag of each memory block, a reusable memory block of the second tensor is obtained in the current multiple memory blocks; in response to obtaining the reusable memory block of the second tensor, based on the memory size required by the second tensor, the address range of the reusable memory block and the current value of the first tag, a memory space reused by the second tensor is determined in the reusable memory block; and based on the memory space reused by the second tensor, the value of the first tag of the reusable memory block is updated.

According to another aspect of the present disclosure, a memory reuse device for a computational graph including multiple subgraphs is provided, comprising: an allocation unit, configured to allocate multiple memory blocks correspondingly to multiple first tensors of a first subgraph that is first executed in the multiple subgraphs, each of the multiple memory blocks corresponding to respective memory block information and reuse mark information, the memory block information comprising an address range and a memory size of the corresponding memory block, the reuse mark information comprising a first mark for recording a reusable memory size in the corresponding memory block; an execution unit, configured to respectively perform the following first operation for each second subgraph executed after the first subgraph in the multiple subgraphs, the execution unit comprising: a first setting subunit, configured to reset the value of the first mark of each memory block in the current multiple memory blocks to a preset value, the preset Set a value indicating that all memories in the corresponding memory block can be reused; and an execution subunit is configured to perform the following second operation for each second tensor of the second subgraph in turn, and the execution subunit: an acquisition module is configured to acquire a reusable memory block of the second tensor in the current multiple memory blocks based on the memory size required by the second tensor and the current value of the first tag of each memory block; a determination module is configured to determine the memory space reused by the second tensor in the reusable memory block in response to acquiring the reusable memory block of the second tensor based on the memory size required by the second tensor, the address range of the reusable memory block and the current value of the first tag; and a first update module is configured to update the value of the first tag of the reusable memory block based on the memory space reused by the second tensor.

According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned memory reuse method for a computational graph including multiple subgraphs.

According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the above-mentioned memory reuse method for a computational graph including multiple subgraphs.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program implements the above-mentioned memory reuse method for a computational graph comprising multiple subgraphs when executed by a processor.

According to one or more embodiments of the present disclosure, by marking each allocated memory block corresponding to the previous subgraph, when allocating memory for each tensor of the next subgraph, first, based on the mark of the allocated memory block, it is determined whether there is a reusable memory block in the allocated memory block; if so, the memory space therein is reused, thereby avoiding the problem of large overall memory usage when allocating memory for multiple subgraphs, and easy memory overflow when there are many subgraphs or a large tensor scale.

It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

FIG1 shows a schematic diagram of an exemplary system in which various methods described herein may be implemented according to an embodiment of the present disclosure;

FIG2 shows a flowchart of a memory reuse method for a computation graph including multiple subgraphs according to an embodiment of the present disclosure;

FIG3 shows a flowchart of a memory reuse method for a computation graph including multiple subgraphs according to an exemplary embodiment of the present disclosure;

FIG4 shows a structural block diagram of a memory reuse device for a computation graph including multiple subgraphs according to an embodiment of the present disclosure;

FIG. 5 shows a block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure.

DETAILED DESCRIPTION

The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, temporal relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and/or" used in this disclosure covers any one of the listed items and all possible combinations.

After the TVM subgraph is split, a memory block (such as the AI chip memory) will be allocated to each subgraph before running, and then the operator will be run on the corresponding memory for inference. In order to prevent the memory allocation operation from taking up the time of inference, all memory allocation occurs before the operator runs, that is, the memory blocks are uniformly allocated for each tensor of each subgraph, and then the operators are run in sequence according to the topological relationship of the subgraph. Because the operator has not started running, the memory occupied by the previous subgraph will not be released when the memory is allocated for the subsequent subgraph. In related technologies, each subgraph can allocate the memory blocks it needs from the free memory pool of the AI chip, that is, the memory allocation between each subgraph is completely independent, and the total memory occupied will continue to accumulate, which will cause the overall memory usage to be large, and memory overflow problems are prone to occur when there are many subgraphs or the scale of tensors is large.

An embodiment of the present disclosure provides a memory reuse method for a computational graph including multiple subgraphs. By marking each allocated memory block corresponding to the previous subgraph, when allocating memory for each tensor of the next subgraph, first, based on the mark of the allocated memory block, it is determined whether there is a reusable memory block in the allocated memory block; if so, the memory space therein is reused, thereby avoiding the problem of large overall memory usage when allocating memory for multiple subgraphs, and easy memory overflow when there are many subgraphs or a large tensor scale.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG1 shows a schematic diagram of an exemplary system 100 in which various methods and apparatuses described herein may be implemented according to an embodiment of the present disclosure. Referring to FIG1 , the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.

In an embodiment of the present disclosure, the server 120 may run one or more services or software applications that enable execution of a memory reuse method for a computation graph including multiple subgraphs.

In some embodiments, server 120 may also provide other services or software applications, which may include non-virtualized environments and virtualized environments. In some embodiments, these services may be provided as web-based services or cloud services, such as provided to users of client devices 101, 102, 103, 104, 105, and/or 106 under a software as a service (SaaS) model.

In the configuration shown in FIG. 1 , the server 120 may include one or more components that implement the functions performed by the server 120. These components may include software components, hardware components, or a combination thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and/or 106 may in turn utilize one or more client applications to interact with the server 120 to utilize the services provided by these components. It should be understood that a variety of different system configurations are possible, which may be different from the system 100. Therefore, FIG. 1 is an example of a system for implementing the various methods described herein and is not intended to be limiting.

The user may use client devices 101, 102, 103, 104, 105 and/or 106 to send execution instructions for the computation graph. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Although FIG. 1 depicts only six client devices, those skilled in the art will appreciate that the present disclosure may support any number of client devices.

Client devices 101, 102, 103, 104, 105 and/or 106 may include various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, game systems, thin clients, various messaging devices, sensors or other sensing devices, etc. These computer devices may run various types and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as GOOGLE Chrome OS); or include various mobile operating systems, such as MICROSOFT Windows Mobile OS, iOS, Windows Phone, Android. Portable handheld devices may include cellular phones, smart phones, tablet computers, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Game systems may include various handheld game devices, Internet-enabled game devices, etc. Client devices are capable of executing various different applications, such as various Internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and may use various communication protocols.

The network 110 may be any type of network known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP/IP, SNA, IPX, etc. By way of example only, the one or more networks 110 may be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and/or any combination of these and/or other networks.

Server 120 may include one or more general purpose computers, dedicated server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. Server 120 may include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain a server's virtual storage device). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

The computing units in the server 120 may run one or more operating systems including any of the above operating systems and any commercially available server operating systems. The server 120 may also run any of a variety of additional server applications and/or middle-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and/or event updates received from users of client devices 101, 102, 103, 104, 105, and/or 106. Server 120 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and/or 106.

In some embodiments, the server 120 may be a server of a distributed system, or a server combined with a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in a cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. The databases 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. The databases 130 may be of different types. In some embodiments, the databases used by the server 120 may be, for example, relational databases. One or more of these databases may store, update, and retrieve data to and from the databases in response to commands.

In some embodiments, one or more of the databases 130 may also be used by applications to store application data. The databases used by the applications may be different types of databases, such as a key-value store, an object store, or a conventional store backed by a file system.

The system 100 of FIG. 1 may be configured and operated in various ways to enable application of various methods and apparatuses described according to the present disclosure.

According to some embodiments, as shown in FIG. 2 , a memory reuse method for a computational graph including multiple subgraphs is provided, including: step S201, allocating multiple memory blocks accordingly for multiple first tensors of a first subgraph that is first executed among multiple subgraphs, each of the multiple memory blocks corresponding to respective memory block information and reuse mark information, the memory block information including an address range and a memory size of the corresponding memory block, the reuse mark information including a first mark for recording a reusable memory size in the corresponding memory block; step S202, for each second subgraph executed after the first subgraph among the multiple subgraphs, respectively performing the following first operations: step S2021, resetting the value of the first mark of each memory block in the current multiple memory blocks to a preset value, the preset value table Indicates that all memories in the corresponding memory block can be reused; and step S2022, perform the following second operation for each second tensor of the second sub-graph in turn: step S2022-1, based on the memory size required by the second tensor and the current value of the first tag of each memory block, obtain the reusable memory block of the second tensor in the current multiple memory blocks; step S2022-2, in response to obtaining the reusable memory block of the second tensor, based on the memory size required by the second tensor, the address range of the reusable memory block and the current value of the first tag, determine the memory space reused by the second tensor in the reusable memory block; and step S2022-3, based on the memory space reused by the second tensor, update the value of the first tag of the reusable memory block.

Therefore, by marking each allocated memory block corresponding to the previous subgraph, when allocating memory for each tensor of the next subgraph, first determine whether there is a reusable memory block in the allocated memory block based on the mark of the allocated memory block; if so, reuse the memory space therein. Since each subgraph runs sequentially, memory reuse between different subgraphs will not cause data overwrite problems. Through the above method, memory reuse between different subgraphs can be achieved, avoiding the problem of large overall memory usage when allocating memory for multiple subgraphs, and easy memory overflow when there are many subgraphs or large tensor scales.

In some embodiments, the multiple subgraphs described above may be run on a CPU or a GPU.

In some embodiments, the memory allocation for the above-mentioned multiple sub-graphs may be the allocation of CPU memory space or GPU memory space (ie, video memory).

In some embodiments, a corresponding memory block may be allocated to each first tensor in a memory pool of a CPU or a GPU.

In some embodiments, allocating multiple memory blocks accordingly for multiple first tensors of a first subgraph that is first executed among multiple subgraphs may be allocating a memory block of a preset memory size to each first tensor, wherein the preset memory size is greater than or equal to the memory size required for each first tensor.

In some embodiments, the memory size of each memory block in the plurality of memory blocks may be determined based on a required memory size of a corresponding tensor.

Therefore, by allocating a memory block to each tensor according to the actual memory size required by each tensor, the used memory can be further saved and the risk of memory overflow can be avoided.

In some embodiments, each memory block in the plurality of memory blocks corresponds to respective memory block information and reuse mark information.

In some embodiments, the memory block information may include an address range and a memory size of the corresponding memory block.

In some embodiments, the memory block information may also include identification information of the memory block, data type of data stored in the current memory block, and other information.

In some embodiments, the reuse mark information may include a first mark for recording the size of the memory that has been reused in the corresponding memory block.

In some exemplary embodiments, the first mark may be an unused address offset (unuse_offset), that is, a relative address, which may be used to indicate the currently occupied space in the corresponding memory block.

Before allocating memory for each second sub-graph, the value of the first mark of each memory block in the currently existing multiple memory blocks can be reset to zero (i.e., the preset value). That is, the first mark indicates that the memory space in each current memory block is not reused by the tensor data of the current second sub-graph.

Subsequently, for each second tensor in the current second subgraph, according to the memory size required by the second tensor, a reusable memory block with sufficient remaining reusable memory can be found in the above-mentioned multiple memory blocks, and an address range can be determined in the memory block to serve as the memory space reused by the second tensor.

The remaining reusable memory in each memory block can be determined by the memory size of the memory block and the current value of the first tag, for example, by subtracting the current value of the first tag from the memory size of the memory block to obtain the remaining reusable memory in the memory block.

In some exemplary embodiments, the first mark may also be the size of the remaining reusable memory space in the corresponding memory block.

Before allocating memory for each second sub-graph, the value of the first mark of each memory block in the currently existing multiple memory blocks can be reset to the memory size of each memory block (i.e., the preset value). That is, the first mark indicates that the memory space in each current memory block is not reused by the tensor data of the current second sub-graph.

Subsequently, for each second tensor in the current second subgraph, according to the memory size required by the second tensor, a reusable memory block with sufficient remaining reusable memory can be found in the above-mentioned multiple memory blocks, and an address range can be determined in the memory block to serve as the memory space reused by the second tensor.

In some embodiments, after each reused memory space of a second tensor is determined, the value of the first tag of the reusable memory block is updated, thereby updating the remaining reusable memory space size of the memory block.

In some exemplary embodiments, when the first tag is an unoccupied address offset, the value of the first tag can be updated by adding the size of the memory space reused by the second tensor to the current value.

In some exemplary embodiments, when the first tag is the size of the remaining reusable memory space in the corresponding memory block, the value of the first tag can be updated by subtracting the size of the memory space reused by the second tensor from the current value.

In some embodiments, when the memory reuse of the next second tensor is continued, the remaining reusable memory can be determined by the updated value of the first mark of the memory block.

In some embodiments, when the remaining reusable memory space in all memory blocks cannot meet the memory space demand of the second tensor, a new memory block can be applied for in the above-mentioned memory pool to be allocated to the second tensor, and the relevant information of the memory block of the second tensor is recorded at the same time to update the information of the above-mentioned multiple memory blocks, so that in the memory reuse of the subsequent sub-graph, the memory block of the second tensor can also be reused.

In some embodiments, the memory block information and reuse mark information of each memory block in a plurality of memory blocks can be recorded in a linked list as an information block, and the information blocks of each memory block are arranged from small to large according to the memory size. Based on the memory size required for the second tensor and the current value of the first mark of each memory block, obtaining the reusable memory block of the second tensor in the current plurality of memory blocks can include: sequentially detecting whether the information of each memory block in the current linked list satisfies a first preset condition, the first preset condition including that the reusable memory size of the corresponding memory block is greater than the memory size required for the second tensor; and in response to detecting a first memory block that satisfies the first preset condition, determining the first memory block as a reusable memory block for the second tensor.

Therefore, by storing the information blocks of each memory block in a linked list in order, and detecting the information of each memory block in order from small to large memory space, until reusable memory space is detected, the detection efficiency can be further improved. At the same time, it can also avoid using a larger memory space for a smaller-scale tensor, thereby improving the reuse rate of the allocated memory.

In some embodiments, a linked list for recording the information of the memory blocks may be provided, wherein the information of each memory block may be uniformly recorded in the linked list in the form of an information block.

In some embodiments, the information block of each memory block may include the above memory block information and reuse mark information. The basic type of the linked list may be defined as a structure Buffer for storing the above information blocks. The above linked list mem_pool may be represented as:

std::list<Buffer>mem_pool;

struct Buffer{

NDArray pool;

size_t unuse_offset = 0;

};

Among them, Buffer represents the structure Buffer used to record the above information block, NDArray pool represents the memory block information, unuse_offset represents the first mark (unoccupied address offset), and its initial value is set to 0.

In some embodiments, the multiple information blocks in the above linked list are arranged from small to large according to the memory size of each memory block.

In some embodiments, each memory block can be tested according to the arrangement order of each memory block in the linked list to determine whether it meets the first preset condition, that is, whether the reusable memory size of the memory block is larger than the memory size required by the second tensor, until a memory block that meets the above-mentioned first preset condition is detected.

In some embodiments, if no memory block that meets the first preset condition is detected after traversing the information blocks of all memory blocks, a new memory block can be applied for in the memory pool to be allocated to the second tensor. At the same time, the information block of the memory block of the second tensor is recorded, and the information block is inserted into the corresponding position in the linked list according to the memory size of the corresponding memory block to update the linked list, so that the memory block of the second tensor can also be reused in the memory reuse of the subsequent sub-graph.

In some embodiments, the reuse mark information may also include a second mark, and the second mark is used to indicate whether the corresponding memory block can be reused by the second tensor of the second subgraph that is undergoing the first operation. The second operation may also include: in response to not obtaining a memory block that meets the first preset condition, allocating a second memory block for the second tensor from the unallocated memory space in the memory pool; and based on the memory size of the second memory block, inserting the information block of the second memory block into the linked list to obtain an updated linked list, wherein the current value of the second mark of the second memory block is set to the first value, and the first value is used to indicate that the corresponding memory block cannot be reused by the second tensor of the second subgraph that is undergoing the first operation.

Therefore, when a memory block that meets the first preset condition is not obtained, a new memory block is allocated from the unallocated part of the memory pool and allocated to the second tensor, and the information of the memory block is inserted into the linked list to update the linked list and improve the memory reuse rate of subsequent sub-graphs; at the same time, by setting the second mark to the first value, the problem of data overwrite caused by the reuse of the memory block in the subsequent tensor data in the current sub-graph is avoided, thereby improving the security and reliability of the data.

In some embodiments, the reuse mark information of the information block of each memory block may further include a second mark, and the second mark is used to indicate whether the corresponding memory block can be reused by the second tensor of the second subgraph that is currently performing the first operation (that is, the second subgraph that is currently performing memory allocation). The above linked list mem_pool can be expressed as:

std::list<Buffer>mem_pool;

struct Buffer{

NDArray pool;

bool is_same_subgraph=false;

size_t unuse_offset = 0;

};

Among them, Buffer represents a structure Buffer used to record the above information block, NDArray pool represents memory block information, unuse_offset represents a first tag (unoccupied address offset), whose initial value is set to 0, and is_same_subgraph represents a second tag, whose initial value can be set to false (second value), which is used to indicate that the corresponding memory block can be reused by the second tensor of the second subgraph that is performing the first operation.

When the newly allocated memory block is inserted into the linked list, the second flag of the memory block is set to the first value (for example, true), so as to avoid the subsequent second tensor in the second subgraph reusing the memory block, causing the problem of data overwriting of the second subgraph during operation.

In some embodiments, the first preset condition may further include that a current value of a second tag of the corresponding memory block is a second value, and the second value indicates that the corresponding memory block can be reused by a second tensor of a second subgraph that is undergoing the first operation.

Therefore, by detecting whether the second flag of each memory block is the second value, the problem of data overwrite caused by reusing the memory block that may have just been inserted into the linked list for storing tensor data of the same subgraph can be avoided, thereby improving data security and reliability.

In some embodiments, the first operation may further include: before performing the second operation on each second subgraph, resetting the second mark of each memory block in the current linked list to a second value.

Therefore, by resetting the second mark of the memory block contained in the current linked list to the second value before allocating memory to each subgraph, the subgraph to be allocated memory can reuse all the memory blocks in the current linked list, further improving the reuse rate of the memory block.

In some embodiments, after each tensor data in each subgraph obtains the memory block used to cache the tensor data through the above method, each subgraph can be executed in sequence on the corresponding running device (such as CPU or GPU), so that there is no need to allocate memory for the data of each subgraph during the running process of each subgraph. While ensuring the execution efficiency of multiple subgraphs, the risk of memory overflow is further reduced through the above method.

FIG3 shows a flowchart of a method for memory reuse of a computation graph including multiple subgraphs according to an exemplary embodiment of the present disclosure.

In some exemplary embodiments, as shown in FIG3 , a memory reuse method for a computational graph including multiple subgraphs is provided, which may include: step S301, creating a global ordered linked list mem_pool to manage memory blocks; step S302, allocating memory for each first tensor of the first subgraph, and recording the information block of each memory block in the linked list mem_pool; step S303, resetting all unuse_offsets in the current linked list mem_pool to 0, and resetting all is_same_subgraphs to false; step S304, for each tensor in the next subgraph, performing the following operations: step S305, searching for a reusable memory block in the linked list mem_pool; step S306, in response to finding a reusable memory block, based on the memory size required for the tensor, the location of the reusable memory block The address range and the current value of unuse_offset are used to determine the memory space reused by the tensor in the reusable memory block; step S307, update the unuse_offset of the reusable memory block in the linked list mem_pool, and execute step S305 for the next tensor in the subgraph; step S308, in response to not finding a reusable memory block, allocate a memory block for the tensor from the unallocated memory space in the memory pool; step S309, insert the information block of the memory block into the linked list mem_pool, reset is_same_subgraph of the memory block to true, and execute step S305 for the next tensor in the subgraph; step S310, in response to each tensor of the current subgraph having executed the above-mentioned memory allocation operation, execute step S303, and execute step S304 for the next subgraph.

In some embodiments, as shown in FIG. 4 , a memory reuse device 400 for a computation graph including multiple subgraphs is provided, the device comprising: an allocation unit 410, configured to allocate multiple memory blocks correspondingly to multiple first tensors of a first subgraph that is first executed in multiple subgraphs, each of the multiple memory blocks corresponding to respective memory block information and reuse mark information, the memory block information comprising an address range and a memory size of the corresponding memory block, the reuse mark information comprising a first mark for recording the size of the memory that has been reused in the corresponding memory block; an execution unit 420, configured to respectively perform the following first operation for each second subgraph executed after the first subgraph in the multiple subgraphs, the execution unit 420 comprising: a first setting subunit 421, configured to reset the value of the first mark of each memory block in the current multiple memory blocks to zero; and an execution subunit 422, The subunit 422 is configured to perform the following second operation for each second tensor of the second subgraph in turn: an acquisition module 422-1 is configured to acquire a reusable memory block of the second tensor in the current multiple memory blocks based on the memory size required by the second tensor and the reusable memory size of each memory block, wherein the reusable memory size of each memory block is determined based on the memory size of the corresponding memory block and the current value of the first tag; a determination module 422-2 is configured to determine the memory space reused by the second tensor in the reusable memory block in response to acquiring the reusable memory block of the second tensor based on the memory size required by the second tensor, the address range of the reusable memory block and the current value of the first tag; and a first update module 422-3 is configured to update the value of the first tag of the reusable memory block based on the memory space reused by the second tensor.

Among them, the operations performed by unit 410, unit 420, sub-unit 421, sub-unit 422 and module 422-1 to module 422-3 in the above-mentioned memory reuse device 400 for a computational graph including multiple sub-graphs are similar to the operations of steps S201, step S202, step S2021, step S2022, step S2022-1 to step S2022-3 in the above-mentioned memory reuse method for a computational graph including multiple sub-graphs, and are not repeated here.

In some embodiments, the memory block information and reuse mark information of each memory block in a plurality of memory blocks can be recorded in a linked list as an information block, and the information blocks of each memory block are arranged from small to large according to the memory size. The acquisition module can be further configured to: detect in turn whether the information of each memory block in the current linked list satisfies a first preset condition, the first preset condition including that the reusable memory size of the corresponding memory block is greater than the memory size required by the second tensor; and in response to detecting a first memory block that satisfies the first preset condition, determine the first memory block as a reusable memory block for the second tensor.

In some embodiments, the reuse mark information also includes a second mark, and the second mark is used to indicate whether the corresponding memory block can be reused by the second tensor of the second subgraph that is undergoing the first operation. The execution subunit may also include: an allocation module, configured to allocate a second memory block for the second tensor from the unallocated memory space in the memory pool in response to not obtaining a memory block that meets the first preset condition; and a second update module, configured to insert the information block of the second memory block into the linked list based on the memory size of the second memory block to obtain an updated linked list, wherein the current value of the second mark of the second memory block is set to the first value, and the first value is used to indicate that the corresponding memory block cannot be reused by the second tensor of the second subgraph that is undergoing the first operation.

In some embodiments, the first preset condition may further include that a current value of a second tag of the corresponding memory block is a second value, and the second value indicates that the corresponding memory block can be reused by a second tensor of a second subgraph that is undergoing the first operation.

In some embodiments, the execution unit may further include: a second setting subunit configured to reset the second mark of each memory block in the current linked list to a second value before executing the second operation on each second subgraph.

In some embodiments, the memory size of each memory block in the plurality of memory blocks may be determined based on a required memory size of a corresponding tensor.

According to an embodiment of the present disclosure, an electronic device, a readable storage medium and a computer program product are also provided.

With reference to Fig. 5, the structural block diagram of the electronic device 500 that can be used as the server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer equipment, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present disclosure described and/or required herein.

As shown in Figure 5, electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In RAM 503, various programs and data required for the operation of electronic device 500 can also be stored. Computing unit 501, ROM 502 and RAM 503 are connected to each other via bus 504. Input/output (I/O) interface 505 is also connected to bus 504.

Multiple components in the electronic device 500 are connected to the I/O interface 505, including: an input unit 506, an output unit 507, a storage unit 508, and a communication unit 509. The input unit 506 can be any type of device that can input information to the electronic device 500. The input unit 506 can receive input digital or character information and generate key signal input related to user settings and/or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and/or a remote controller. The output unit 507 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video/audio output terminal, a vibrator, and/or a printer. The storage unit 508 can include but is not limited to a disk, an optical disk. The communication unit 509 allows the electronic device 500 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and/or a chipset, such as a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and/or the like.

The computing unit 501 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as the above-mentioned memory reuse method for a computing graph including multiple subgraphs. For example, in some embodiments, the above-mentioned memory reuse method for a computing graph including multiple subgraphs may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed on the electronic device 500 via ROM 502 and/or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of the above-mentioned memory reuse method for a computing graph including multiple subgraphs may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured in any other appropriate manner (e.g., by means of firmware) to execute the above-mentioned memory reuse method for a computation graph including multiple subgraphs.

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and/or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions/operations specified in the flow chart and/or block diagram. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document is not limited here.

Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the claims after authorization and their equivalent scope. Various elements in the embodiments or examples may be omitted or replaced by their equivalent elements. In addition, each step may be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples may be combined in various ways. It is important that with the evolution of technology, many of the elements described herein may be replaced by equivalent elements that appear after the present disclosure.

Claims (15)

1. A memory multiplexing method for a computational graph comprising a plurality of subgraphs, the method comprising:

Correspondingly distributing a plurality of memory blocks for a plurality of first tensors of a first sub-graph which is executed first in the plurality of sub-graphs, wherein each memory block in the plurality of memory blocks corresponds to respective memory block information and multiplexing mark information, the memory block information comprises an address range and a memory size of the corresponding memory block, and the multiplexing mark information comprises a first mark used for recording the reusable memory size in the corresponding memory block;

for each second sub-graph of the plurality of sub-graphs, which is executed after the first sub-graph, respectively executing the following first operations:

resetting the value of the first flag of each memory block in the current plurality of memory blocks to a preset value, wherein the preset value represents that all memories in the corresponding memory blocks can be multiplexed; and

For each second tensor of the second sub-graph in turn, the following second operation is performed:

Acquiring reusable memory blocks of the second tensor from the plurality of memory blocks based on the memory size required by the second tensor and the current value of the first mark of each memory block;

In response to obtaining the reusable memory block of the second tensor, determining a memory space for multiplexing the second tensor in the reusable memory block based on the required memory size of the second tensor, the address range of the reusable memory block and the current value of the first flag; and

And updating the value of the first mark of the reusable memory block based on the memory space multiplexed by the second tensor.

2. The method of claim 1, wherein the respective memory block information and multiplexing flag information of each of the plurality of memory blocks are recorded as one information block in a linked list, and the information blocks of the respective memory blocks are arranged from small to large according to the memory size, and the obtaining the reusable memory block of the second tensor in the current plurality of memory blocks based on the memory size required by the second tensor and the current value of the first flag of the respective memory block comprises:

Sequentially detecting whether the information of each memory block in the current linked list meets a first preset condition, wherein the first preset condition comprises that the size of the reusable memory of the corresponding memory block is larger than the size of the memory required by the second tensor; and

And in response to detecting the first memory block meeting the first preset condition, determining the first memory block as the reusable memory block of the second tensor.

3. The method of claim 2, wherein the multiplexing flag information further comprises a second flag indicating whether the corresponding memory block can be multiplexed by a second tensor of a second sub-graph that is performing the first operation, the second operation further comprising:

In response to not obtaining the memory blocks meeting the first preset condition, distributing a second memory block for the second tensor from unallocated memory spaces in the memory pool; and

And inserting the information block of the second memory block into the linked list based on the memory size of the second memory block to acquire an updated linked list, wherein the current value of the second flag of the second memory block is set to be a first value, and the first value is used for indicating that the corresponding memory block cannot be multiplexed by the second tensor of the second sub-graph in which the first operation is being performed.

4. The method of claim 3, wherein the first preset condition further comprises a current value of a second flag of the corresponding memory block being a second value indicating that the corresponding memory block may be multiplexed by a second tensor of a second sub-graph in which the first operation is being performed.

5. The method of claim 4, wherein the first operation further comprises:

and before the second operation is executed for each second sub-graph, resetting the second mark of each memory block in the current linked list to the second value.

6. The method of any of claims 1-5, wherein a memory size of each memory block of the plurality of memory blocks is determined based on a desired memory size of a corresponding tensor.

7. A memory multiplexing device for a computational graph comprising a plurality of subgraphs, the device comprising:

An allocation unit configured to allocate a plurality of memory blocks, for a plurality of first tensors of a first sub-graph that is executed first among the plurality of sub-graphs, respectively, each memory block of the plurality of memory blocks corresponding to respective memory block information including an address range and a memory size of the corresponding memory block and multiplexing flag information including a first flag for recording a reusable memory size in the corresponding memory block;

an execution unit configured to perform the following first operations, respectively, for each second sub-graph of the plurality of sub-graphs, which is executed after the first sub-graph, the execution unit including:

a first setting subunit configured to reset a value of a first flag of each memory block of the current plurality of memory blocks to a preset value, where the preset value indicates that all memories in the corresponding memory block can be multiplexed; and

An execution subunit configured to perform, for each second tensor of the second sub-graph in turn, a second operation of:

an obtaining module configured to obtain a reusable memory block of the second tensor from the plurality of memory blocks at present based on a required memory size of the second tensor and a current value of a first flag of each memory block;

a determining module configured to determine, in response to acquiring the reusable memory block of the second tensor, a memory space multiplexed by the second tensor in the reusable memory block based on a required memory size of the second tensor, an address range of the reusable memory block, and a current value of the first flag; and

And a first updating module configured to update a value of a first flag of the reusable memory block based on the memory space multiplexed by the second tensor.

8. The apparatus of claim 7, wherein the respective memory block information and multiplexing flag information for each of the plurality of memory blocks are recorded as one information block in a linked list, and the information blocks for the respective memory blocks are arranged in a memory size from small to large, the acquisition module being further configured to:

Sequentially detecting whether the information of each memory block in the current linked list meets a first preset condition, wherein the first preset condition comprises that the size of the reusable memory of the corresponding memory block is larger than the size of the memory required by the second tensor; and

And in response to detecting the first memory block meeting the first preset condition, determining the first memory block as the reusable memory block of the second tensor.

9. The apparatus of claim 8, wherein the multiplexing flag information further comprises a second flag indicating whether a corresponding memory block can be multiplexed by a second tensor of a second sub-graph that is performing the first operation, the execution subunit further comprising:

The allocation module is configured to allocate a second memory block for the second tensor from unallocated memory spaces in the memory pool in response to not acquiring the memory block meeting the first preset condition; and

And a second updating module configured to insert an information block of the second memory block into the linked list based on a memory size of the second memory block to obtain an updated linked list, where a current value of a second flag of the second memory block is set to a first value, and the first value is used to indicate that the corresponding memory block cannot be multiplexed by a second tensor of a second sub-graph that is performing the first operation.

10. The apparatus of claim 9, wherein the first preset condition further comprises a current value of a second flag of the respective memory block being a second value indicating that the respective memory block may be multiplexed by a second tensor of a second sub-graph that is performing the first operation.

11. The apparatus of claim 10, the execution unit further comprising:

And the second setting subunit is configured to reset the second flag of each memory block in the current linked list to the second value before the second operation is performed on each second sub-graph.

12. The apparatus of any of claims 7-11, wherein a memory size of each memory block of the plurality of memory blocks is determined based on a desired memory size of a respective tensor.

13. An electronic device, comprising:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein the method comprises the steps of

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

14. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-6.

15. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method of any of claims 1-6.