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CN118658502B - A high-precision and low-power power-off detection circuit - Google Patents

A high-precision and low-power power-off detection circuit Download PDF

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Publication number
CN118658502B
CN118658502B CN202410749203.4A CN202410749203A CN118658502B CN 118658502 B CN118658502 B CN 118658502B CN 202410749203 A CN202410749203 A CN 202410749203A CN 118658502 B CN118658502 B CN 118658502B
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tube
pmos
power
electrode
twenty
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CN118658502A (en
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黄轶
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Shanghai Kunang Electronic Technology Co ltd
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Shanghai Kunang Electronic Technology Co ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24Resetting means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

本发明提供了一种高精度低功耗的下电检测电路,包括:电流产生模块,用于在电源下电过程中,当检测电源电压低于预下电阈值电压时产生参考电流、下电电流和恢复电流;电流比较模块,连接至电流产生模块,用于在电源下电过程中,当检测电源电压低于预下电阈值电压后,比较参考电流和下电电流,产生第一输出信号;比较参考电流和恢复电流,产生第二输出信号;控制与输出模块,连接于电流产生模块和电流比较模块;输入第一输出信号和第二输出信号;产生开关控制信号、预下电信号和恢复信号,并输出下电信号;且开关控制信号和预下电信号输入至电流产生模块。

The present invention provides a high-precision, low-power power-off detection circuit, comprising: a current generating module, used for generating a reference current, a power-off current and a recovery current when a power supply voltage is detected to be lower than a pre-power-off threshold voltage during a power-off process; a current comparison module, connected to the current generating module, used for comparing a reference current and a power-off current to generate a first output signal when a power supply voltage is detected to be lower than a pre-power-off threshold voltage during a power-off process; comparing a reference current and a recovery current to generate a second output signal; a control and output module, connected to the current generating module and the current comparison module; inputting the first output signal and the second output signal; generating a switch control signal, a pre-power-off signal and a recovery signal, and outputting a power-off signal; and the switch control signal and the pre-power-off signal are input to the current generating module.

Description

High-precision low-power-consumption power-down detection circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-precision low-power-consumption power-down detection circuit.
Background
With the development of mixed signal integrated circuits that integrate power management and emerging non-volatile memory technologies, a brown-out-detection (BOD) circuit plays a critical role in monitoring the supply voltage. The BOD module responds to the power down event caused by the interference to ensure that the system operates normally at a sufficient power supply voltage level. When the power supply voltage drops below the minimum required voltage level, a reset signal is generated to ensure system safety.
In the conventional power-down detection circuit, a power-down detection scheme is mainly implemented based on a band gap reference and a comparator as shown in fig. 1, and power-down detection is implemented based on a delay unit and a diode as shown in fig. 2. In the scheme shown in fig. 1, when the power supply voltage starts to drop from the normal power supply voltage, the power supply voltage is divided by two resistors to obtain a reference voltage related to the power supply voltage, and meanwhile, the band gap reference generates a reference voltage which is not influenced by the power supply voltage and the temperature. The two voltages are compared by a voltage comparator which outputs a low level when the supply voltage drops to a certain threshold. The power-down detection structure can accurately realize power-down detection, but the band gap reference, the resistor voltage divider and the voltage comparator consume a large amount of static power consumption and circuit area. In the scheme shown in fig. 2, in the power-on stage, the capacitor formed by the NMOS transistor N3 is fully charged by the current mirror circuit formed by the NMOS transistor N1, the NMOS transistor N2, the PMOS transistor P1 and the PMOS transistor P2. In the power-down stage, after the power supply voltage is lower than the threshold voltages of the first diode D1 and the second diode D2, the PMOS transistor P4 is turned off, and the gate of the PMOS transistor P3 is pulled to a low potential, so that the PMOS transistor P3 is turned on, the charge at the gate end of the NMOS transistor N3 is released, and the output is turned over by the inverter. The diode of the circuit can be replaced by a MOS tube with interconnected grid and drain electrodes. The circuit has simple structure and relatively low power consumption, but the precision is limited by the threshold voltage of the diode, and is sensitive to the process angle, the temperature and the power-down time.
In view of this, it is necessary to provide a novel high-precision low-power-consumption power-down detection circuit to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a high-precision low-power-consumption power-down detection circuit which at least can solve the problems of large area, high power consumption and low reliability of the existing power-down detection circuit.
In order to achieve the above object, the present invention provides a high-precision low-power-consumption power-down detection circuit, comprising:
The current generation module is used for generating reference current, power-down current and recovery current when the detected power supply voltage is lower than the pre-power-down threshold voltage in the power-down process of the power supply; the reference current is irrelevant to absolute temperature and is irrelevant to power supply voltage, the power-down current and the recovery current are irrelevant to absolute temperature and are relevant to power supply voltage, and output ports corresponding to the reference current, the power-down current and the recovery current are respectively marked as a V IR end, a V IB end and a V IRE end;
the current comparison module is connected to the current generation module and is used for comparing the reference current with the power-down current to generate a first output signal, wherein the port is marked as an OUT B end;
The control and output module is connected with the current generation module and the current comparison module, inputs the first output signal and the second output signal, generates a switch control signal, a Pre-power-down electric signal and a recovery signal, and outputs a power-down electric signal, wherein the switch control signal and the Pre-power-down electric signal are input to the current generation module, and output ports corresponding to the switch control signal, the Pre-power-down electric signal and the recovery signal are respectively marked as a B end, a Pre end and a Rec end;
in the power-down process of the power voltage, when the power voltage is lower than the pre-power-down threshold voltage, the control and output module generates the pre-power-down electric signal, the switch control signal jumps to start the current generation module and the current comparison module;
In the power-down process of the power voltage, if the power voltage returns to a normal state after being lower than a pre-power-down threshold voltage and is higher than a recovery threshold voltage, the recovery current exceeds the reference current, the second output signal is output to jump, the control and output module generates the recovery signal, and the switch control signal is turned over, so that the current generation module and the current comparison module are turned off, and the circuit enters a voltage stable state;
Wherein the pre-power-down threshold voltage, the power-down threshold voltage, and the recovery threshold voltage satisfy a relationship V BOD<VPre-BOD<VREC, wherein V BOD represents the power-down threshold voltage, V Pre-BOD represents the pre-power-down threshold voltage, and V REC represents the recovery threshold voltage.
In an alternative scheme, the current generation module comprises a reference current generation circuit, a reference current generation circuit and a reference current generation circuit, wherein the reference current generation circuit is used for generating the reference current in the power-down process of the power supply voltage;
and the power-down and recovery current generating circuit is used for generating the power-down current and the recovery current in the power-down process of the power supply voltage.
In an alternative scheme, the reference current generating circuit comprises a first PNP transistor, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube;
The grid electrode of the first PMOS tube P1 is connected to the Pre end, the drain electrode of the first PMOS tube P1 is connected to the control and output module, and the source electrode of the first PMOS tube P1 is connected to the grid electrode and the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the source electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the eleventh PMOS tube; the source terminal of the second PMOS tube is connected to the power supply voltage VDD, the source terminal of the third PMOS tube is connected to the power supply voltage VDD, the drain terminal of the third PMOS tube is connected to the source terminal of the fifth PMOS tube, the gate terminal of the fourth PMOS tube is connected to the drain terminal of the first NMOS tube, the gate terminal of the fifth PMOS tube is connected to the drain terminal of the first NMOS tube and the gate and drain terminal of the second NMOS tube, the source terminal of the first NMOS tube is connected to one end of the first resistor, the other end of the first resistor is grounded, the source terminal of the second NMOS tube is grounded, the source terminal of the sixth PMOS tube is connected to the power supply voltage, the drain terminal of the seventh PMOS tube is connected to one end of the second resistor, the other end of the second resistor is connected to the gate terminal of the first PNP transistor and the third NMOS tube, the source terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS tube is connected to the drain terminal of the eighth PMOS tube is connected to the source terminal of the eighth PMOS tube, the drain electrode is connected to the drain electrode of the eleventh PMOS tube and the source electrode of the twelfth PMOS tube, the source electrode of the eleventh PMOS tube is connected to the power supply voltage, the grid electrode of the twelfth PMOS tube is connected to the end B, the drain electrode is connected to the drain electrode and the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fifth NMOS tube is grounded, the drain electrode is connected to the grid electrode and the drain electrode of the thirteenth PMOS tube, the end point is the VIR end, and the source electrode of the thirteenth PMOS tube is connected to the power supply voltage.
In an alternative scheme, the power-down and recovery current generation circuit comprises a second PNP transistor, a third resistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty first PMOS transistor, a twenty second PMOS transistor and a twenty third PMOS transistor;
The source electrode of the fourteenth PMOS tube is connected to the power supply voltage, and the grid electrode and the drain electrode of the fourteenth PMOS tube are connected to the source electrode of the fifteenth PMOS tube and the grid electrode of the nineteenth PMOS tube; the drain electrode of the fifteenth PMOS transistor is connected to one end of the third resistor, the other end of the third resistor is connected to the emitter electrode of the second PNP transistor and the drain electrode of the sixth NMOS transistor, the base electrode and the collector electrode of the second PNP transistor are grounded, the source electrode of the sixth PMOS transistor is grounded, the drain electrode of the seventeenth PMOS transistor is connected to the drain electrode of the seventeenth PMOS transistor, the gate electrode of the seventeenth PMOS transistor is connected to the B end, the source electrode of the seventeenth PMOS transistor is connected to the gate and the drain electrode of the sixteenth PMOS transistor and the gate electrode of the twenty first PMOS transistor and the gate electrode of the twenty second PMOS transistor, the source electrode of the sixteenth PMOS transistor is connected to a power supply voltage, the source electrode of the eighteenth PMOS transistor is connected to the power supply voltage, the drain electrode of the nineteenth PMOS transistor is connected to the drain electrode of the nineteenth PMOS transistor and the source electrode of the twenty eighth PMOS transistor, the gate electrode of the seventeenth PMOS transistor is connected to the B end, the drain electrode of the seventeenth PMOS transistor is connected to the power supply voltage, the drain electrode of the seventeenth PMOS transistor is connected to the drain electrode of the twenty eighth PMOS transistor.
In an alternative scheme, the control and output module comprises a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirty-third PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first buffer, a second buffer and a first NAND gate;
The drain electrode and the source electrode of the twenty-seventh PMOS tube are connected to the power supply voltage, and the grid electrode is connected to the drain electrode and the grid electrode of the twelfth NMOS tube; the source electrode of the thirteenth NMOS tube is connected to the drain electrode and the grid electrode of the thirteenth NMOS tube, the end points are connected to the current generating module, the source electrode of the thirteenth NMOS tube is connected to the drain electrode and the grid electrode of the fourteenth NMOS tube, the source electrode of the thirteenth NMOS tube is grounded, the source electrode of the twenty eighth PMOS tube is connected to the power supply voltage, the grid electrode and the drain electrode of the twenty ninth PMOS tube are connected to the source electrode of the twenty ninth PMOS tube, the drain electrode and the grid electrode of the twenty ninth PMOS tube are connected to the grid electrode of the fifteenth NMOS tube and the source electrode of the thirty second PMOS tube, the source electrode and the drain electrode of the fifteenth NMOS tube are grounded, the source electrode of the thirty PMOS tube is connected to the power supply voltage, the grid electrode and the drain electrode of the thirty first PMOS tube are connected to the grid electrode of the sixteenth PMOS tube and the source electrode of the thirty third PMOS tube, the drain electrode and the source electrode of the thirty fifth PMOS tube are connected to the source electrode of the thirty eighth PMOS tube, the drain electrode of the sixteenth NMOS tube and the drain electrode of the thirty eighth PMOS tube are connected to the power supply voltage, the drain electrode of the thirty second PMOS tube is connected to the drain electrode of the thirty third PMOS tube is connected to the power supply voltage, the drain electrode of the thirty-third PMOS tube is connected to the source voltage, the source electrode is connected to the source electrode of the source tube is connected to the source electrode of the source, The drain electrode of the eighteenth NMOS tube, the drain electrode of the thirty-sixth PMOS tube and the input end of the fourth inverter; the grid electrode of the thirty-fifth PMOS tube is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the nineteenth NMOS tube, the drain electrode of the twentieth NMOS tube, The drain electrode of the thirty-seventh PMOS tube and the input end of the second inverter; the source electrode of the thirty-sixth PMOS tube is connected to the power supply voltage, and the grid electrode is connected to the end B; the seventeenth NMOS tube has its gate connected to the On signal of external input and its source grounded, the eighteenth NMOS tube has its gate connected to the Rec terminal and its source grounded, the thirty seventh PMOS tube has its source connected to the power supply voltage and its gate connected to the B terminal, the nineteenth NMOS tube has its gate connected to the On signal of external input and its source grounded, the twenty-eighth NMOS tube has its gate connected to the Rec terminal and its source grounded, the first inverter has its input connected to the OUT B terminal and its output connected to the input terminal of the first buffer, the first buffer has its output connected to the lower signal, the second inverter has its output connected to the input terminal of the third inverter, its output connected to one input terminal of the first NAND gate, its other input terminal connected to the B terminal, its output terminal being the Pre terminal, its output terminal connected to the fifth inverter, its output terminal being the output terminal of the eighth buffer, its output terminal being the output terminal of the eighth inverter, its output terminal being the output terminal of the eighth buffer, its output terminal being the output terminal of the eighth buffer, The drain electrode of the thirty-eighth PMOS tube is connected to the grid electrode and the drain electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube and the input end of the eighth inverter, the source electrode of the twenty-first NMOS tube is connected to the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-second NMOS tube is connected to the drain electrode of the twenty-third NMOS tube, the source electrode of the twenty-third NMOS tube is grounded, the source electrode and the drain electrode of the twenty-fourth NMOS tube are grounded, and the output end of the eighth inverter is the Rec end.
In an alternative scheme, the current comparison module comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube and a twenty-sixth PMOS tube;
The grid electrode of the twenty-fourth PMOS tube is connected to the V IR end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube, the end points are the OUT B end, the grid electrode of the ninth NMOS tube is connected to the V IB end, the source electrode is grounded, the grid electrode of the tenth NMOS tube is connected to the B end, the source electrode is grounded, the grid electrode of the twenty-fifth PMOS tube is connected to the B_end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the twenty-sixth PMOS tube and the drain electrode of the eleventh NMOS tube, the end points are the OUT R end, the grid electrode of the twenty-sixth PMOS tube is connected to the V IR end, the source electrode of the eleventh NMOS tube is connected to the V IRE end, and the source electrode is grounded.
In an alternative, the first inverter, the second inverter, the fourth inverter, the seventh inverter, and the eighth inverter are schmitt inverters.
The invention has the beneficial effects that:
The invention realizes that the power-down detection circuit generates a reliable power-down signal when the power supply voltage drops below the minimum required voltage (power-down threshold voltage) level from the normal working voltage. The main function of the power-down signal is to reset the circuit, so that misoperation of the integrated circuit system caused by insufficient voltage is avoided.
Furthermore, when the power-down detection circuit of the invention works normally, the current generation module and the current comparison module are turned off, so that extremely low static power consumption can be realized.
Furthermore, the power-down detection circuit of the invention compares the reference current and the power-down current which have similar temperature characteristics and greatly different power supply voltage sensitivity, and the power-down threshold voltage is insensitive to the process angle and the temperature (improves the accuracy of the power-down threshold voltage) and is insensitive to the power supply voltage, the power-down speed and the power-down time.
Furthermore, the power-down and recovery current generation circuit of the power-down detection circuit and the logic control signal thereof can prevent the circuit from causing large static power consumption under special conditions.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
FIG. 1 is a high-precision power-down detection circuit in the prior art.
FIG. 2 is a low-consumption power-down detection circuit in the prior art.
Fig. 3 is a circuit diagram of a high-precision low-power-consumption power-down detection circuit according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a transient simulation result of normal power down of the power down detection circuit according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a transient simulation result of a specific power-down of the power-down detection circuit according to an embodiment of the invention.
FIG. 6 is a schematic diagram of the simulation results of the process corner and temperature of the slow power down detection circuit according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of the simulation results of the process corner and temperature of the fast power-down detection circuit according to an embodiment of the invention.
Fig. 8a is a schematic diagram of a monte carlo simulation result (power-down threshold voltage) under a slow condition of the power-down detection circuit according to an embodiment of the present invention.
Fig. 8b is a schematic diagram of a monte carlo simulation result (power-down threshold voltage) under a fast power-down detection circuit according to an embodiment of the present invention.
FIG. 9a is a diagram illustrating a variation of the power-down threshold voltage of the power-down detection circuit according to an embodiment of the invention.
FIG. 9b is a diagram illustrating a variation of the power-down threshold voltage of the power-down detection circuit according to an embodiment of the invention.
Reference numerals illustrate:
10-power-down detection circuit, 100-current generation module, 101-reference current generation circuit, 102-power-down and recovery current generation circuit, 200-current comparison module and 300-control and output module.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
Referring to fig. 3 to 9, the present embodiment provides a power-down detection circuit 10 with high accuracy and low power consumption, including:
The current generation module 100 is used for generating a reference current IR, a power-down current IB and a recovery current IRE when the detected power supply voltage VDD is lower than a pre-power-down threshold voltage in the power-down process of the power supply, wherein the reference current IR is irrelevant to absolute temperature and is irrelevant to the power supply voltage, the power-down current IB and the recovery current IRE are irrelevant to absolute temperature and are relevant to the power supply voltage, and output ports corresponding to the reference current IR, the power-down current IB and the recovery current IRE are respectively marked as a V IR end, a V IB end and a V IRE end;
A current comparing module 200, coupled to the current generating module 100, for comparing the reference current IR with the power-down current IB to generate a first output signal OUT B, which is denoted as an OUT B terminal, and comparing the reference current IR with the recovery current IRE to generate a second output signal OUT R, which is denoted as an OUT R terminal, when the detected power supply voltage VDD is lower than the pre-power-down threshold voltage during power-down;
The control and output module 300 is connected to the current generation module 100 and the current comparison module 200, inputs the first output signal OUT B and the second output signal OUT R, generates a switch control signal B, a Pre-power-down signal Pre and a recovery signal Rec, and outputs a power-down signal BOD, wherein the switch control signal B and the Pre-power-down signal Pre are input to the current generation module 100, and output ports corresponding to the switch control signal B, the Pre-power-down signal Pre and the recovery signal Rec are respectively marked as a B end, a Pre end and a Rec end;
During the power-down process of the power supply voltage, when the power supply voltage VDD is lower than the Pre-power-down threshold voltage, the control and output module 300 generates the Pre-power-down signal Pre, the switch control signal B jumps to start the current generation module 100 and the current comparison module 200;
During the power-down process of the power supply voltage, if the power supply voltage VDD returns to a normal state after being lower than the pre-power-down threshold voltage, and is higher than the recovery threshold voltage, the recovery current IRE exceeds the reference current IR, the second output signal OUT R is output to jump, the control and output module 300 generates a recovery signal Rec, the switch control signal B is turned over, so that the current generation module 100 and the current comparison module 200 are turned off, and the circuit enters a voltage stable state;
Wherein the pre-power-down threshold voltage, the power-down threshold voltage, and the recovery threshold voltage satisfy a relationship V BOD<VPre-BOD<VREC, wherein V BOD represents the power-down threshold voltage, V Pre-BOD represents the pre-power-down threshold voltage, and V REC represents the recovery threshold voltage.
Specifically, in this embodiment, the current generation module 100 includes a reference current generation circuit 101 for generating the reference current IR during power-down of the power supply voltage VDD, and a power-down and recovery current generation circuit 102 for generating the power-down current IB and the recovery current IRE during power-down of the power supply voltage VDD.
In this embodiment, the reference current generating circuit comprises a first PNP transistor Q 1, a first resistor R 1, a second resistor R 2, a first NMOS transistor N 1, A second NMOS tube N 2, a third NMOS tube N 3, a fourth NMOS tube N 4, a fifth NMOS tube N 5, A first PMOS tube P 1, a second PMOS tube P 2, a third PMOS tube P 3, a fourth PMOS tube P 4, Fifth PMOS tube P 5, sixth PMOS tube P 6, seventh PMOS tube P 7, eighth PMOS tube P 8, A ninth PMOS tube P 9, a tenth PMOS tube P 10, an eleventh PMOS tube P 11, A twelfth PMOS tube P 12 and a thirteenth PMOS tube P 13, wherein the grid electrode of the first PMOS tube P 1 is connected with the Pre end, the drain electrode is connected with the V C end of the control and output module, the source electrode is connected with the grid electrode and the drain electrode of the second PMOS tube P 2, The grid electrode of the third PMOS tube P 3, the source electrode of the fourth PMOS tube P 4, the grid electrode of the sixth PMOS tube P 6, The eleventh PMOS transistor P 11 has a gate, a source terminal connected to the power supply voltage VDD, a drain terminal connected to the source of the fifth PMOS transistor P 5, a gate connected to the drain of the first NMOS transistor N 1, a gate connected to the B terminal, a drain connected to the first NMOS transistor N 1, a gate of the fifth PMOS transistor P 5, a gate and a drain connected to the gate of the first NMOS transistor N 1 and the gate and drain of the second NMOS transistor N 2, a source terminal connected to one terminal of the first resistor R 1, another terminal of the first resistor R 1 is grounded, a source terminal connected to the ground of the second NMOS transistor N 2, a source terminal connected to the power supply voltage, a drain connected to the seventh PMOS transistor P 7, a gate of the seventh PMOS transistor P 5, a gate connected to the gate of PNP 2, a gate connected to the drain terminal of the first PMOS transistor N39348, a source terminal connected to the first resistor R39357, another terminal of the first resistor R39375, a source terminal connected to the source of the second PMOS transistor P 7, a source terminal connected to the eighth PMOS transistor P 7, a drain terminal of the eighth PMOS transistor P 7, a source terminal connected to the source of the eighth PMOS transistor P 7, and a drain terminal of the eighth PMOS transistor P 7, a source connected to the source terminal of the eighth transistor P 7, and a source terminal connected to the source of the eighth transistor P 7, and a source connected to the source terminal of the eighth transistor P 7, and a source. The drain is connected to the drain of the eleventh PMOS transistor P 11 and the source of the twelfth PMOS transistor P 12, the source of the eleventh PMOS transistor P 11 is connected to the power supply voltage, the gate of the twelfth PMOS transistor P 12 is connected to the B terminal, the drain is connected to the drain and the gate of the fourth NMOS transistor N 4 and the gate of the fifth NMOS transistor N 5, the source of the fourth NMOS transistor N4 is grounded, the source of the fifth NMOS transistor N 5 is grounded, the drain is connected to the gate and the drain of the thirteenth PMOS transistor P 13, the end point is the V IR terminal, and the source of the thirteenth PMOS transistor P 13 is connected to the power supply voltage.
In this embodiment, the power-down and recovery current generation circuit 102 includes a second PNP transistor Q 2, a third resistor R 3, a sixth NMOS transistor N 6, a seventh NMOS transistor N 7, Eighth NMOS tube N 8, fourteenth PMOS tube P 14, fifteenth PMOS tube P 15, sixteenth PMOS tube P 16, Seventeenth PMOS tube P 17, eighteenth PMOS tube P 18, nineteenth PMOS tube P 19, twentieth PMOS tube P 20, A twenty-first PMOS tube P 21, A twenty-second PMOS transistor P 22 and a twenty-third PMOS transistor P 23; the source of the fourteenth PMOS transistor P 14 is connected to a power supply voltage, the gate and the drain are connected to the source of the fifteenth PMOS transistor P 15 and the gate of the nineteenth PMOS transistor P 19, the gate of the fifteenth PMOS transistor P 15 is connected to the end B, the drain is connected to one end of the third resistor R 3, the other end of the third resistor R 3 is connected to the emitter of the second PNP transistor Q 2 and the gate of the sixth NMOS transistor N 6, the base and the collector of the second PNP transistor Q 2 are grounded, the source of the sixth NMOS transistor N 6 is connected to the drain of the seventeenth PMOS transistor P 17, the gate of the seventeenth PMOS transistor P 17 is connected to the end B, the source is connected to the gate and the drain of the twenty first PMOS transistor P 21 and the gate of the twenty second PMOS transistor P 22, the base and the collector of the second PNP transistor Q 2 are grounded, the drain is connected to the drain of the twenty-eighth PMOS transistor P 18, the source is connected to the source of the twenty-eighth PMOS transistor P 18, the drain is connected to the source of the twenty-eighth PMOS transistor P 18, the source is connected to the drain of the twenty-eighth PMOS transistor P 18, the source is connected to the source of the twenty-eighth PMOS transistor P 18, and the drain is connected to the twenty-eighth PMOS transistor P 18, the drain is connected to the drain of the twenty-second PMOS transistor P 22 and the source of the twenty-third PMOS transistor P 23, the source of the twenty-second PMOS transistor P 22 is connected to the power supply voltage, the gate of the twenty-third PMOS transistor P 23 is connected to the B terminal, the drain is connected to the gate and the drain of the eighth NMOS transistor N 8, the end point is the V IRE terminal, and the source of the eighth NMOS transistor N 8 is grounded.
Wherein the reference current ir=m1i PTAT+m2ICTAT provided by the reference current generation circuit 101, wherein I PTAT and I CTAT represent the current of positive temperature coefficient and the current of negative temperature coefficient, respectively, and m1 represent the coefficients of these two currents scaled by the current mirror, respectively. By setting the appropriate current mirror scaling, a reference current IR with a temperature coefficient close to zero can be generated. The power-down and recovery current generation circuit 102 operates in a similar manner, with both the power-down current IB and the recovery current IRE achieving a temperature coefficient close to zero by positive and negative temperature coefficients. The positive temperature coefficient current and the negative temperature coefficient current constituting the reference current IR are little affected by the power supply voltage in a range where the power supply is larger than the power-down threshold voltage, and thus the reference current is little affected by the power supply voltage. In contrast, the two positive and negative temperature coefficient currents, which constitute the power-down and recovery currents, are derived from bias, the magnitude of which is very sensitive to the magnitude of the supply voltage. Since the currents described above exhibit similar temperature characteristics and distinct power supply characteristics, an accurate power-down threshold voltage can be obtained by the current comparison module 200.
The current comparison module 200 comprises a ninth NMOS tube N 9, a tenth NMOS tube N 10, an eleventh NMOS tube N 11, a twenty-fourth PMOS tube P 24, The twenty-fifth PMOS transistor P 25 and the twenty-sixth PMOS transistor P 26, wherein the grid electrode of the twenty-fourth PMOS transistor P 24 is connected to the V IR end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the ninth NMOS transistor N 9 and the drain electrode of the tenth NMOS transistor N 10, the end points are the OUT B end, the grid electrode of the ninth NMOS transistor N 9 is connected to the V IB end, the source electrode is grounded, the grid electrode of the tenth NMOS transistor N 10 is connected to the B end, the source electrode is grounded, the grid electrode of the twenty-fifth PMOS transistor P 25 is connected to the B_end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the twenty-sixth PMOS transistor P 26 and the drain electrode of the eleventh NMOS transistor N 11, the end points are the OUT R end, the grid electrode of the twenty-sixth PMOS transistor P 26 is connected to the V IR end, the source electrode is connected to the power supply voltage, and the grid electrode of the eleventh NMOS transistor N 11 is connected to the V IRE end, and the source electrode is grounded.
The tenth NMOS transistor N 10 and the twenty-fifth PMOS transistor P 25 in the current comparing module 200 are configured to prevent the signal interference from causing the current comparing module to generate an erroneous output before the pre-power-down signal arrives.
The control and output module comprises a twenty-seventh PMOS tube P 27, a twenty-eighth PMOS tube P 28, a twenty-ninth PMOS tube P 29, a thirty-eighth PMOS tube P 30, Thirty-first PMOS tube P 31, thirty-second PMOS tube P 32, thirty-third PMOS tube P 33, thirty-fourth PMOS tube P 34, thirty-fifth PMOS tube P 35, thirty-sixth PMOS tube P 36, thirty-seventh PMOS tube P 37, thirty-eighth PMOS tube P 38, Twelfth NMOS tube N 12, thirteenth NMOS tube N 13, fourteenth NMOS tube N 14, fifteenth NMOS tube N 15, Sixteenth NMOS tube N 16, seventeenth NMOS tube N 17, eighteenth NMOS tube N 18, nineteenth NMOS tube N 19, A twenty-first NMOS tube N 20, a twenty-first NMOS tube N 21, a twenty-second NMOS tube N 22, a twenty-third NMOS tube N 23, A twenty-fourth NMOS transistor N 24, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5 a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first Buffer1, a second Buffer1, A first NAND gate NAND1; the drain and the source of the twenty-seventh PMOS P 27 are connected to the power supply voltage, and the gate is connected to the drain and the gate of the twelfth NMOS N 12; the source of the twelfth NMOS transistor N 12 is connected to the drain and gate of the thirteenth NMOS transistor N 13, which is referred to as the V C terminal (connected to the drain of the first PMOS transistor P1), the source of the thirteenth NMOS transistor N 13 is connected to the drain and gate of the fourteenth NMOS transistor N 14, the source of the fourteenth NMOS transistor N 14 is grounded, the source of the twenty eighth PMOS transistor P 28 is connected to the power supply voltage, the gate and drain are connected to the source of the twenty ninth PMOS transistor P 29, the drain and gate of the twenty ninth PMOS transistor P 29 are connected to the gate terminal of the fifteenth NMOS transistor N 15 and the drain of the thirty second PMOS transistor P 32 and the source of the thirty fourth PMOS transistor P 34, the source and drain of the fifteenth NMOS transistor N 15 are grounded, the source and drain of the thirty second PMOS transistor P 30 are connected to the power supply voltage, the source and drain of the thirty eighth PMOS transistor P 28 are connected to the power supply voltage, the drain and source of the thirty second PMOS transistor P34962 are connected to the drain and the drain of the thirty second PMOS transistor P 32 are connected to the source of the thirty fourth PMOS transistor P 34, the source and the drain of the thirty second PMOS transistor P34963 are connected to the source and the drain of the thirty second PMOS transistor P7248 is connected to the source of the thirty second PMOS transistor P7252, the source electrode is connected to the power supply voltage, the grid electrode of the thirty-fourth PMOS tube P 34 is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the seventeenth NMOS tube N 17, The drain electrode of the eighteenth NMOS tube N 18, The drain of the thirty-sixth PMOS transistor P 36 and the input end of the fourth inverter INV4 are connected to the power supply voltage by the gate of the thirty-fifth PMOS transistor P 35, the drain is connected to the drain of the nineteenth NMOS transistor N 19, The drain electrode of the twentieth NMOS tube N 20, The drain of the thirty-seventh PMOS transistor P 37 and the input of the second inverter INV 2; the source electrode of the thirty-sixth PMOS pipe P 36 is connected to a power supply voltage, the grid electrode is connected to a B end, the grid electrode of the seventeenth NMOS pipe N 17 is connected to an On signal of an external input, the source electrode is grounded, the grid electrode of the eighteenth NMOS pipe N 18 is connected to the Rec end, the source electrode is grounded, the source electrode of the thirty-seventh PMOS pipe P 37 is connected to the power supply voltage, the grid electrode is connected to the B end, the grid electrode of the nineteenth NMOS pipe N 19 is connected to an On signal of the external input, the source electrode is grounded, the grid electrode of the twenty-sixth NMOS pipe N 20 is connected to the Rec end, the source electrode is grounded, the input of the first inverter INV1 is connected to the OUT B end, the output end is connected to the input end of the first Buffer Buffer1, the output end of the first Buffer Buffer1 is output of the lower electric signal, the output end of the second inverter INV2 is connected to the input end of the third inverter 3, the output end of the third inverter INV3 is connected to the output end of the first inverter INV1, the grid electrode is connected to the output end of the fifth inverter 35, the output end of the fifth inverter INV2 is connected to the output end of the fifth inverter 2, The gate of the twenty-second NMOS transistor N 22 and the gate of the twenty-third NMOS transistor N 23, the source of the thirty-eighth PMOS transistor P 38 is connected to a power supply voltage, the drain is connected to the gate and the drain of the twenty-first NMOS transistor N 21 and the gate of the twenty-fourth NMOS transistor N 24 and the input end of the eighth inverter INV8, the source of the twenty-first NMOS transistor N 21 is connected to the drain of the twenty-second NMOS transistor N 22, the source of the twenty-second NMOS transistor N 22 is connected to the drain of the twenty-third NMOS transistor N 23, the source of the twenty-third NMOS transistor N 23 is grounded, the source and the drain of the twenty-fourth NMOS transistor N 24 are grounded, and the output end of the eighth inverter INV8 is the Rec end.
In this embodiment, the first inverter, the second inverter, the fourth inverter, the seventh inverter, and the eighth inverter are schmitt inverters.
The control and output module 300 generates the switch control signal B and the Pre-power signal Pre, which are affected by the transistor threshold voltage. Specifically, the Pre-down electric signal Pre is a pulse signal for activating the reference current generating circuit. Specifically, a positive temperature coefficient current generator for activating a reference current (the current generator comprises a second PMOS tube P 2, a third PMOS tube P 3, a fourth PMOS tube P 4, a fifth PMOS tube P 5, The first NMOS transistor N 1, the second NMOS transistor N 2 and the first resistor R 1), and then the negative temperature coefficient reference current is generated through a current mirror, so that the final reference current is obtained. and the switch control signal B is a switch control signal for activating the current generation module 100 after a power-down event is detected. the fifteenth NMOS tube N 15 and the sixteenth NMOS tube N 16 serve as two identical capacitors, the twenty eighth PMOS tube P 28, the twenty ninth PMOS tube P 29, The thirty-first PMOS transistor P 30 and the thirty-first PMOS transistor P 31 are connected as diodes to prevent charge leakage. During the power supply voltage drop, the capacitor voltage remains unchanged. When the voltage difference between the power supply voltage and the capacitor voltage causes the thirty-fourth PMOS transistor P 34 as a switch to be turned on, the switch control signal B is converted into logic "0". This threshold voltage is referred to as the pre-power-down threshold voltage V Pre-BOD. The thirty-second PMOS transistor P 32, the thirty-third PMOS transistor P 33, the thirty-sixth PMOS transistor P 36, and the thirty-seventh PMOS transistor P 37 function to prevent charge leakage during a slow power down event. By adjusting the sizes of the thirty-fourth PMOS transistor P 34 and the thirty-fifth PMOS transistor P 35, different switching threshold voltages can be obtained, so that the Pre-down electrical signal Pre is generated by the logic element.
Wherein the control and output module 300 receives the output second output signal OUT R from the current comparison module 200 to be connected to the seventh inverter INV7. A small delay module composed of the thirty-eighth PMOS tube P 38, the twenty-first NMOS tube N 21, the twenty-second NMOS tube N 22, the twenty-third NMOS tube N 23 and the twenty-fourth NMOS tube N 24 generates a pre-down electric signal Rec to reset the switch control signal B. The On signal is provided by an external power-On reset circuit. The on_signal is a direction signal of the On signal, and when the system is powered On or is recovered from an unstable state, the switch control signal B is refreshed, and the current generation module is turned off, so that extremely low static power consumption can be realized.
In this embodiment, during the power-down process of the power supply voltage, the power-down detection is divided into two stages, wherein the first stage is the pre-power-down detection process, the control and output module 300 generates the pre-power-down detection of the power supply voltage, and when the power supply voltage is lower than the pre-power-down threshold voltage, the control and output module generates the pre-power-down signal and starts the current generation module 100 and the current comparison module 200. The second stage is an accurate power-down detection process, and by comparing reference current and power-down current which have similar temperature characteristics and have great difference on power supply sensitivity characteristics, when the power supply voltage is lower than the power-down threshold voltage, the current comparison module for power-down detection outputs jump (the power-down current is lower than the reference current, and the first output signal OUT B of the current comparison module is turned to high level), and the control and output module 300 generates an accurate power-down signal BOD to output so as to realize power-down detection operation. If the power supply voltage returns to the normal state after being lower than the pre-power-down threshold voltage, and the recovery current exceeds the reference current when being higher than the recovery threshold voltage, the second output signal OUT R jumps to a low potential, the control and output module generates a recovery signal Rec, the end B is overturned to a high level, the current generation module and the current comparison module are turned off, and the circuit enters a voltage stable state. When the power-down detection circuit works normally, the current generation module and the current comparison module are turned off.
The recovery current is used for protecting the circuit under a special scene, the current generation module is turned off to realize low static power consumption, when the power supply voltage is lower than the pre-power-down threshold voltage, the current generation module is activated, and in the normal power-down process, the circuit does not consume power consumption any more along with the reduction of the power supply voltage to zero after the power supply voltage is lower than the power-down threshold voltage. If the power supply is powered down to be lower than the power-down threshold voltage, the normal voltage is restored, and the circuit can enter a low-power consumption state through an external power-up signal. However, in a special case, the power supply voltage is reduced to be lower than the pre-power-down threshold voltage and then returns to the normal working voltage, and if the signal control circuit is not restored, the current generation module is always started, so that larger static power consumption is caused. In this embodiment, in the current generation module, a recovery current for comparison with the reference current is generated, and when the power supply voltage is recovered to exceed the recovery threshold voltage, the recovery current exceeds the reference current, so that the output of the current comparator for recovering the signal is inverted, and the control and output module generates the recovery signal to control the current generation module and the current comparison module to be turned off, thereby realizing extremely low static power consumption.
A method of implementing power-down detection by the power-down detection circuit 10 will be described in detail with reference to fig. 3 to 9.
In the normal working state of the power supply voltage, the switch control signal B of the power-down detection circuit is high level, the current generation module in the circuit is in an off state, and the output first output signal OUT B and the second output signal OUT R of the current comparison module are respectively low level and high level. As the power supply voltage starts to drop, after the power supply voltage drops below the Pre-power-down threshold voltage, the switch control signal B (B terminal) jumps to a low level, and at the same time, the Pre-power-down electrical signal Pre is generated, and the reference current generating circuit is activated. The two currents of the power-down current device are reference current almost irrelevant to absolute temperature and power supply voltage and power-down current almost irrelevant to absolute temperature and related to power supply voltage, under the normal power-down condition, the power-down current is continuously reduced along with the reduction of the power supply voltage until the power supply voltage is lower than the power-down threshold voltage, the power-down current is lower than the reference current, the first output signal OUT B of the current comparison module is turned to be high level, and the final power-down signal BOD is obtained through the Schmitt trigger and the buffer. In the special power-down situation, the power supply voltage returns to the normal state after being lower than the pre-power-down threshold voltage, and the two currents of the two currents are respectively the reference current almost irrelevant to absolute temperature and almost irrelevant to the power supply voltage and the recovery current almost irrelevant to absolute temperature and relevant to the power supply voltage. When the power supply voltage is higher than the recovery threshold voltage, the recovery current exceeds the reference current, and the second output signal OUT R jumps to a low potential. After passing through the Schmitt inverter, the buffer and the small delay module, a recovery signal Rec is generated, and the switch control signal B is turned to a high level, so that the current generation module is turned off, the circuit enters a voltage stable state, and the static power consumption is extremely low.
As shown in fig. 4, the static power consumption of the circuit is extremely low when the power supply voltage is at the normal operating voltage. When the power supply is powered down normally, the power-down detection circuit generates reliable power-on and power-off signals.
As shown in fig. 5, the static power consumption of the circuit is extremely low when the power supply voltage is at the normal operating voltage. When the power supply is specially powered down, when the power supply voltage is lower than the pre-power-down threshold voltage, the current generating circuit is turned on, when the power supply rises to the recovery threshold voltage, the switch control signal B jumps to a high level, the circuit enters a voltage stable state, and the static power consumption is extremely low.
As shown in fig. 6, the power-down detection circuit works normally under the condition of slow power-down at different temperatures and process angles, and has high precision.
As shown in fig. 7, the power-down detection circuit works normally under the condition of quick power-down at different temperatures and process angles, and has high precision.
As shown in fig. 8a and 8b, in 1000 monte carlo simulations, the power-down threshold voltage deviation of the power-down signal generated by the power-down detection circuit in two power-down situations of slow speed (power-down time is 10 ms) and fast speed (power-down time is 100 μs) is smaller, so that the reliability and the high precision are provided.
As shown in fig. 9a and 9b, under the condition of different power supply voltages and power-down time, the power-down threshold voltage deviation of the power-down signal generated by the power-down detection circuit is small, and the reliability and the high precision are provided.
Therefore, the high-precision low-power-consumption power-down detection circuit has the advantages that 1) the power-down detection circuit can achieve extremely low static power consumption when the power supply voltage works normally, and 2) the power-down detection circuit can achieve accurate power-down threshold voltage and is insensitive to process angles and temperature. 3) The power-down and recovery current generation circuit of the power-down detection circuit and the logic control signal thereof can prevent the circuit from causing large static power consumption under special conditions. 4) The power-down detection circuit is insensitive to power supply voltage and power-down time.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (7)

1. The utility model provides a low power consumption of high accuracy power down detection circuit which characterized in that includes:
The current generation module is used for generating reference current, power-down current and recovery current when the detected power supply voltage is lower than the pre-power-down threshold voltage in the power-down process of the power supply; the reference current is irrelevant to absolute temperature and is irrelevant to power supply voltage, the power-down current and the recovery current are irrelevant to absolute temperature and are relevant to power supply voltage, and output ports corresponding to the reference current, the power-down current and the recovery current are respectively marked as a V IR end, a V IB end and a V IRE end;
the current comparison module is connected to the current generation module and is used for comparing the reference current with the power-down current to generate a first output signal, wherein the port is marked as an OUT B end;
The control and output module is connected with the current generation module and the current comparison module, inputs the first output signal and the second output signal, generates a switch control signal, a Pre-power-down electric signal and a recovery signal, and outputs a power-down electric signal, wherein the switch control signal and the Pre-power-down electric signal are input to the current generation module, and output ports corresponding to the switch control signal, the Pre-power-down electric signal and the recovery signal are respectively marked as a B end, a Pre end and a Rec end;
in the power-down process of the power voltage, when the power voltage is lower than the pre-power-down threshold voltage, the control and output module generates the pre-power-down electric signal, the switch control signal jumps to start the current generation module and the current comparison module;
In the power-down process of the power voltage, if the power voltage returns to a normal state after being lower than a pre-power-down threshold voltage and is higher than a recovery threshold voltage, the recovery current exceeds the reference current, the second output signal is output to jump, the control and output module generates the recovery signal, and the switch control signal is turned over, so that the current generation module and the current comparison module are turned off, and the circuit enters a voltage stable state;
Wherein the pre-power-down threshold voltage, the power-down threshold voltage, and the recovery threshold voltage satisfy a relationship V BOD<VPre-BOD<VREC, wherein V BOD represents the power-down threshold voltage, V Pre-BOD represents the pre-power-down threshold voltage, and V REC represents the recovery threshold voltage.
2. The high precision low power consumption power down detection circuit of claim 1, wherein the current generation module comprises:
A reference current generation circuit for generating the reference current during power-down of a power supply voltage;
and the power-down and recovery current generating circuit is used for generating the power-down current and the recovery current in the power-down process of the power supply voltage.
3. The high-precision low-power consumption power-down detection circuit according to claim 2, wherein the reference current generation circuit comprises a first PNP transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor;
The grid electrode of the first PMOS tube P1 is connected to the Pre end, the drain electrode of the first PMOS tube P1 is connected to the control and output module, and the source electrode of the first PMOS tube P1 is connected to the grid electrode and the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the source electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the eleventh PMOS tube; the source terminal of the second PMOS tube is connected to the power supply voltage VDD, the source terminal of the third PMOS tube is connected to the power supply voltage VDD, the drain terminal of the third PMOS tube is connected to the source terminal of the fifth PMOS tube, the gate terminal of the fourth PMOS tube is connected to the drain terminal of the first NMOS tube, the gate terminal of the fifth PMOS tube is connected to the drain terminal of the first NMOS tube and the gate and drain terminal of the second NMOS tube, the source terminal of the first NMOS tube is connected to one end of the first resistor, the other end of the first resistor is grounded, the source terminal of the second NMOS tube is grounded, the source terminal of the sixth PMOS tube is connected to the power supply voltage, the drain terminal of the seventh PMOS tube is connected to one end of the second resistor, the other end of the second resistor is connected to the gate terminal of the first PNP transistor and the third NMOS tube, the source terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS tube is connected to the drain terminal of the eighth PMOS tube is connected to the source terminal of the eighth PMOS tube, the drain electrode is connected to the drain electrode of the eleventh PMOS tube and the source electrode of the twelfth PMOS tube, the source electrode of the eleventh PMOS tube is connected to the power supply voltage, the grid electrode of the twelfth PMOS tube is connected to the end B, the drain electrode is connected to the drain electrode and the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fifth NMOS tube is grounded, the drain electrode is connected to the grid electrode and the drain electrode of the thirteenth PMOS tube, the end points are the end V IR, and the source electrode of the thirteenth PMOS tube is connected to the power supply voltage.
4. The high-precision low-power consumption power-down detection circuit according to claim 2, wherein the power-down and recovery current generation circuit comprises a second PNP transistor, a third resistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, and a twenty-third PMOS transistor;
The source electrode of the fourteenth PMOS tube is connected to the power supply voltage, and the grid electrode and the drain electrode of the fourteenth PMOS tube are connected to the source electrode of the fifteenth PMOS tube and the grid electrode of the nineteenth PMOS tube; the grid electrode of the fifteenth PMOS tube is connected to the end B, and the drain electrode of the fifteenth PMOS tube is connected to one end of the third resistor; the other end of the third resistor is connected to the emitter of the second PNP transistor and the grid electrode of the sixth NMOS transistor, the base electrode and the collector of the second PNP transistor are grounded, the source electrode of the sixth NMOS transistor is grounded, the drain electrode of the sixth NMOS transistor is connected to the drain electrode of the seventeenth PMOS transistor, the grid electrode of the seventeenth PMOS transistor is connected to the B end, the source electrode of the seventh PMOS transistor is connected to the grid electrode and the drain electrode of the sixteenth PMOS transistor and the grid electrode of the twenty second PMOS transistor, the source electrode of the sixteenth PMOS transistor is connected to the power supply voltage, the source electrode of the eighteenth PMOS transistor is connected to the power supply voltage, the drain electrode of the nineteenth PMOS transistor is connected to the source electrode of the nineteenth PMOS transistor, the grid electrode of the twenty eighth PMOS transistor is connected to the B end, the drain electrode of the seventeenth PMOS transistor is connected to the grid electrode and the drain electrode of the seventh NMOS transistor, the end is the V IB end, the source electrode of the seventh NMOS transistor is grounded, the source electrode of the twenty eighth PMOS transistor is connected to the drain electrode of the twenty eighth PMOS transistor, the twenty eighth PMOS is connected to the drain electrode of the twenty eighth PMOS transistor.
5. The high-precision low-power consumption power-down detection circuit according to claim 1, wherein the control and output module comprises a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirty-eighth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first buffer, a second buffer, and a first NAND gate;
The drain electrode and the source electrode of the twenty-seventh PMOS tube are connected to the power supply voltage, and the grid electrode is connected to the drain electrode and the grid electrode of the twelfth NMOS tube; the source electrode of the thirteenth NMOS tube is connected to the drain electrode and the grid electrode of the thirteenth NMOS tube, the end points of the thirteenth NMOS tube are connected to the current generating module, the source electrode of the thirteenth NMOS tube is connected to the drain electrode and the grid electrode of the fourteenth NMOS tube, the source electrode of the thirty-eighth PMOS tube is grounded, the source electrode of the twenty-eighth PMOS tube is connected to the power supply voltage, the grid electrode and the drain electrode of the twenty-ninth PMOS tube are connected to the source electrode of the twenty-ninth PMOS tube, the drain electrode and the grid electrode of the thirty-second PMOS tube are connected to the grid electrode of the fifteenth NMOS tube and the source electrode of the thirty-fourth PMOS tube, the source electrode and the drain electrode of the fifteenth NMOS tube are grounded, the source electrode of the thirty-first PMOS tube is connected to the power supply voltage, the grid electrode and the drain electrode of the thirty-first PMOS tube are connected to the grid electrode of the thirty-first PMOS tube, the drain electrode of the thirty-first PMOS tube is connected to the source voltage, the source electrode of the thirty-eighth PMOS tube is connected to the source electrode of the thirty-third PMOS tube is connected to the source voltage, the source electrode of the thirty-eighth PMOS tube is connected to the source voltage, the source electrode of the thirty-third PMOS tube is connected to the source voltage is connected to the source electrode of the source voltage, the source electrode of the source tube is connected to the source electrode of the source electrode is connected to the source electrode of the source tube is connected to the source electrode of the source, The drain electrode of the eighteenth NMOS tube, the drain electrode of the thirty-sixth PMOS tube and the input end of the fourth inverter; the grid electrode of the thirty-fifth PMOS tube is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the nineteenth NMOS tube, the drain electrode of the twentieth NMOS tube, The drain of the thirty-seventh PMOS tube and the input end of the second inverter, the source of the thirty-sixth PMOS tube is connected to a power supply voltage, the grid electrode is connected to a B end, the grid electrode of the seventeenth NMOS tube is connected to an On signal of an external input, the source is grounded, the grid electrode of the thirty-seventh PMOS tube is connected to the Rec end, the source is connected to the power supply voltage, the grid electrode is connected to the B end, the grid electrode of the nineteenth NMOS tube is connected to an On signal of the external input, the source is grounded, the grid electrode of the twenty-sixth NMOS tube is connected to a Rec end, the input of the first inverter is connected to the OUT B end, the output of the first buffer is connected to the input end of the first buffer, the output end of the first buffer outputs the down signal, the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to a first input end of the first NAND gate, the grid electrode is connected to the B end of the second inverter, the grid electrode of the nineteenth NMOS tube is connected to the On signal of the external input, the source is grounded, the grid electrode of the twenty-sixth NMOS tube is connected to the output end of the second inverter is connected to the output end of the second inverter, the output end of the first inverter is connected to the output end of the first inverter, The drain electrode of the thirty-eighth PMOS tube is connected to the grid electrode and the drain electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube and the input end of the eighth inverter, the source electrode of the twenty-first NMOS tube is connected to the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-second NMOS tube is connected to the drain electrode of the twenty-third NMOS tube, the source electrode of the twenty-third NMOS tube is grounded, the source electrode and the drain electrode of the twenty-fourth NMOS tube are grounded, and the output end of the eighth inverter is the Rec end.
6. The high-precision low-power consumption power-down detection circuit according to claim 5, wherein the current comparison module comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube and a twenty-sixth PMOS tube;
The grid electrode of the twenty-fourth PMOS tube is connected to the V IR end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube, the end points are the OUT B end, the grid electrode of the ninth NMOS tube is connected to the V IB end, the source electrode is grounded, the grid electrode of the tenth NMOS tube is connected to the B end, the source electrode is grounded, the grid electrode of the twenty-fifth PMOS tube is connected to the B-end, the source electrode is connected to the power supply voltage, the drain electrode is connected to the drain electrode of the twenty-sixth PMOS tube and the drain electrode of the eleventh NMOS tube, the end points are the OUT R end, the grid electrode of the twenty-sixth PMOS tube is connected to the V IR end, the source electrode of the eleventh NMOS tube is connected to the V IRE end, and the source electrode is grounded.
7. The high precision low power consumption power down detection circuit according to claim 5, wherein the first inverter, the second inverter, the fourth inverter, the seventh inverter, and the eighth inverter are schmitt inverters.
CN202410749203.4A 2024-06-12 2024-06-12 A high-precision and low-power power-off detection circuit Active CN118658502B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9280164B2 (en) * 2013-01-18 2016-03-08 Sanken Electric Co., Ltd. Switching power-supply device and method for manufacturing switching power-supply device
CN110672943A (en) * 2019-09-26 2020-01-10 宁波大学 Aging Detection Sensor Based on Voltage Comparison

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9280164B2 (en) * 2013-01-18 2016-03-08 Sanken Electric Co., Ltd. Switching power-supply device and method for manufacturing switching power-supply device
CN110672943A (en) * 2019-09-26 2020-01-10 宁波大学 Aging Detection Sensor Based on Voltage Comparison

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