CN118658398B

CN118658398B - Display panel and display device

Info

Publication number: CN118658398B
Application number: CN202411136043.2A
Authority: CN
Inventors: 陈有山; 张欢喜
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2024-08-19
Filing date: 2024-08-19
Publication date: 2024-11-08
Anticipated expiration: 2044-08-19
Also published as: CN118658398A

Abstract

The present application provides a display panel and a display device; the display panel connects one of a first group of clock signal lines and a second group of clock signal lines to the gate of a control transistor, and the orthographic projection of at least one clock signal line of the other of the first group of clock signal lines and the second group of clock signal lines overlaps with the orthographic projection of at least one output transistor, so that the loads of the clock signal lines in the first group of clock signal lines and the clock signal lines in the second group of clock signal lines are similar or even the same, thereby avoiding the problem of display abnormality caused by the voltage drop difference between different clock signal lines.

Description

Display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display devices, higher demands are being made on the power consumption and performance of the display devices. In order to achieve the effects of reducing power consumption, reducing leakage current, improving switching speed and the like, the conventional display device adopts a low-temperature polycrystalline oxide (Low Temperature Polysilicon Oxide, LTPO) technology to form a pixel driving circuit, the pixel driving circuit adopts a gate driving circuit (GATE DRIVER On Array, GOA) to drive, and specifically, the GOA circuit comprises a first output circuit, a second output circuit and a third output circuit, and the first output circuit, the second output circuit and the third output circuit are used for respectively outputting scanning signals corresponding to P-type transistors, scanning signals corresponding to N-type transistors and scanning signals corresponding to light-emitting control transistors to control the pixel driving circuit to work. However, the GOA circuit has a problem of large frame. In order to solve the above technical problems, a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) GOA circuit is proposed, which combines a first output circuit and a second output circuit, and makes a first-stage CMOS GOA output signals corresponding to two rows of pixel driving circuits, so as to achieve the effect of a narrow frame. However, in the actual use process, the voltage drop difference of the different clock signal lines is found to be larger, so that the scanning signal difference corresponding to the two P-type transistors output by the same-stage CMOS GOA is larger, and dense transverse stripes appear in display.

Therefore, the display device adopting the CMOS GOA circuit has the technical problem that the voltage drop difference of different clock signal lines is large, so that abnormal display is caused.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which are used for solving the technical problem that the display abnormality is caused by larger voltage drop difference of different clock signal lines in the existing display device adopting a CMOS GOA circuit.

An embodiment of the present application provides a display panel, including a display portion and a gate driving circuit located at least one side of the display portion, the gate driving circuit including a plurality of cascaded gate driving units, the gate driving unit including:

The first control module is electrically connected with the first node and the internal node of the gate driving unit of the current stage and is configured to control signals transmitted to the first node and the internal node according to a starting signal;

the second control module is electrically connected with the first node and the internal node and is configured to control signals transmitted to the internal node according to the signals of the first node;

a first output module connected to a first group of clock signal lines, the first node, and the internal node, configured to output a first gate control signal according to signals of the first group of clock signal lines, the first node, and the internal node;

a second output module connected to a second group of clock signal lines, the first node, and the internal node, and configured to output a second gate control signal according to signals of the second group of clock signal lines, the first node, and the internal node; a phase difference exists between the first gate control signal and the second gate control signal;

The first group of clock signal lines comprises at least two clock signal lines, the second group of clock signal lines comprises at least two clock signal lines, the first output module and the second output module comprise output transistors, the first control module further comprises control transistors, one of the first group of clock signal lines and the second group of clock signal lines is further connected with gates of the control transistors, and orthographic projections of at least one clock signal line of the other of the first group of clock signal lines and the second group of clock signal lines are overlapped with orthographic projections of at least one output transistor.

Meanwhile, an embodiment of the present application provides a display device including the display panel according to any one of the above embodiments.

The beneficial effects are that: the application provides a display panel and a display device; according to the display panel, one of the first group of clock signal lines and the second group of clock signal lines is connected with the grid electrode of the control transistor, the orthographic projection of at least one clock signal line of the other one of the first group of clock signal lines and the second group of clock signal lines is overlapped with the orthographic projection of at least one output transistor, so that the loads of the clock signal lines in the first group of clock signal lines and the clock signal lines in the second group of clock signal lines are similar or even the same, and the problem of abnormal display caused by voltage drop difference of different clock signal lines can be avoided.

Drawings

The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a first comparative display device according to an embodiment of the present application.

Fig. 2 is a driving schematic diagram of the comparative display device in fig. 1.

Fig. 3 is a schematic diagram of a second comparative display device according to an embodiment of the present application.

Fig. 4 is a driving schematic diagram of the comparative display device in fig. 3.

Fig. 5 is a schematic diagram of a third comparative display device according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a display panel according to an embodiment of the application.

Fig. 7 is a cross-sectional view of a display panel according to an embodiment of the present application.

Fig. 8 is a circuit diagram of a gate driving unit of a display panel according to an embodiment of the application.

Fig. 9 is a laminated diagram of film layers of a display panel according to an embodiment of the application.

Fig. 10 is an exploded view of a first active layer of the display panel of fig. 9.

Fig. 11 is an exploded view of a first gate layer of the display panel of fig. 9.

Fig. 12 is an exploded view of a second gate layer of the display panel of fig. 9.

Fig. 13 is an exploded view of a second active layer of the display panel of fig. 9.

Fig. 14 is an exploded view of a third gate layer of the display panel of fig. 9.

Fig. 15 is an exploded view of a first source/drain layer of the display panel of fig. 9.

Fig. 16 is an exploded view of a second source/drain layer of the display panel of fig. 9.

Fig. 17 is a circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present application, it should be noted that, unless explicitly stated and limited otherwise, the term "connected" means that they are directly connected, and "electrically connected" means that they may be directly connected or indirectly connected through an intermediary. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

Fig. 1 is a schematic diagram of a first comparative display device according to an embodiment of the present application. Fig. 2 is a driving schematic diagram of the comparative display device in fig. 1. Fig. 3 is a schematic diagram of a second comparative display device according to an embodiment of the present application. Fig. 4 is a driving schematic diagram of the comparative display device in fig. 3. Fig. 5 is a schematic diagram of a third comparative display device according to an embodiment of the present application.

To illustrate the principles of the technical problem addressed by embodiments of the present application, contrast display devices are provided that are not known in the art. As shown in fig. 1, the GOA circuit in the first comparative display device includes a first output circuit Pscan, a second output circuit NSCAN1 and a third output circuit EM1, it can be seen from fig. 1 that the first output circuit Pscan drives the n-th row pixel unit and the n+1th row pixel unit by using a pair of two-sided driving, the second output circuit NSCAN1 and the third output circuit EM1 drive the multiple rows of pixel units by implementing a level signal through a level transmission, as shown in fig. 2, two nodes of the first output circuit PscanA in adjacent two levels of the first output circuit Pscan are connected to the first clock line XCK and the second clock line CK and output signals to the first row scan line Pscan1, two nodes of the second first output circuit PscanB are connected to the second clock line and the first clock line and output signals to the second row scan line Pscan, and correspondingly, other first output circuits output signals to the third row scan line Pscan and the fourth row scan line Pscan. In this driving circuit, since the first output circuit Pscan adopts the double-sided driving, the influence of the voltage drop on the first output circuit Pscan can be reduced, so that the brightness uniformity is improved, the clock signal line can avoid other signal lines, the signal distortion caused by the larger voltage drop of the clock signal line is prevented, and the first clock line XCK and the second clock line CK can be alternately connected to the inside of the GOA according to odd-even rows, so that the voltage drop difference of the first clock line XCK and the second clock line CK is smaller, and the dense cross stripes are prevented, but the driving circuit has the problem of larger frame.

In order to reduce the frame of the display device, a second contrast display device is provided, as shown in fig. 3, a CMOS GOA circuit is used to output Pscan signals and Nscan signals in a two-side one-drive two manner, and a third output circuit EM1 is used to output EM signals, so that a one-stage CMOS GOA circuit can output Pscan signals with a two-stage phase difference of 1 unit length, thereby reducing the frame. As shown in fig. 4, the first Point1 and the second Point2 of the first stage CMOS GOA circuit CMOS a are respectively connected to the first clock line CK1 and the second clock line CK2, and then output signals to the first row scan line Pscan and the second row scan line Pscan, the first Point1 and the second Point2 of the second stage CMOS GOA circuit CMOS B are respectively connected to the third clock line CK3 and the fourth clock line CK4, and then output signals to the third row scan line Pscan3 and the fourth row scan line Pscan, and similarly, other CMOS GOA circuits may output signals to the fifth row scan line Pscan, the sixth row scan line Pscan6, the seventh row scan line Pscan7 and the eighth row scan line Pscan.

As can be seen from fig. 4, the first Point1 is connected to the signals of the first clock line CK1 and the third clock line CK3, the second Point2 is connected to the signals of the second clock line CK2 and the fourth clock line CK4, and the second clock line CK2 and the fourth clock line CK4 also need to control transistors, so that parasitic capacitance of the second clock line CK2 and the fourth clock line CK4 is larger, and a problem that a voltage drop of the second clock line CK2 and the fourth clock line CK4 is different from a voltage drop of the first clock line CK1 and the third clock line CK3 occurs, which results in abnormal display of the display device. Therefore, the display device adopting the CMOS GOA circuit has the technical problem that the voltage drop difference of different clock signal lines is large, so that abnormal display is caused.

The embodiment of the application provides a display panel and a display device, which are used for solving the technical problems.

Fig. 6 is a schematic diagram of a display panel according to an embodiment of the application. Fig. 7 is a cross-sectional view of a display panel according to an embodiment of the present application. Fig. 8 is a circuit diagram of a gate driving unit of a display panel according to an embodiment of the application. Fig. 9 is a laminated diagram of film layers of a display panel according to an embodiment of the application. Fig. 10 is an exploded view of a first active layer of the display panel of fig. 9. Fig. 11 is an exploded view of a first gate layer of the display panel of fig. 9. Fig. 12 is an exploded view of a second gate layer of the display panel of fig. 9. Fig. 13 is an exploded view of a second active layer of the display panel of fig. 9. Fig. 14 is an exploded view of a third gate layer of the display panel of fig. 9. Fig. 15 is an exploded view of a first source/drain layer of the display panel of fig. 9. Fig. 16 is an exploded view of a second source/drain layer of the display panel of fig. 9. Fig. 17 is a circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the application.

As shown in fig. 6 to 16, an embodiment of the present application provides a display panel 2 including a display portion 21 and a gate driving circuit 22 located at least one side of the display portion 21, the gate driving circuit 22 including a plurality of cascade gate driving units 120, the gate driving units 120 including:

a first control module 10 electrically connected to the first node K and the internal node P (n) of the gate driving unit 120, and configured to control signals transmitted to the first node K and the internal node P (n) according to a start signal;

A second control module 20 electrically connected to the first node K and the internal node P (n), and configured to control a signal transmitted to the internal node P (n) according to the signal of the first node K;

A first output module 501 connected to a first group of clock signal lines CK-1, the first node K, and the internal node P (n), and configured to output a first gate control signal according to signals of the first group of clock signal lines CK-1, the first node K, and the internal node P (n);

A second output module 502 connected to a second group clock signal line CK-2, the first node K, and the internal node P (n), and configured to output a second gate control signal according to signals of the second group clock signal line CK-2, the first node K, and the internal node P (n); a phase difference exists between the first gate control signal and the second gate control signal;

Wherein the first group of clock signal lines CK-1 includes at least two clock signal lines (e.g., the first group of clock signal lines CK-1 includes a first clock signal line PCK1 and a third clock signal line PCK 3), the second group of clock signal lines CK-2 includes at least two clock signal lines (e.g., the second group of clock signal lines CK-2 includes a second clock signal line PCK2 and a fourth clock signal line PCK 4), the first output module 501 and the second output module 502 each include an output transistor (e.g., the first output module 501 includes a first output transistor T6, the second output module 502 includes a third output transistor T24), the first control module 10 further includes a control transistor (e.g., the first control module 10 further includes a third control transistor T2), one of the first and second sets of clock signal lines CK-1 and CK-2 is also connected to the gate of the control transistor (e.g., the second set of clock signal lines CK-2 includes the second and fourth clock signal lines PCK2 and PCK4, the second and fourth clock signal lines PCK2 and PCK4 would be connected to the gate of the third control transistor T2), and the orthographic projection of at least one of the other of the first and second sets of clock signal lines CK-1 and CK-2 coincides with the orthographic projection of at least one of the output transistors (e.g., the orthographic projection of the first clock signal line PCK1 coincides with the orthographic projection of the first output transistor T6).

The embodiment of the application provides a display panel, which has the advantages that one of a first group of clock signal lines and a second group of clock signal lines is connected with a grid electrode of a control transistor, and the orthographic projection of at least one clock signal line of the other one of the first group of clock signal lines and the second group of clock signal lines is overlapped with the orthographic projection of at least one output transistor, so that the loads of the clock signal lines in the first group of clock signal lines and the clock signal lines in the second group of clock signal lines are similar or even the same, and the problem of abnormal display caused by the difference of voltage drops of different clock signal lines can be avoided.

Specifically, the orthographic projection in the embodiment of the present application refers to a projection in a thickness direction of a display panel, for example, the display panel includes a substrate, and the orthographic projection of the output transistor may refer to a projection of the output transistor on a plane on which the substrate is located.

Specifically, as shown in fig. 6, the display panel 2 includes a display area AA and a non-display area NA, the display portion 21 is disposed in the display area AA, the gate driving circuit 22 is disposed in the non-display area NA, and the display panel 2 further includes a terminal portion 23.

Specifically, the first gate control signal may be a signal output from the first output signal line Pout1 (n), and the second gate control signal may be a signal output from the second output signal line Pout2 (n).

Specifically, it can be understood that, in order to reduce the number of wires, reducing the frame of the display panel, the multiple clock signal wires in one of the first group of clock signal wires and the second group of clock signal wires drive different transistors in the gate driving circuit, and accordingly, this can cause the voltage drops of the two groups of clock signal wires to be different, by connecting the first group of clock signal wires with the first output module, the second group of clock signal wires with the second output module, and one of the first group of clock signal wires and the second group of clock signal wires is also connected with the gate of the control transistor, the positive projection of at least one clock signal wire in the first group of clock signal wires and the second group of clock signal wires is overlapped with the positive projection of at least one of the output transistors, so that the parasitic capacitance caused by connecting one of the first group of clock signal wires and the second group of clock signal wires with the gate of the control transistor is formed, the parasitic capacitance caused by overlapping the other of the first group of clock signal wires and the second group of clock signal wires with the second output transistors is even formed, the parasitic capacitance is formed by connecting the parasitic capacitance with the other groups of the first group of clock signal wires and the second group of clock signal wires with the second clock signal wires with the same impedance, and the parasitic capacitance is even formed by the parasitic capacitance is similar to the parasitic capacitance formed by the second group of the same clock signal wires, and the parasitic capacitance is even formed by the parasitic capacitance of the second group of the output transistors, thus, the problem of abnormal display caused by voltage drop difference of different clock signal lines can be avoided.

Specifically, the first group of clock signal lines may be connected to the gates of the control transistors, and the orthographic projection of at least one clock signal line in the second group of clock signal lines coincides with the orthographic projection of at least one output transistor; the second set of clock signal lines may also be connected to the gates of the control transistors, the orthographic projection of at least one clock signal line of the first set of clock signal lines coinciding with the orthographic projection of at least one output transistor.

In some embodiments, as shown in fig. 6 to 16, the first group of clock signal lines CK-1 includes a first clock signal line PCK1 and a third clock signal line PCK3, the second group of clock signal lines CK-2 includes a second clock signal line PCK2 and a fourth clock signal line PCK4, in adjacent two stages of the gate driving units 120, the first output module 501 within one stage of the gate driving units 120 is connected to the first clock signal line PCK1, the second output module 502 is connected to the second clock signal line PCK2, and the fourth clock signal line PCK4 is connected to the gate of the control transistor; the first output module 501 in the gate driving unit 120 of the other stage is connected to a third clock signal line PCK3, the second output module 502 is connected to a fourth clock signal line PCK4, and the second clock signal line PCK2 is connected to the gate of the control transistor;

Wherein there is a coincidence of an orthographic projection of at least one of the first clock signal line PCK1 and the third clock signal line PCK3 with an orthographic projection of at least one of the output transistors. The first group of clock signal lines comprise a first clock signal line and a third clock signal line, the second group of clock signal lines comprise a second clock signal line and a fourth clock signal line, in the first-stage grid driving unit, the first output module is connected with the first clock signal line, the second output module is connected with the second clock signal line, the fourth clock signal line is connected with the grid electrode of the control transistor, in the other grid driving unit, the first output module is connected with the third clock signal line, the second output module is connected with the fourth clock signal line, the second clock signal line is connected with the grid electrode of the control transistor, so that adjacent two-stage grid driving units can be driven by the first clock signal line, the second clock signal line, the fourth clock signal line and the second clock signal line, the third clock signal line and the fourth clock signal line respectively, normal operation of the grid driving circuit is realized, the second clock signal line and the fourth clock signal line can be seen to be connected with the grid electrode of the transistor, and the front projection of at least one of the first clock signal line and the third clock signal line can be overlapped with the grid electrode of the transistor, and the second clock signal line can even be prevented from being overlapped with the first clock signal line and the second clock signal line, and the second clock signal line can even have the same group of abnormal signal load.

In some embodiments, as shown in fig. 6 to 16, the front projection of the first clock signal line PCK1 coincides with the front projection of at least one of the output transistors, the front projection of the third clock signal line PCK3 coincides with the front projection of at least one of the output transistors, and by overlapping the front projection of the first clock signal line with the front projection of at least one of the output transistors, the front projection of the third clock signal line coincides with the front projection of at least one of the output transistors, so that the load on each clock signal line is similar or even the same, so that the voltage drop of the signals on each clock signal line is similar or even the same, so that the voltage drops of the signals output by the first output module and the second output module are similar or even the same, and thus dense cross-stripes can be avoided during display.

In some embodiments, as shown in fig. 8 to 16, the first control module 10 includes a first control transistor T13, a second control transistor T12, a third control transistor T2, a first high potential signal line PVGH, a first low potential signal line NVGL, and a start signal line STV, the gate of the first control transistor T13 (including a first gate T13Ga of the first control transistor T13 and a second gate T13Gb of the first control transistor T13) and the gate T12G of the second control transistor T12 are connected to the start signal line STV, the first electrode T13S of the first control transistor T13 is connected to the first low potential signal line NVGL, the first electrode T12S of the second control transistor T12 is connected to the first high potential signal line PVGH, the second electrode T13D of the first control transistor T13 and the second electrode T12D of the second control transistor T12 are connected to the first control transistor T2 and the second electrode T2K of the third control transistor T2, the first electrode T12 is connected to the third control transistor T2K of the third control transistor T2 group; the third group of clock signal lines XCK includes the second clock signal line PCK2 and a fourth clock signal line PCK4, the second output module 502 is connected to one of the second clock signal line PCK2 and the fourth clock signal line PCK4, and the gate T2G of the third control transistor T2 is connected to the other of the second clock signal line PCK2 and the fourth clock signal line PCK4 within one stage of the gate driving unit 120;

The second control module 20 includes a fourth control transistor T1, a fifth control transistor T3, and a second low potential signal line PVGL, wherein a gate of the fourth control transistor T1 (including a first gate T1Ga of the fourth control transistor T1 and a second gate T1Gb of the fourth control transistor T1) and a gate T3G of the fifth control transistor T3 are connected to the first node K, a first electrode T1S of the fourth control transistor T1 is connected to the second low potential signal line PVGL, a first electrode T3S of the fifth control transistor T3 is connected to the first high potential signal line PVGH, and a second electrode T1D of the fourth control transistor T1 and a second electrode T3D of the fifth control transistor T3 are connected to the internal node P (n);

The first output module 501 includes a first switching transistor T8, a first output transistor T6, a second output transistor T7, a first capacitor C1, and a first output signal line Pout1 (n), where a gate T8G of the first switching transistor T8 is connected to an internal node P (n-2) of the gate driving unit 120 of the upper two stages, a first electrode T8S of the first switching transistor T8 is electrically connected to the first node K, a second electrode T8D of the first switching transistor T8, a first electrode plate C1a of the first capacitor C1, and a gate T6G of the first output transistor T6 are connected to a third node Q1, a first electrode T6S of the first output transistor T6 is connected to a first group of clock signal lines CK-1, a second electrode T6D of the first output transistor T6, a second electrode T7D of the second output transistor T7, a first capacitor C1b of the first output transistor T1 and a gate T6 are connected to a first output signal line P (n-1 of the first output transistor T7 is connected to the first node P7 of the first output signal line P);

The second output module 502 includes a second switching transistor T23, a third output transistor T24, a fourth output transistor T25, a second capacitor C4, and a second output signal line Pout2 (n), where a gate T23G of the second switching transistor T23 is connected to an internal node P (n-2) of the gate driving unit 120 of the upper two stages, a first electrode T23S of the second switching transistor T23 is connected to the first node K, a second electrode T23D of the second switching transistor T23, a first electrode plate C4a of the second capacitor C4, and a gate T24G of the third output transistor T24 are connected to a fourth node Q2, a first electrode T24S of the third output transistor T24 is connected to a second group clock signal line CK-2, a second electrode T24D of the fourth output transistor T24, a second electrode T25D of the fourth output transistor T25, a first electrode plate C4b of the second capacitor C4, and a gate T24G of the third output transistor T24 are connected to a second group clock signal line CK-2, and a second electrode T25 of the fourth output transistor T25 is connected to the first node T25;

The orthographic projection of the first clock signal line PCK1 coincides with orthographic projections of the first output transistor T6, the second output transistor T7, the third output transistor T24 and the fourth output transistor T25, and the orthographic projection of the third clock signal line PCK3 coincides with orthographic projections of the first output transistor T6, the second output transistor T7, the third output transistor T24 and the fourth output transistor T25. By overlapping the orthographic projection of the first clock signal line with the orthographic projections of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor, the orthographic projection of the third clock signal line overlaps with the orthographic projections of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor, the loads of the first clock signal line and the third clock signal line can be increased, and the loads of the first clock signal line and the third clock signal line are similar to or even the same as the loads of the second clock signal line and the fourth clock signal line, so that dense cross stripes are avoided during display.

In some embodiments, as shown in fig. 8 to 16, the gate driving unit 120 further includes:

An output control unit 30 including a third switching transistor T4, a fourth switching transistor T5, and a fifth switching transistor T14, the gate of the third switching transistor T4 (including a first gate T4Ga of the third switching transistor T4 and a second gate T4Gb of the third switching transistor T4) being connected to the third group clock signal line XCK, the first electrode T4S of the third switching transistor T4 being connected to the first node K, the second electrode T4D of the third switching transistor T4 being connected to the second electrode T5D of the fourth switching transistor T5, the gate T5G of the fourth switching transistor T5 being connected to the internal node P (n), the first electrode T5S of the fourth switching transistor T5 being connected to the first high potential signal line PVGH, the gate of the fifth switching transistor T14 (including a first gate T14Ga of the fifth switching transistor T14 and a second gate T14K of the fifth switching transistor T14 being connected to the first node T14, the gate T5G of the fourth switching transistor T5 being connected to the fifth node T14S;

A third control unit 40 including a sixth control transistor T17 and a seventh control transistor T18, the gate of the sixth control transistor T17 (including a first gate T17Ga of the sixth control transistor T17 and a second gate T17Gb of the sixth control transistor T17) being connected to the third group clock signal line XCK, a first electrode T17S of the sixth control transistor T17 being electrically connected to the first node K, a second electrode T17D of the sixth control transistor T17 being connected to a second electrode T18D of the seventh control transistor T18, a gate T18G of the seventh control transistor T18 being connected to the internal node P (n), a first electrode T18S of the seventh control transistor T18 being connected to the first high potential signal line PVGH;

A fourth control unit 80 including an eighth control transistor T21 and a ninth control transistor T22, the gate of the eighth control transistor T21 (including a first gate T21Ga of the eighth control transistor T21 and a second gate T21Gb of the eighth control transistor T21) being connected to a third group clock signal line XCK, a first electrode T21S of the eighth control transistor T21 being electrically connected to the first node K, a second electrode T21D of the eighth control transistor T21 being connected to a second electrode T22D of the ninth control transistor T22, a gate T22G of the ninth control transistor T22 being connected to the internal node P (n), a first electrode T22S of the ninth control transistor T22 being connected to the first high potential signal line PVGH;

A third output module 503 including a fifth output transistor T10, a sixth output transistor T9, a second high potential signal line NVGH, and a third output signal line Nout (n), wherein a gate of the fifth output transistor T10 (including a first gate T10Ga of the fifth output transistor T10 and a second gate T10Gb of the fifth output transistor T10) is connected to the first node K, a first electrode T10S of the fifth output transistor T10 is connected to the first low potential signal line NVGL, a second electrode T10D of the fifth output transistor T10, a second electrode T9D of the sixth output transistor T9, and the third output signal line Nout (n) are connected, a gate T9G of the sixth output transistor T9 is electrically connected to the first node K, and a first electrode T9S of the sixth output transistor T9 is connected to the second high potential signal line NVGH;

The frequency dividing module 60 comprises a first frequency dividing module 601 and a second frequency dividing module 602, the first frequency dividing module 601 comprises a first frequency dividing transistor T16, a second frequency dividing transistor T11, a third capacitor C2 and a first frequency dividing signal line NLF, a gate T16G of the first frequency dividing transistor T16 is connected with the internal node P (n) of the current stage gate driving unit 120, a first electrode T16S of the first frequency dividing transistor T16 is connected with the first frequency dividing signal line NLF, a second electrode T16D of the first frequency dividing transistor T16, a first electrode plate C2a of the third capacitor C2 and a gate T11G of the second frequency dividing transistor T11 are connected, a first electrode T11S of the second frequency dividing transistor T11 is connected with the first node K, and a second electrode T11D of the second frequency dividing transistor T11 is connected with a second electrode plate C2b of the third capacitor C2; the second frequency dividing module 602 includes a third frequency dividing transistor T20, a fourth frequency dividing transistor T19, a fourth capacitor C3, and a second frequency dividing signal line PLF, where a gate T20G of the third frequency dividing transistor T20 is connected to the internal node P (n) of the current stage gate driving unit 120, a first electrode T20S of the third frequency dividing transistor T20 is connected to the second frequency dividing signal line PLF, a second electrode T20D of the third frequency dividing transistor T20, a gate T19G of the fourth frequency dividing transistor T19 is connected to a first plate C3a of the fourth capacitor C3, a first electrode T19S of the fourth frequency dividing transistor T19 is connected to the first node K, and a second electrode T19D of the fourth frequency dividing transistor T19 and a second plate of the fourth capacitor C3 are connected to a sixth node M;

the reset module 70 includes a reset transistor T15 and a Control signal line Control, wherein a gate T15G of the reset transistor T15 is connected to the Control signal line Control, a first electrode T15S of the reset transistor T15 is connected to the first high potential signal line PVGH, and a second electrode T15D of the reset transistor T15 is connected to the first node K.

Specifically, it is understood that the above embodiment distinguishes the clock signal lines connected to the gates of the transistors from the second output module by the third group of clock signal lines and the second group of clock signal lines, and actually, the types and the numbers of the clock signal lines in the third group of clock signal lines and the second group of clock signal lines are the same, and the difference is that in the same stage of gate driving unit, the clock signal lines connected to the gates of the second output module and the transistors respectively in the third group of clock signal lines and the second group of clock signal lines are different, that is, when the second output module is connected to the second clock signal line, the gates of the transistors are connected to the fourth clock signal line, and when the second output module is connected to the fourth clock signal line, the gates of the transistors are connected to the second clock signal line.

Specifically, in the embodiment of the present application, a single gate design is adopted for a part of transistors, a double gate design is adopted for a part of transistors, the gate of the transistor adopting the single gate design is the only gate of the transistor, the gate of the transistor adopting the double gate design is the bottom gate and the top gate, for example, the first control transistor adopts the double gate design, the gate of the first control transistor is the first gate and the second gate of the first control transistor, and similarly, the description of the gates of other transistors can be referred to the description of the transistors, and the description of the other transistors is omitted in the following embodiments.

Specifically, the start signal line STV may be connected to an internal node of the gate driving unit of the previous stage.

In some embodiments, as shown in fig. 7 and 16, the display panel 2 includes:

A substrate 201;

A first active layer 205 disposed on one side of the substrate 201;

A first gate layer 207 disposed on a side of the first active layer 205 away from the substrate 201;

a second gate layer 209 disposed on a side of the first gate layer 207 away from the first active layer 205;

a second active layer 211 disposed on a side of the second gate layer 209 away from the first gate layer 207;

a third gate layer 213 disposed on a side of the second active layer 211 away from the second gate layer 209;

A first source/drain layer 215 disposed on a side of the third gate layer 213 away from the second active layer 211;

a second source/drain layer 217 disposed on a side of the first source/drain layer 215 away from the third gate layer 213;

The second source/drain layer 217 includes the first clock signal line PCK1, the second clock signal line PCK2, the third clock signal line PCK3, and the fourth clock signal line PCK4.

Specifically, the material of the first active layer includes a silicon semiconductor, which may be specifically low-temperature polysilicon.

Specifically, the material of the second active layer includes an oxide semiconductor, which may be a metal oxide semiconductor.

In some embodiments, as shown in fig. 8, 9 and 10, the first active layer 205 includes an active pattern T12A of the second control transistor T12, an active pattern T2A of the third control transistor T2, an active pattern T3A of the fifth control transistor T3, an active pattern T18A of the seventh control transistor T18, an active pattern T22A of the ninth control transistor T22, an active pattern T6A of the first output transistor T6, an active pattern T7A of the second output transistor T7, an active pattern T24A of the third output transistor T24, an active pattern T25A of the fourth output transistor T25, an active pattern T9A of the sixth output transistor T9, an active pattern T8A of the first switch transistor T8, an active pattern T23A of the second switch transistor T23, an active pattern T5A of the fourth switch transistor T5, an active pattern T16A of the first frequency dividing transistor T16, an active pattern T16A of the third output transistor T11A, an active pattern T20A of the fourth output transistor T25, and an active pattern T20A of the fourth output transistor T20.

Specifically, as shown in fig. 10, in the first direction X, an active pattern T9A of the sixth output transistor T9, an active pattern T11A of the second frequency dividing transistor T11, an active pattern T16A of the first frequency dividing transistor T16, an active pattern T12A of the second control transistor T12, an active pattern T2A of the third control transistor T2, an active pattern T19A of the fourth frequency dividing transistor T19, an active pattern T8A of the first switching transistor T8, and an active pattern T6A of the first output transistor T6 are sequentially arranged; the active pattern T5A of the fourth switching transistor T5, the active pattern T18A of the seventh control transistor T18, and the active pattern T22A of the ninth control transistor T22 are sequentially disposed along the first direction X; the active pattern T12A of the second control transistor T12, the active pattern T15A of the reset transistor T15, and the active pattern T3A of the fifth control transistor T3 are sequentially disposed along the second direction Y; the active pattern T8A of the first switching transistor T8 and the active pattern T23A of the second switching transistor T23 are sequentially disposed along the second direction Y; along the second direction Y, the active pattern T6A of the first output transistor T6, the active pattern T7A of the second output transistor T7, the active pattern T24A of the third output transistor T24, and the active pattern T25A of the fourth output transistor T25 are sequentially disposed, and an included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

In some embodiments, as shown in fig. 8, 9 and 11, the first gate layer 207 includes a gate T12G of the second control transistor T12, a gate T2G of the third control transistor T2, a gate T3G of the fifth control transistor T3, a gate T18G of the seventh control transistor T18, a gate T22G of the ninth control transistor T22, a gate T6G of the first output transistor T6, a gate T7G of the second output transistor T7, a gate T24G of the third output transistor T24, a gate T25G of the fourth output transistor T25, a gate T9G of the sixth output transistor T9, a gate T8G of the first switch transistor T8, a gate T23G of the second switch transistor T5, a gate T5G of the first frequency dividing transistor T16, a gate T11G of the third frequency dividing transistor T20G, a gate 20G of the fourth frequency dividing transistor T19, a gate capacitance of the fourth gate plate T19C 1a, and a capacitance C2a of the fourth gate plate C3a, C2a capacitance of the fourth gate plate 15 a, C2 a.

In particular, the method comprises the steps of, the gate T12G of the second control transistor T12, the gate T2G of the third control transistor T2, the gate T3G of the fifth control transistor T3, the gate T18G of the seventh control transistor T18, the gate T22G of the ninth control transistor T22, the gate T6G of the first output transistor T6, the gate T7G of the second output transistor T7, the gate T24G of the third output transistor T24, the gate T25G of the fourth output transistor T25, the gate T9G of the sixth output transistor T9, the gate T8G of the first switching transistor T8, the gate T23G of the second switching transistor T23, the gate T5G of the fourth switching transistor T5, the gate T16G of the first frequency dividing transistor T16, the gate T11G of the second frequency dividing transistor T11, the gate T20G of the third frequency dividing transistor T20, the gate T19G of the fourth frequency dividing transistor T19 and the gate 15 are respectively in a pattern with the second control transistor T12A an active pattern T2A of the third control transistor T2, an active pattern T3A of the fifth control transistor T3, an active pattern T18A of the seventh control transistor T18, an active pattern T22A of the ninth control transistor T22, an active pattern T6A of the first output transistor T6, an active pattern T7A of the second output transistor T7, an active pattern T24A of the third output transistor T24, an active pattern T25A of the fourth output transistor T25, an active pattern T9A of the sixth output transistor T9, an active pattern T8A of the first switching transistor T8, an active pattern T23A of the second switching transistor T23, an active pattern T5A of the fourth switching transistor T5, an active pattern T16A of the first frequency dividing transistor T16, an active pattern T11A of the second frequency dividing transistor T11, an active pattern T20A of the third frequency dividing transistor T20, an active pattern T19A of the fourth frequency dividing transistor T19 and an active pattern T15A of the corresponding reset transistor 15 are provided, the first plate C1a of the first capacitor C1 is connected to the gate T6G of the first output transistor T6, the first plate C4a of the second capacitor C4 is connected to the gate T24G of the third output transistor T24, the first plate C2a of the third capacitor C2 is connected to the gate T11G of the second frequency dividing transistor T11, and the first plate C3a of the fourth capacitor C3 is connected to the gate T19G of the fourth frequency dividing transistor T19.

Specifically, it can be understood that, in the actual design process, the transistors, the capacitors and the traces are not separately arranged and then connected by the traces, but the same structure is adopted as a plurality of elements or a plurality of electrodes, so in the drawing in the embodiment of the present application, a part of the structures are marked by a plurality of labels, because a part of the structures can be used as an electrode or a plate of one element or as a trace, another part of the structures can be used as an electrode or a plate of another element or as a trace, for example, one structure in fig. 11 is used as both the gate T6G of the first output transistor T6 and the first plate C1a of the first capacitor C1, and the part of the structures used as the gate T6G of the first output transistor T6 can be determined according to the active pattern of the first output transistor T6, and the part of the structures used as the first plate C1a of the first capacitor C1 can be determined according to the setting position of the second plate C1b of the first capacitor C1, so that other labels and structures can not be described herein.

In some embodiments, as shown in fig. 8, 9 and 12, the second gate layer 209 includes a first gate T13Ga of the first control transistor T13, a first gate T1Ga of the fourth control transistor T1, a first gate T17Ga of the sixth control transistor T17, a first gate T21Ga of the eighth control transistor T21, a first gate T4Ga of the third switching transistor T4, a first gate T14Ga of the fifth switching transistor T14, a first gate T10Ga of the fifth output transistor T10, a second plate C1b of the first capacitor C1, a second plate C4b of the second capacitor C4, a second plate C2b of the third capacitor C2, and a second plate C3b of the fourth capacitor C3.

Specifically, the first gate T10Ga of the fifth output transistor T10, the first gate T13Ga of the first control transistor T13, the first gate T1Ga of the fourth control transistor T1, and the first plate C1a of the first capacitor C1 are disposed along the first direction, the first gate T4Ga of the third switch transistor T4, the first gate T17Ga of the sixth control transistor T17, and the first gate T21Ga of the eighth control transistor T21 are disposed along the first direction, the first gate T13Ga of the first control transistor T13 and the first gate T14Ga of the fifth switch transistor T14 are disposed along the second direction, the second plate C1b of the first capacitor C1 and the second plate C4b of the second capacitor C4 are disposed corresponding to the first plate C1a of the first capacitor C1, the second plate C4b of the second capacitor C4 and the second plate C4a of the second capacitor C4 are disposed corresponding to the second plate C2a of the second capacitor C4, and the second plate C2b of the fourth capacitor C3b is disposed corresponding to the second plate C2b of the second capacitor C3a of the fourth capacitor C4.

In some embodiments, as shown in fig. 8, 9, and 13, the second active layer 211 includes an active pattern T13A of the first control transistor T13, an active pattern T1A of the fourth control transistor T1, an active pattern T17A of the sixth control transistor T17, an active pattern T21A of the eighth control transistor T21, an active pattern T4A of the third switching transistor T4, an active pattern T14A of the fifth switching transistor T14, and an active pattern T10A of the fifth output transistor T10, an active pattern T13A of the first control transistor T13, and an active pattern T1A of the fourth control transistor T1 are disposed in a first direction, an active pattern T4A of the third switching transistor T4, an active pattern T17A of the sixth control transistor T17, and an active pattern T21A of the eighth control transistor T21 are disposed in a first direction, the active patterns T13A and T14A of the first and fifth switching transistors T13 and T14 are disposed along the second direction, and the active patterns T13A and T1A of the first and fourth control transistors T13 and T1A and T17A of the sixth and eighth control transistors T17 and T21A and T21 and T4A of the third and fifth switching transistors T4 and T14A and T10A of the fifth and fifth output transistors T14 and T10 are disposed corresponding to the first gates T13Ga and T1Ga of the first and fourth control transistors T13 and T1 and T17Ga of the sixth control transistors T17 and T21Ga of the eighth and T21 and T4 and T14 and the first and fifth gates T10Ga of the fifth switching transistors T14 and T10, respectively.

In some embodiments, as shown in fig. 8, 9 and 14, the third gate layer 213 includes a second gate T13Gb of the first control transistor T13, a second gate T1Gb of the fourth control transistor T1, a second gate T17Gb of the sixth control transistor T17, a second gate T21Gb of the eighth control transistor T21, a second gate T4Gb of the third switching transistor T4, a second gate T14Gb of the fifth switching transistor T14, a second gate T13Gb of the fifth output transistor T10, and a plurality of rows of first scan signal lines, the second gate T13Gb of the first control transistor T13, the second gate T1Gb of the fourth control transistor T1, the second gate T17Gb of the sixth control transistor T17, the second gate T21Gb of the eighth control transistor T21, the second gate T4Gb of the third switching transistor T4, the second gate T14Gb of the fifth switching transistor T14, and the fifth output transistor T14 are disposed along the first scan signal line pattern T10A, the fifth scan signal line pattern a of the fifth control transistor T10, the fifth output transistor T14A, and the fifth scan signal line pattern a 1A, the fifth output transistor T14A, the fifth output transistor T10 are disposed along the first scan signal line pattern T10A, the fifth signal line T1A, the fifth gate pattern a 1Gb of the fifth control transistor T1, the fifth control transistor T17, the fifth control transistor T21Gb is disposed.

Specifically, as shown in fig. 14, the nth row first scanning signal line Pscan (n) and the n+1th row first scanning signal line Pscan (n+1) are shown in fig. 14, and it is understood that the nth row first scanning signal line Pscan (n) and the n+1th row first scanning signal line Pscan (n+1) are adjacent two row first scanning signal lines that drive transistors in adjacent two rows of pixel units.

Specifically, taking a pixel driving circuit in which the display panel includes 7T2C (7 transistors and 2 capacitors) or 8T2C (8 transistors and 2 capacitors) as an example, the first scan signal line may be connected to a switching transistor in the pixel driving circuit.

Specifically, as shown in fig. 17, the display portion 21 is provided with a pixel driving circuit 110 including a driving transistor T31, a pixel switching transistor T32, a compensation transistor T33, a first initialization transistor T34, a first light emitting transistor T35, a second light emitting transistor T36, a second initialization transistor T37, and a third initialization transistor T38, a gate of the pixel switching transistor T32 is connected to a first scanning signal line Pscan (n), a first electrode of the pixel switching transistor T32 is connected to a Data signal line Data, a second electrode of the pixel switching transistor T32 is connected to a first electrode of the driving transistor T31, a gate of the compensation transistor T33 is connected to a second scanning signal line Nscan1, a first electrode of the compensation transistor T33 is connected to a second electrode of the first initialization transistor T34, a second electrode of the compensation transistor T33 is connected to a second electrode of the driving transistor T31, the gate of the first initialization transistor T34 is connected to the third scan signal line Nscan, the first electrode of the first initialization transistor T34 is connected to the first initialization line Vi1, the gate of the first initialization transistor T35 is connected to the light emission control line EM, the first electrode of the first initialization transistor T35 is connected to the power high potential signal line VDD, the second electrode of the first initialization transistor T35 is connected to the first electrode of the driving transistor T31, the gate of the second initialization transistor T36 is connected to the light emission control line EM, the first electrode of the second initialization transistor T36 is connected to the second electrode of the driving transistor T31, the second electrode of the second initialization transistor T36 is connected to the light emitting device LED, the gate of the second initialization transistor T37 is connected to the fourth scan signal line Pscan, the first electrode of the second initialization transistor T37 is connected to the second initialization line Vi2, the second electrode of the second initialization transistor T37 is connected to the light emitting device LED, the gate of the third initialization transistor T38 is connected to the fourth scan signal line Pscan, the first electrode of the third initialization transistor T38 is connected to the third initialization line Vi3, and the second electrode of the third initialization transistor T38 is connected to the first electrode of the driving transistor T31.

Specifically, as shown in fig. 17, the light emitting device LED is connected to the low-power-supply potential signal line VSS, and the pixel driving circuit further includes a storage capacitor Cst and a boost capacitor Cboost, where one end of the storage capacitor Cst is connected to the high-power-supply potential signal line VDD, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor T31; one end of the boost capacitor Cboost is connected to the gate of the pixel switching transistor T32, and the other end of the boost capacitor Cboost is connected to the gate of the driving transistor T31.

Specifically, it can be understood that the n-th row first scanning signal line Pscan (n) is a signal output by the first signal output terminal Pout1 (n) of the present stage gate driving circuit, the n+1-th row first scanning signal line Pscan (n+1) is a signal output by the second signal output terminal Pout2 (n) of the present stage gate driving circuit, the n-th row first scanning signal line Pscan (n) and the n+1-th row first scanning signal line Pscan (n+1) are connected to gates of the pixel switching transistors T32 in the n-th row pixel driving circuit and the n+1-th row pixel driving circuit, the signal of the second scanning signal line Nscan1 may be a signal output by the third signal output terminal Nout (n) of the present stage gate driving unit, the signal of the second scanning signal line Nscan2 may be a signal output by the first signal output terminal of the upper five stage gate driving unit, and the signal of the fourth scanning signal line Pscan may be a signal output by other gate driving unit. However, the embodiments of the present application are not limited thereto, and the signals of the gate connections of the compensation transistor and the first initialization transistor may be set according to the requirements.

Specifically, the driving transistor T31, the pixel switching transistor T32, the first light emitting transistor T35, the second light emitting transistor T36, the second initialization transistor T37, and the third initialization transistor T38 are silicon semiconductor transistors, and the compensation transistor T33 and the first initialization transistor T34 are oxide semiconductor transistors.

Specifically, the driving transistor T31, the pixel switching transistor T32, the first light emitting transistor T35, the second light emitting transistor T36, the second initialization transistor T37, and the third initialization transistor T38 are P-type transistors, and the compensation transistor T33 and the first initialization transistor T34 are N-type transistors.

In some embodiments, as shown in fig. 8, 9 and 15, the first source-drain layer 215 includes a first electrode T13S of the first control transistor T13, a second electrode T13D of the first control transistor T13, a first electrode T12D of the second control transistor T12, a second electrode T12D of the second control transistor T12, a first electrode T2S of the third control transistor T2, a second electrode T2D of the third control transistor T2, a first electrode T1S of the fourth control transistor T1, a second electrode T8T 1D of the fourth control transistor T3, a second electrode T3D of the fifth control transistor T3, a first electrode T17S of the sixth control transistor T17, a second electrode T17D of the sixth control transistor T17, a first electrode T18S of the seventh control transistor T18, a second electrode T18D of the third control transistor T18D, a second electrode T22D of the fourth electrode T8T 7T 21D of the fourth control transistor T21, a first electrode T10D of the fourth output switch transistor T10D, a third electrode T25D of the fourth output switch transistor T10T 22, a third electrode T25D of the fourth output 10T 9D, a third output 10T 9S of the fourth output switch transistor T22D, a third output 10T 9S of the fourth output 10T 7S, a third output 10D, a third output electrode T9S 8T 7D, a third output transistor T7D, a third output 7D, the second electrode T23D of the second switching transistor T23, the first electrode T4S of the third switching transistor T4, the second electrode T4D of the third switching transistor T4, the first electrode T5S of the fourth switching transistor T5, the second electrode T5D of the fourth switching transistor T5, the first electrode T14S of the fifth switching transistor T14, the second electrode T14D of the fifth switching transistor T14, the first electrode T16S of the first dividing transistor T16, the second electrode T16D of the first dividing transistor T16, the first electrode T11S of the second dividing transistor T11, the second electrode T11D of the second dividing transistor T11, the first electrode T20S of the third dividing transistor T20, the second electrode T20D of the third dividing transistor T20, the first electrode T19S of the fourth dividing transistor T19, the second electrode T19D of the fourth dividing transistor T19, the first electrode T11S of the first dividing transistor T15S of the reset transistor T15 and the second electrode T15S of the reset transistor T15.

In some embodiments, as shown in fig. 8, 9 and 16, the second source-drain layer 217 includes a second high-potential signal line NVGH, a first low-potential signal line NVGL, a first frequency-dividing signal line NLF, a Control signal line Control, two first high-potential signal lines PVGH, a second frequency-dividing signal line PLF, a second low-potential signal line PVGL, a start signal line STV, a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3 and a fourth clock signal line PCK4;

The second high-potential signal line NVGH, the first low-potential signal line NVGL, the first frequency-divided signal line NLF, the Control signal line Control, the second frequency-divided signal line PLF, the second low-potential signal line PVGL, the fourth clock signal line PCK4, the second clock signal line PCK2, the third clock signal line PCK3, the start signal line STV, and the first clock signal line PCK1 are sequentially arranged in a first direction X, one of the first high-potential signal lines PVGH is arranged between the Control signal line Control and the second frequency-divided signal line PLF, and the other of the first high-potential signal lines PVGH is arranged between the second clock signal line PCK2 and the third clock signal line PCK 3. According to the embodiment of the application, the first clock signal line and the third clock signal line are arranged on the two sides of the initial signal line, so that the first clock signal line and the third clock signal line are overlapped with the projection of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor on the substrate, the loads of the first clock signal line and the third clock signal line can be increased, and the loads of the first clock signal line and the third clock signal line are similar to or even the same as the loads of the second clock signal line and the fourth clock signal line, thereby avoiding dense cross stripes during display.

Specifically, the projection of the first clock signal line on the substrate coincides with the gate of the first output transistor, the projection of the first clock signal line on the substrate coincides with the active pattern of the first output transistor, the projection of the first clock signal line on the substrate coincides with the first electrode of the first output transistor, and the projection of the first clock signal line on the substrate coincides with the second electrode of the first output transistor; the projection of the first clock signal line on the substrate coincides with the grid electrode of the second output transistor, the projection of the first clock signal line on the substrate coincides with the active pattern of the second output transistor, the projection of the first clock signal line on the substrate coincides with the first electrode of the second output transistor, and the projection of the first clock signal line on the substrate coincides with the second electrode of the second output transistor; the projection of the first clock signal line on the substrate coincides with the gate of the third output transistor, the projection of the first clock signal line on the substrate coincides with the active pattern of the third output transistor, the projection of the first clock signal line on the substrate coincides with the first electrode of the third output transistor, and the projection of the first clock signal line on the substrate coincides with the second electrode of the third output transistor; the projection of the first clock signal line on the substrate coincides with the gate of the fourth output transistor, the projection of the first clock signal line on the substrate coincides with the active pattern of the fourth output transistor, the projection of the first clock signal line on the substrate coincides with the first electrode of the fourth output transistor, and the projection of the first clock signal line on the substrate coincides with the second electrode of the fourth output transistor.

Specifically, the projection of the third clock signal line on the substrate coincides with the gate of the first output transistor, the projection of the third clock signal line on the substrate coincides with the active pattern of the first output transistor, the projection of the third clock signal line on the substrate coincides with the first electrode of the first output transistor, and the projection of the third clock signal line on the substrate coincides with the second electrode of the first output transistor; the projection of the third clock signal line on the substrate is overlapped with the grid electrode of the second output transistor, the projection of the third clock signal line on the substrate is overlapped with the active pattern of the second output transistor, the projection of the third clock signal line on the substrate is overlapped with the first electrode of the second output transistor, and the projection of the third clock signal line on the substrate is overlapped with the second electrode of the second output transistor; the projection of the third clock signal line on the substrate is overlapped with the grid electrode of the third output transistor, the projection of the third clock signal line on the substrate is overlapped with the active pattern of the third output transistor, the projection of the third clock signal line on the substrate is overlapped with the first electrode of the third output transistor, and the projection of the third clock signal line on the substrate is overlapped with the second electrode of the third output transistor; the projection of the third clock signal line on the substrate coincides with the gate of the fourth output transistor, the projection of the third clock signal line on the substrate coincides with the active pattern of the fourth output transistor, the projection of the third clock signal line on the substrate coincides with the first electrode of the fourth output transistor, and the projection of the third clock signal line on the substrate coincides with the second electrode of the fourth output transistor.

In some embodiments, as shown in fig. 7, 8, 9, and 16, the projection of the second clock signal line PCK2 on the substrate 201 coincides with the projection of the second electrode T19D of the fourth frequency dividing transistor T19 on the substrate 201, and the projection of the first high potential signal line PVGH on the substrate 201 coincides with the projection of the second electrode T8D of the first switching transistor T8 and the projection of the second electrode T23D of the second switching transistor T23 on the substrate 201. By overlapping the projection of the second clock signal line on the substrate with the projection of the second electrode of the fourth frequency dividing transistor on the substrate, the projection of the first high potential signal line on the substrate overlaps with the projection of the second electrode of the first switching transistor and the projection of the second electrode of the second switching transistor on the substrate, the overlapping of the first clock signal line, the third clock signal line and the output transistor can be realized by changing the positions of the signal lines, the line width of the signal lines does not need to be changed, and components do not need to be increased.

In some embodiments, the first set of clock signal lines includes a first clock signal line and a third clock signal line, the second set of clock signal lines includes a second clock signal line and a fourth clock signal line, in two adjacent stages of the gate driving units, the first output module in one stage of the gate driving unit is connected to the first clock signal line, the second output module is connected to the second clock signal line, and the third clock signal line is connected to a gate of a control transistor; the first output module in the grid driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, and the first clock signal line is connected with the grid of the control transistor;

wherein there is coincidence of an orthographic projection of at least one of the second clock signal line and the fourth clock signal line with an orthographic projection of at least one of the output transistors.

Specifically, for the first group of clock signal lines and the second group of clock signal lines, one group of clock signal lines can be multiplexed into the clock signal line of the grid electrode of the driving transistor, and the other group of clock signal lines are overlapped with the orthographic projection of the output transistor, so that the loads of the clock signal lines are similar or even the same, and abnormal display is avoided. In the above embodiment, the first output module in the first stage of the gate driving unit is connected to the first clock signal line, the second output module is connected to the second clock signal line, and the fourth clock signal line is connected to the gate of the control transistor; the first output module in the gate driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, the second clock signal line is connected with the gate of the control transistor, the orthographic projection of the first clock signal line is overlapped with the orthographic projection of at least one output transistor, the orthographic projection of the third clock signal line is overlapped with the orthographic projection of at least one output transistor, it is understood that the first output module in the gate driving unit of the one stage is connected with the first clock signal line, the second output module is connected with the second clock signal line, and the third clock signal line is connected with the gate of the control transistor; the first output module in the grid driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, the first clock signal line is connected with the grid of the control transistor, the orthographic projection of the second clock signal line is overlapped with the orthographic projection of at least one output transistor, and when the orthographic projection of the fourth clock signal line is overlapped with the orthographic projection of at least one output transistor, the design of each film layer and the design of connecting lines of each film layer can be correspondingly changed, the line width of a wiring is not increased, components are not increased, and the repeated description is omitted.

In some embodiments, as shown in fig. 6 to 16, the display portion 21 includes a plurality of rows of first scanning signal lines, and the first output module 501 and the second output module 502 are connected to two adjacent rows of the first scanning signal lines. By connecting the first output module and the second output module to the adjacent two rows of the first scanning signal lines, the frame of the display panel can be reduced.

Specifically, the first output module 501 in the n-th stage gate driving unit may be connected to the n-th row first scan signal line Pscan (n), and the second output module 502 in the n-th stage gate driving unit may be connected to the n+1-th row first scan signal line Pscan (n+1).

Specifically, as shown in fig. 8, the embodiment of the present application shows two stages of gate driving units, and it is understood that the two stages of gate driving units form a repeating unit, and the design of other stages of gate driving units can be referred to the design of the two stages of gate driving circuits.

Specifically, as shown in fig. 5 and 9, it can be seen that the first clock signal line PCK1, the second clock signal line PCK2, the third clock signal line PCK3 and the fourth clock signal line PCK4 are disposed adjacent to each other in the comparative display device, and the second clock signal line PCK2 and the fourth clock signal line PCK4 need to be connected to the gates of the transistors, so that the loads of the second clock signal line PCK2 and the fourth clock signal line PCK4 are different from the loads of the first clock signal line PCK1 and the third clock signal line PCK3, and in the embodiment of the application, the first clock signal line PCK1 and the third clock signal line PCK3 are correspondingly disposed with the first output transistor, the second output transistor, the third output transistor and the fourth output transistor, so that the loads of the first clock signal line PCK1, the second clock signal line PCK2, the third clock signal line PCK3 and the fourth clock signal line PCK4 are similar to each other, and the widths of the wiring lines do not need to be changed, and the line width does not need to be increased, and the device does not need to be increased.

Specifically, it is understood that the transistors, capacitors, traces and nodes may be located in different layers, and in order to implement connection of the transistors, capacitors, traces and nodes, connection lines may be provided, as shown in fig. 9 and 12, the second gate layer 209 includes a first connection line L1, as shown in fig. 9 and 14, the third gate layer 213 includes a second connection line L2 and a third connection line L3, as shown in fig. 9 and 15, and the first source-drain layer 215 includes a fourth connection line L4, a fifth connection line L5, a sixth connection line L6, a seventh connection line L7, an eighth connection line L8 and a ninth connection line L9.

Specifically, as shown in fig. 9 to 16, the second divided signal line PLF is connected to the sixth connection line L6, the sixth connection line L6 is connected to the first connection line L1, and the first connection line L1 is connected to the first electrode T20S of the third divided transistor T20, thereby realizing connection of the second divided signal line PLF to the first electrode T20S of the third divided transistor T20.

Specifically, as shown in fig. 9 to 16, the second connection line L2 connects the internal node P (n-2) in the two-stage gate driving unit and the gate T8G of the first switching transistor T8 and the gate T23G of the second switching transistor T23 in the present-stage gate driving circuit.

Specifically, as shown in fig. 9 to 16, the third connection line L3 connects the second electrode T9S of the sixth output transistor T9 and the third output signal line Nout (n).

Specifically, as shown in fig. 9 to 16, the fourth connection line L4 connects the gate electrode T2G of the third control transistor T2 and the third group of clock signal lines, and as can be seen from fig. 15, the fourth connection line L4 of the upper gate driving unit connects the fourth clock signal line PCK4 and the gate electrode T2G of the third control transistor T2, the fourth connection line L4 of the lower gate driving unit connects the second clock signal line PCK2 and the gate electrode T2G of the third control transistor T2, the structures of the fourth connection lines L4 in the adjacent two-stage gate driving units are different, and particularly, it can be seen that the width of the fourth connection line L4 of the upper gate driving unit is smaller than the width of the fourth connection line L4 of the lower gate driving unit, because the fourth clock signal line PCK4 is closer to the gate electrode of the third control transistor T2 than the second clock signal line PCK2, and the structure of the fourth connection line L4 can be changed accordingly for other designs.

Specifically, as shown in fig. 9 to 16, the fifth connection line L5 connects the gate T15G of the reset transistor T15 and the Control signal line Control.

Specifically, as shown in fig. 9 to 16, the eighth connection line L8 connects the gate of the first control transistor T13 and the gate of the second control transistor T12, and the seventh connection line L7 connects the internal node P (n-1) of the gate driving unit of the previous stage and the gate of the second control transistor T12, so that when the start signal line STV inputs a signal of the internal node P (n-1) of the gate driving unit of the previous stage, connection of the start signal line STV and the gates of the first control transistor T13 and the second control transistor T12 is achieved.

Specifically, as shown in fig. 9 to 16, the ninth connection line L9 connects the gate of the ninth control transistor T22 and the gate of the fourth output transistor T25.

Specifically, as shown in fig. 9 to 16, the tenth connection line L10 connects the gate electrode T21G of the eighth control transistor T21 and the third group of clock signal lines, and as can be seen from fig. 15, the tenth connection line L10 of the upper gate driving unit connects the fourth clock signal line PCK4 and the gate electrode T21G of the eighth control transistor T21, the tenth connection line L10 of the lower gate driving unit connects the second clock signal line PCK2 and the gate electrode T21G of the eighth control transistor T21, the tenth connection line L10 in the adjacent two-stage gate driving units has a different structure, and in particular, it can be seen that the width of the tenth connection line L10 of the upper gate driving unit is smaller than the width of the tenth connection line L10 of the lower gate driving unit, because the fourth clock signal line PCK4 is closer to the gate electrode T21G of the eighth control transistor T21 than the second clock signal line PCK2, and the structure of the tenth connection line L10 can be changed accordingly for other designs.

Specifically, as shown in fig. 9 to 16, the eleventh connection line L11 is connected to the first scanning signal line Pscan (n).

Specifically, as shown in fig. 7, the display panel 2 includes a substrate 201, a shielding layer 202, a barrier layer 203, a buffer layer 204, a first active layer 205, a first gate insulating layer 206, a first gate layer 207, a second gate insulating layer 208, a second gate layer 209, a third gate insulating layer 210, a second active layer 211, a fourth gate insulating layer 212, a third gate layer 213, a first interlayer insulating layer 214, a first source/drain layer 215, a first planarization layer 216, a second source/drain layer 217, a second planarization layer 218, a third source/drain layer 219, a third planarization layer 220, a pixel electrode layer 221, and a pixel defining layer 222, wherein the shielding layer 202 is disposed on one side of the substrate 201, the barrier layer 203 is disposed on one side of the shielding layer 202 away from the substrate 201, the buffer layer 204 is disposed on one side of the barrier layer 203 away from the shielding layer 202, the first gate insulating layer 206 is disposed between the first active layer 205 and the first gate layer 207, the second gate insulating layer 208 is disposed between the first gate layer 207 and the second gate layer 209, the third gate insulating layer 215 is disposed between the first gate layer 215 and the second gate layer 215, the third gate insulating layer 215 is disposed between the second drain layer 215 and the third gate layer 215, the third planarization layer 215 is disposed between the second source/drain layer 215 and the third planarization layer 215, the third planarization layer 219 is disposed between the first drain layer 211 and the second gate insulating layer 211 and the second drain layer 221, the second planarization layer 221 is disposed between the second gate insulating layer 211 and the second source/drain layer 219, the second planarization layer and the second drain layer 219 is disposed between the second gate insulating layer and the second layer.

Specifically, the first electrode of the transistor in the above embodiment is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiment is a drain electrode and the second electrode is a source electrode.

Specifically, the second control transistor, the third control transistor, the fifth control transistor, the seventh control transistor, the ninth control transistor, the first output transistor, the second output transistor, the third output transistor, the fourth output transistor, the sixth output transistor, the first switch transistor, the second switch transistor, the fourth switch transistor, the first frequency dividing transistor, the second frequency dividing transistor, the third frequency dividing transistor, the fourth frequency dividing transistor, and the reset transistor are P-type transistors; the first control transistor, the fourth control transistor, the sixth control transistor, the eighth control transistor, the third switching transistor, the fifth switching transistor, and the fifth output transistor are N-type transistors.

Specifically, the second control transistor, the third control transistor, the fifth control transistor, the seventh control transistor, the ninth control transistor, the first output transistor, the second output transistor, the third output transistor, the fourth output transistor, the sixth output transistor, the first switch transistor, the second switch transistor, the fourth switch transistor, the first frequency dividing transistor, the second frequency dividing transistor, the third frequency dividing transistor, the fourth frequency dividing transistor, and the reset transistor are silicon semiconductor transistors; the first control transistor, the fourth control transistor, the sixth control transistor, the eighth control transistor, the third switching transistor, the fifth switching transistor, and the fifth output transistor are oxide semiconductor transistors.

Specifically, the oxide semiconductor transistor may be a metal oxide transistor, and the silicon semiconductor transistor may be a low-temperature polysilicon transistor.

Specifically, the foregoing embodiments have specifically described the display panel from each circuit, each film layer, each structure, and combinations thereof, and it is understood that when there is no conflict in each embodiment, each embodiment may be combined, for example, the first group of clock signal lines includes a first clock signal line and a third clock signal line, the second group of clock signal lines includes a second clock signal line and a fourth clock signal line, in two adjacent stages of the gate driving units, the first output module in a stage of the gate driving unit is connected to the first clock signal line, the second output module is connected to the second clock signal line, and the third clock signal line is connected to the gate of the control transistor; the first output module in the grid driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, and the first clock signal line is connected with the grid of the control transistor; wherein there is a coincidence of an orthographic projection of at least one of the second clock signal line and the fourth clock signal line with an orthographic projection of at least one of the output transistors; the display part comprises a plurality of rows of first scanning signal lines, and the first output module and the second output module are connected with two adjacent rows of first scanning signal lines.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The display panel and the display device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A display panel comprising a display portion and a gate driving circuit located on at least one side of the display portion, the gate driving circuit comprising a plurality of cascaded gate driving units, the gate driving unit comprising:

2. The display panel according to claim 1, wherein the first group of clock signal lines includes a first clock signal line and a third clock signal line, the second group of clock signal lines includes a second clock signal line and a fourth clock signal line, the first output module in one stage of the gate driving units is connected to the first clock signal line, the second output module is connected to the second clock signal line, and the fourth clock signal line is connected to a gate of the control transistor in adjacent two stages of the gate driving units; the first output module in the gate driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, and the second clock signal line is connected with the gate of the control transistor;

wherein there is a coincidence of an orthographic projection of at least one of the first clock signal line and the third clock signal line with an orthographic projection of at least one of the output transistors.

3. The display panel of claim 2, wherein the front projection of the first clock signal line coincides with the front projection of at least one of the output transistors, and the front projection of the third clock signal line coincides with the front projection of at least one of the output transistors.

4. The display panel according to claim 3, wherein the first control module includes a first control transistor, a second control transistor, a third control transistor, a first high potential signal line, a first low potential signal line, and a start signal line, a gate of the first control transistor and a gate of the second control transistor are connected to the start signal line, a first electrode of the first control transistor is connected to the first low potential signal line, a first electrode of the second control transistor is connected to the first high potential signal line, a second electrode of the first control transistor and a second electrode of the second control transistor are connected to a first electrode of a third control transistor, a gate of the third control transistor is connected to a third group of clock signal lines, and a second electrode of the third control transistor is connected to the first node; the second clock signal line and the fourth clock signal line are shared by the third group of clock signal lines and the second group of clock signal lines, in each stage of the gate driving unit, the second output module is connected with the second group of clock signal lines, the gate of the third control transistor is connected with the third group of clock signal lines, in two adjacent stages of gate driving units, one stage of the gate driving unit is connected with the second clock signal line, the gate of the third control transistor is connected with the fourth clock signal line, the other stage of the gate driving unit is connected with the fourth clock signal line, and the gate of the third control transistor is connected with the second clock signal line;

The first output module comprises a first switch transistor, a first output transistor, a second output transistor, a first capacitor and a first output signal line, wherein the grid electrode of the first switch transistor is connected with the internal node of the upper two stages of grid driving units, the first electrode of the first switch transistor is electrically connected with the first node, the second electrode of the first switch transistor, a polar plate of the first capacitor and the grid electrode of the first output transistor are connected, the first electrode of the first output transistor is connected with a first group of clock signal lines, the second electrode of the first output transistor, the second electrode of the second output transistor, the other polar plate of the first capacitor and the first output signal line are connected, the grid electrode of the second output transistor is connected with the internal node of the local stage of grid driving units, and the first electrode of the second output transistor is connected with the first high potential signal line;

The second output module comprises a second switch transistor, a third output transistor, a fourth output transistor, a second capacitor and a second output signal line, wherein the grid electrode of the second switch transistor is connected with the internal node of the upper two stages of grid driving units, the first electrode of the second switch transistor is connected with the first node, the second electrode of the second switch transistor, a polar plate of the second capacitor and the grid electrode of the third output transistor are connected, the first electrode of the third output transistor is connected with a second group of clock signal lines, the second electrode of the third output transistor, the second electrode of the fourth output transistor, the other polar plate of the second capacitor and the second output signal line are connected, the grid electrode of the fourth output transistor is connected with the internal node of the local stage of grid driving units, and the first electrode of the fourth output transistor is connected with the first high-potential signal line;

The orthographic projection of the first clock signal line is overlapped with orthographic projections of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor, and the orthographic projection of the third clock signal line is overlapped with orthographic projections of the first output transistor, the second output transistor, the third output transistor and the fourth output transistor.

5. The display panel of claim 4, wherein the display panel comprises:

A substrate;

the first active layer is arranged on one side of the substrate;

the first grid electrode layer is arranged on one side of the first active layer, which is far away from the substrate;

The second grid electrode layer is arranged on one side of the first grid electrode layer, which is far away from the first active layer;

the second active layer is arranged on one side of the second grid electrode layer far away from the first grid electrode layer;

the third grid electrode layer is arranged on one side of the second active layer, which is far away from the second grid electrode layer;

the first source-drain electrode layer is arranged on one side of the third grid electrode layer far away from the second active layer;

the second source-drain electrode layer is arranged on one side of the first source-drain electrode layer, which is far away from the third grid electrode layer;

The second source-drain electrode layer comprises the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line.

6. The display panel of claim 5, wherein the first active layer includes an active pattern of a second control transistor, an active pattern of a third control transistor, an active pattern of a first output transistor, an active pattern of a second output transistor, an active pattern of a third output transistor, an active pattern of a fourth output transistor, an active pattern of a first switch transistor, and an active pattern of a second switch transistor, the active pattern of the second control transistor, the active pattern of the third switch transistor, and the active pattern of the first output transistor are disposed in a first direction, the active pattern of the first switch transistor is disposed in a second direction with the active pattern of the second switch transistor, the active pattern of the first output transistor, the active pattern of the second output transistor, the active pattern of the third output transistor, and the active pattern of the fourth output transistor are disposed in the second direction, and an included angle between the first direction and the second direction is equal to or greater than 0.

7. The display panel of claim 6, wherein the first gate layer comprises a gate of the second control transistor, a gate of the third control transistor, a gate of the first output transistor, a gate of the second output transistor, a gate of the third output transistor, a gate of the fourth output transistor, a gate of the first switching transistor, a gate of the second switching transistor, a first plate of the first capacitor, and a first plate of the second capacitor, the gate of the second control transistor, the gate of the third control transistor, the gate of the first switch transistor, the gate of the second switch transistor, the gate of the first output transistor, the gate of the second output transistor, the gate of the third output transistor and the gate of the fourth output transistor are respectively arranged corresponding to the active pattern of the second control transistor, the active pattern of the third control transistor, the active pattern of the first switch transistor, the active pattern of the second switch transistor, the active pattern of the first output transistor, the active pattern of the second output transistor, the active pattern of the third output transistor and the active pattern of the fourth output transistor, the first electrode plate of the first capacitor is connected with the gate of the first output transistor, and the first electrode plate of the second capacitor is connected with the gate of the third output transistor.

8. The display panel of claim 7, wherein the second gate layer comprises a first gate of a first control transistor, a second plate of a first capacitor, and a second plate of a second capacitor, the first gate of the first control transistor and the second plate of the first capacitor being disposed along the first direction, the second plate of the first capacitor and the second plate of the second capacitor being disposed along the second direction, the second plate of the first capacitor and the first plate of the first capacitor being disposed in correspondence, and the second plate of the second capacitor and the first plate of the second capacitor being disposed in correspondence.

9. The display panel of claim 8, wherein the second active layer includes an active pattern of a first control transistor disposed corresponding to a first gate of the first control transistor.

10. The display panel of claim 9, wherein the third gate layer includes a second gate of the first control transistor and a plurality of rows of first scan signal lines, the plurality of rows of first scan signal lines being disposed along the second direction.

11. The display panel of claim 10, wherein the first source-drain layer includes a first electrode of a first control transistor, a second electrode of the first control transistor, a first electrode of a second control transistor, a second electrode of the second control transistor, a first electrode of a third control transistor, a second electrode of a third control transistor, a first electrode of a first output transistor, a second electrode of the first output transistor, a first electrode of a second output transistor, a second electrode of the second output transistor, a first electrode of a third output transistor, a second electrode of the third output transistor, a first electrode of a fourth output transistor, a second electrode of the fourth output transistor, a first electrode of the first switch transistor, a second electrode of the first switch transistor, a first electrode of the second switch transistor, and a second electrode of the second switch transistor.

12. The display panel of claim 11, wherein the second source-drain layer further comprises a first low potential signal line, two first high potential signal lines, and a start signal line;

the first low-potential signal line, the fourth clock signal line, the second clock signal line, the third clock signal line, the initial signal line and the first clock signal line are sequentially arranged along a first direction, one of the first high-potential signal lines is arranged between the first low-potential signal line and the fourth clock signal line, and the other of the first high-potential signal lines is arranged between the second clock signal line and the third clock signal line.

13. The display panel of claim 12, wherein the gate driving unit further comprises a frequency dividing module including a first frequency dividing module and a second frequency dividing module, the first frequency dividing module including a first frequency dividing transistor, a second frequency dividing transistor, a third capacitor, and a first frequency dividing signal line, a gate of the first frequency dividing transistor being connected to the internal node of the present stage gate driving unit, a first electrode of the first frequency dividing transistor being connected to the first frequency dividing signal line, a second electrode of the first frequency dividing transistor, a plate of the third capacitor, and a gate of the second frequency dividing transistor being connected to the first node, a second electrode of the second frequency dividing transistor being connected to the other plate of the third capacitor; the second frequency dividing module comprises a third frequency dividing transistor, a fourth capacitor and a second frequency dividing signal line, wherein a grid electrode of the third frequency dividing transistor is connected with the internal node of the gate driving unit of the stage, a first electrode of the third frequency dividing transistor is connected with the second frequency dividing signal line, a second electrode of the third frequency dividing transistor, a grid electrode of the fourth frequency dividing transistor is connected with one polar plate of the fourth capacitor, a first electrode of the fourth frequency dividing transistor is connected with the first node, and a second electrode of the fourth frequency dividing transistor is connected with the other polar plate of the fourth capacitor.

14. The display panel according to claim 13, wherein a projection of the second clock signal line onto the substrate coincides with a projection of the second electrode of the fourth frequency dividing transistor onto the substrate, and a projection of the first high potential signal line onto the substrate coincides with a projection of the second electrode of the first switching transistor and the second electrode of the second switching transistor onto the substrate.

15. The display panel of claim 12, wherein a projection of the first clock signal line onto the substrate coincides with a projection of the first electrode of the first output transistor and the second electrode of the first output transistor onto the substrate, a projection of the first clock signal line onto the substrate coincides with a projection of the first electrode of the second output transistor and the second electrode of the second output transistor onto the substrate, a projection of the first clock signal line onto the substrate coincides with a projection of the first electrode of the third output transistor and the second electrode of the third output transistor onto the substrate, and a projection of the first clock signal line onto the substrate coincides with a projection of the first electrode of the fourth output transistor and the second electrode of the fourth output transistor onto the substrate.

16. The display panel of claim 12, wherein a projection of the third clock signal line onto the substrate coincides with a projection of the first electrode of the first output transistor and the second electrode of the first output transistor onto the substrate, a projection of the third clock signal line onto the substrate coincides with a projection of the first electrode of the second output transistor and the second electrode of the second output transistor onto the substrate, a projection of the third clock signal line onto the substrate coincides with a projection of the first electrode of the third output transistor and the second electrode of the third output transistor onto the substrate, and a projection of the third clock signal line onto the substrate coincides with a projection of the first electrode of the fourth output transistor and the second electrode of the fourth output transistor onto the substrate.

17. The display panel of claim 4, wherein the gate driving unit further comprises:

The second control module comprises a fourth control transistor, a fifth control transistor and a second low-potential signal line, wherein the grid electrode of the fourth control transistor and the grid electrode of the fifth control transistor are connected with the first node, the first electrode of the fourth control transistor is connected with the second low-potential signal line, the first electrode of the fifth control transistor is connected with the first high-potential signal line, and the second electrode of the fourth control transistor and the second electrode of the fifth control transistor are connected with the internal node;

the output control unit comprises a third switch transistor, a fourth switch transistor and a fifth switch transistor, wherein the grid electrode of the third switch transistor is connected with the third group of clock signal lines, the first electrode of the third switch transistor is connected with the first node, the second electrode of the third switch transistor is connected with the second electrode of the fourth switch transistor, the grid electrode of the fourth switch transistor is connected with the internal node, the first electrode of the fourth switch transistor is connected with the first high-potential signal line, the grid electrode of the fifth switch transistor is connected with the internal node, the first electrode of the fifth switch transistor is connected with the first low-potential signal line, and the second electrode of the fifth switch transistor is connected with the first node;

A third control unit including a sixth control transistor and a seventh control transistor, a gate of the sixth control transistor being connected to the third group clock signal line, a first electrode of the sixth control transistor being electrically connected to the first node, a second electrode of the sixth control transistor being connected to a second electrode of the seventh control transistor, a gate of the seventh control transistor being connected to the internal node, a first electrode of the seventh control transistor being connected to the first high potential signal line;

A fourth control unit including an eighth control transistor and a ninth control transistor, a gate of the eighth control transistor being connected to a third group clock signal line, a first electrode of the eighth control transistor being electrically connected to the first node, a second electrode of the eighth control transistor being connected to a second electrode of the ninth control transistor, a gate of the ninth control transistor being connected to the internal node, a first electrode of the ninth control transistor being connected to the first high potential signal line;

The third output module comprises a fifth output transistor, a sixth output transistor, a second high-potential signal line and a third output signal line, wherein the grid electrode of the fifth output transistor is connected with the first node, the first electrode of the fifth output transistor is connected with the first low-potential signal line, the second electrode of the fifth output transistor, the second electrode of the sixth output transistor and the third output signal line are connected, the grid electrode of the sixth output transistor is electrically connected with the first node, and the first electrode of the sixth output transistor is connected with the second high-potential signal line;

the reset module comprises a reset transistor and a control signal line, wherein the grid electrode of the reset transistor is connected with the control signal line, the first electrode of the reset transistor is connected with the first high-potential signal line, and the second electrode of the reset transistor is connected with the first node.

18. The display panel according to claim 1, wherein the first group of clock signal lines includes a first clock signal line and a third clock signal line, the second group of clock signal lines includes a second clock signal line and a fourth clock signal line, the first output module in one stage of the gate driving units is connected to the first clock signal line, the second output module is connected to the second clock signal line, and the third clock signal line is connected to a gate of the control transistor in adjacent two stages of the gate driving units; the first output module in the grid driving unit of the other stage is connected with a third clock signal line, the second output module is connected with a fourth clock signal line, and the first clock signal line is connected with the grid of the control transistor;

19. The display panel of claim 1, wherein the display portion includes a plurality of rows of first scan signal lines, and the first output module and the second output module are connected to two adjacent rows of the first scan signal lines.

20. A display device comprising a display panel as claimed in any one of claims 1 to 19.