CN118657734B

CN118657734B - Chip surface defect detection method, device and storage medium

Info

Publication number: CN118657734B
Application number: CN202410803237.7A
Authority: CN
Inventors: 王东武; 陆俊材; 李新文
Original assignee: Shenzhen Meisi Micro Vision Technology Co ltd
Current assignee: Shenzhen Meisi Micro Vision Technology Co ltd
Priority date: 2024-06-20
Filing date: 2024-06-20
Publication date: 2025-03-14
Anticipated expiration: 2044-06-20
Also published as: CN118657734A

Abstract

The present application relates to the technical field of chip defect detection, and in particular to a chip surface defect detection method, device and storage medium, the method comprising: obtaining a detection area image including a target chip; matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image; determining multiple detection points on the detection area image according to the binding rectangle; continuously judging whether the first difference between the gray value corresponding to each detection point and the standard gray value is greater than a first difference threshold, and determining the detection point whose first difference is greater than the first difference threshold as an offset point; determining the offset score of each offset point; judging whether the total offset score of the offset points formed by continuous series connection reaches the edge collapse score, and if there is a series connection The total offset score of the offset points reaches the edge collapse score, it is determined that the target chip has edge collapse. The present application can achieve the beneficial effect of improving the efficiency of chip surface defect detection.

Description

Chip surface defect detection method, device and storage medium

Technical Field

The present application relates to the field of chip defect detection technologies, and in particular, to a method and an apparatus for detecting a chip surface defect, and a storage medium.

Background

In the physical processing processes such as cutting, grinding or polishing of the wafer, if the applied external force is too large or uneven, the chip may be broken, the broken chip may damage the circuit of the edge area of the wafer, affect the performance of the whole chip, and even cause the whole chip to fail. Therefore, the detection of chip edge breakage is an indispensable part in the chip production process, and plays an important role in ensuring the precision of semiconductor manufacture, improving the yield of products, preventing pollution, optimizing the production process, maintaining equipment and the like.

The invention patent with publication number CN116109572A discloses a method, a device and an electronic device for detecting weak defects of the edges of a workpiece, which are characterized in that the method, the device and the electronic device are used for detecting the defects of the edges of the workpiece by acquiring image information of the edges of the workpiece to be detected (namely a chip to be detected), extracting the outline, judging the angle information of each outline point in the extracted outline, and determining whether the corresponding position of the workpiece to be detected has the defects according to the angle information.

In the prior art, all outline information of the edge of the chip to be detected needs to be obtained first, then the chip is further subjected to defect detection, and under the normal condition of industrial application, referring to fig. 1, fig. 1 is a view schematic diagram of typical chip surface defect detection, the whole large box is a detection area, each small box is a view of an image acquisition device (camera), each camera view is approximately provided with 10-20 chips to be detected, and the cameras sequentially move to acquire images of multiple camera views and perform chip detection. If all the contour point information is acquired for each chip to be detected, whether the long and thin edge collapse defects exist is judged according to contour point connection, the influence on the detection efficiency of the whole detection flow is difficult to neglect, and based on the influence, how to further optimize the chip surface defect detection method to improve the chip detection efficiency is a technical problem to be solved urgently.

Disclosure of Invention

The application aims to provide a chip surface defect detection method, a chip surface defect detection device and a storage medium, which can realize the beneficial effect of improving the chip surface defect detection efficiency.

The first aspect of the present application provides a method for detecting a chip surface defect, including:

Acquiring a detection area image comprising a target chip;

Matching a binding rectangle of a target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

determining a plurality of detection points on the detection area image according to the binding rectangle;

Continuously detecting the detection points, including judging whether a first difference value between a gray value corresponding to each detection point and a standard gray value is larger than a first difference value threshold, and determining that the detection point with the first difference value larger than the first difference value threshold is an offset point, wherein the standard gray value is a pixel gray value corresponding to each detection point in a binding rectangle of the chip image template;

Determining an offset score value of each offset point, including judging whether the first difference value of each offset point is larger than a second difference value threshold value, and determining an offset score value corresponding to an offset point, of which the first difference value is not larger than the second difference value threshold value, as a first score value, and an offset score value corresponding to an offset point, of which the first difference value is larger than the second difference value threshold value, as a second score value, wherein the first score value is smaller than the second score value;

Judging whether the total offset scores of the serial offset points form continuous serial offset points reach the edge collapse scores or not, if the total offset scores of the serial offset points reach the edge collapse scores, determining that the target chip is subjected to edge collapse, wherein the total offset scores are the sum of offset score values corresponding to all offset points in each serial offset point.

Optionally, the step of matching the binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image includes:

Performing image matching on the detection area image according to the chip image template to obtain binding rectangles corresponding to one or more target chips;

and determining a target chip image of each target chip in the detection area image according to the binding rectangle of each target chip.

Optionally, the step of performing image matching on the detection area image according to the chip image template includes:

Constructing a pyramid image based on the detection area image, wherein the pyramid image comprises taking an original image of the detection area image as a bottom layer of the pyramid image, and obtaining the pyramid image with gradually reduced resolution from the bottom layer to the upper layer through continuous downsampling;

Carrying out normalization calculation on each layer of image of the pyramid image to obtain a normalization index corresponding to each layer of image;

and matching the binding rectangle of each target chip in the detection area image according to the normalization index corresponding to each layer of image.

Optionally, the step of determining a plurality of detection points on the detection area image according to the binding rectangle includes:

And adjusting the rotation angle of each target chip image according to the rotation angle of the chip image template so as to enable the rotation angle of each target chip image to be consistent with the rotation angle of the chip image template.

Optionally, after the step of determining whether the total offset score of the offset points forming the continuous serial offset points reaches the edge collapse score, the method further includes:

If the offset total score does not exist and reaches the serial offset point of the edge collapse score, judging whether a second difference value between each pixel point in the target chip image and the pixel point at the corresponding position in the chip image template is larger than a third difference value threshold value or not;

marking a plurality of pixel points which are in an adjacent relation and the corresponding second difference value of which is larger than the third difference value threshold value as a dead pixel point group;

Judging whether the number of pixel points in the dead pixel point group exceeds a dead pixel point threshold value or not;

And if the pixel points in the dead pixel point group exceed the dead pixel point threshold value, determining that the corresponding area of the pixel point group on the target chip is the dead point.

Optionally, after the step of determining that the corresponding area of the pixel group on the target chip is a dead pixel if the pixel in the dead pixel group exceeds the dead pixel threshold, the method further includes:

According to the number of the pixel points corresponding to the dead pixel, adjusting laser parameters for laser burning at the corresponding position of the dead pixel to obtain a corresponding laser irradiation mode;

And adopting the laser irradiation mode to burn out the corresponding position of the dead pixel.

extracting target features of the chip image template;

And carrying out positioning matching in the detection area image according to the target characteristics so as to determine one or more binding rectangles corresponding to the target chips.

The second aspect of the present application provides a chip surface defect detection device, comprising:

The image acquisition module acquires a detection area image comprising a target chip;

The rectangle matching module is used for matching the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image;

The detection point determining module is used for determining a plurality of detection points on the detection area image according to the binding rectangle;

The offset point judging module is used for continuously detecting the detection points and comprises judging whether a first difference value between a gray value corresponding to each detection point and a standard gray value is larger than a first difference value threshold value or not, and determining that the detection point with the first difference value larger than the first difference value threshold value is an offset point, wherein the standard gray value is a pixel point gray value corresponding to each detection point in a binding rectangle of the chip image template;

The offset score determining module is used for determining an offset score value of each offset point, and comprises judging whether the first difference value of each offset point is larger than a second difference value threshold value or not, determining an offset score value corresponding to an offset point, of which the first difference value is not larger than the second difference value threshold value, as a first score value, and determining an offset score value corresponding to an offset point, of which the first difference value is larger than the second difference value threshold value, as a second score value, wherein the first score value is smaller than the second score value;

And the edge collapse determining module is used for judging whether the total offset scores of the continuous serial offset points formed in the offset points reach the edge collapse score, if the total offset scores of the serial offset points reach the edge collapse score, determining that the edge collapse occurs to the target chip, wherein the total offset scores are the sum of the offset score values corresponding to all the offset points in each serial offset point.

Optionally, the rectangular matching module further includes:

The image matching sub-module is used for carrying out image matching on the detection area image according to the chip image template so as to obtain binding rectangles corresponding to one or more target chips;

an image extraction sub-module for determining a target chip image of each target chip in the detection area image according to the binding rectangle of each target chip

The image matching sub-module further includes:

The pyramid construction unit is used for constructing pyramid images based on the detection area images, and comprises the steps of taking original images of the detection area images as bottom layers of the pyramid images, and obtaining the pyramid images with resolution gradually reduced from bottom layers to top layers through continuous downsampling;

the normalization unit is used for carrying out normalization calculation on each layer of image of the pyramid image so as to obtain a normalization index corresponding to each layer of image;

And the rectangle matching unit is used for matching the binding rectangle of each target chip in the detection area image according to the normalization index corresponding to each layer of image.

A third aspect of the present application provides a storage medium storing a computer program capable of being loaded by a processor and executing a chip surface defect detection method as described above.

In summary, the beneficial effects of the application are as follows:

The image of the detection area including the target chip is obtained, and the binding rectangle of the standard chip image template used as the detection standard, that is, the standard binding rectangle, may be obtained by using an image matching algorithm (in this embodiment, the image matching algorithm adopted is pyramid gray value matching) to frame the image corresponding to one or more target chips in the detection area image, and obtaining the binding rectangle corresponding to the target chip image, and setting a plurality of detection points in the detection area image according to the binding rectangle and the standard rectangle of the target chip image.

And then continuously detecting a plurality of detection points to determine whether each detection point is an offset point or not, and further determining an offset score corresponding to each offset point according to the offset degree of each offset point (i.e. judging whether the first difference value of the offset point is greater than a second difference value threshold value). In the process of forming the continuous serial offset points, once the sum of the corresponding translation score values reaches the preset edge breakage score value, the edge breakage of the target chip is determined, and gray information corresponding to all detection points on the target chip is not required to be acquired, so that the chip detection efficiency of single edge breakage is improved, and the efficiency of batch detection of chips is further improved.

Drawings

FIG. 1 is a schematic view of a typical chip surface defect detection;

FIG. 2 is a schematic flow chart of a method for detecting surface defects of a chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating the execution of step S1 in the method for detecting a chip surface defect according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a chip surface defect detection process according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of edge analysis according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of dead pixel processing according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating the execution of step S2 in the method for detecting a chip surface defect according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating the execution of step S3 in the method for detecting a chip surface defect according to an embodiment of the present application;

FIG. 9 is a flowchart illustrating steps included in step S4 in the method for detecting a chip surface defect according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating the execution of step S4 in the method for detecting a chip surface defect according to the embodiment of the present application;

FIG. 11 is a flowchart illustrating steps included in step S5 in the method for detecting a chip surface defect according to the embodiment of the present application;

FIG. 12 is a schematic diagram illustrating the execution of step S6 in the method for detecting surface defects of a chip according to an embodiment of the present application;

Fig. 13 is a schematic diagram of a virtual structure of a chip surface defect detecting device according to an embodiment of the present application.

Detailed Description

The following examples will assist those skilled in the art in further understanding the function of the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In order to make the objects, technical solutions and advantages of the present application more clear, the method for detecting a chip surface defect according to the present application is described below from the perspective of a chip surface defect detecting device, where the chip surface defect detecting device may be an electronic device, and the electronic device may be a device such as a mobile phone terminal, a computer terminal, or the like.

The present application will be described in further detail with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a flowchart of a method for detecting a chip surface defect according to an embodiment of the present application, where the method includes the following steps:

s1, acquiring a detection area image comprising a target chip;

s2, matching a binding rectangle of a target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

s3, determining a plurality of detection points on the detection area image according to the binding rectangle;

S4, continuously detecting the detection points, wherein the detection points comprise judging whether a first difference value between a gray value corresponding to each detection point and a standard gray value is larger than a first difference value threshold value, and determining that the detection point with the first difference value larger than the first difference value threshold value is an offset point, wherein the standard gray value is a pixel gray value corresponding to each detection point in a binding rectangle of the chip image template;

S5, determining the offset score value of each offset point, wherein the offset score value comprises judging whether the first difference value of each offset point is larger than a second difference value threshold value or not, and determining the offset score value corresponding to the offset point with the first difference value not larger than the second difference value threshold value as a first score value, and the offset score value corresponding to the offset point with the first difference value larger than the second difference value threshold value as a second score value, wherein the first score value is smaller than the second score value;

And S6, judging whether the total offset scores of the continuous serial offset points formed in the offset points reach the edge collapse score, if the total offset scores of the serial offset points reach the edge collapse score, determining that the target chip is subjected to edge collapse, wherein the total offset scores are the sum of the offset score values corresponding to all the offset points in each serial offset point.

The following is a specific explanation of each step:

in step S1, a detection area image including a target chip is acquired.

Specifically, referring to fig. 3, fig. 3 is a schematic diagram illustrating the execution of step S1 in the method for detecting a chip surface defect according to the embodiment of the present application, an image of a detection area is acquired by a related image acquisition device, and an image in a field of view may be acquired by a related image acquisition device (hereinafter referred to as a camera), and an outer frame is an overall image of the detection area, including a plurality of camera fields (refer to small boxes in the drawing), where each camera field may be provided with a plurality of chips to be detected, typically, 10-20 chips are provided in each camera field, and in this embodiment, the cameras are sequentially moved according to a preset detection sequence to detect each camera field one by one.

More specifically, before acquiring the detection area image including the target chip, the apparatus may be corrected to avoid a deviation in the acquired result. The method mainly comprises the steps of hardware calibration, namely calibrating an x axis and a y axis of an image position and an axis relation, wherein a three-point calibration method can be used in a z axis of a height relation, the three-point calibration method is a method for ensuring that the distance between equipment and the surface of a wafer is correct and the precision is accurate when the equipment is scanned, and the optimal image acquisition effect and analysis precision are obtained by adjusting the distance between the equipment and the surface of the wafer, so that the equipment is ensured to keep proper focusing and imaging quality in the whole scanning process, and image blurring or distortion caused by height difference is avoided. In the calibration process, the plane of the platform is considered to be in a flat state, but the height of the platform is different at different positions due to the installation difference of equipment, so that matching adjustment is required.

More specifically, as an example, the method provided by the application may be applied to an upper computer, the related detection flow may refer to fig. 4, fig. 4 is a schematic diagram of a chip surface defect detection flow provided by the embodiment of the application, before starting, the upper computer enters a standby state after being powered on and initialized, in the standby state, a related person may control to enter the detection flow, first control a target chip to be detected to move to align with a related device, and then perform image capturing by using an image capturing device such as a camera to obtain a detection area image including one or more target chips, and perform edge analysis and/or dead pixel area analysis according to the detection area image obtained by capturing the image by using the camera.

On the one hand, the edge analysis is used for analyzing whether the defects of weak edge breakage angle, weak burr and the like exist at the edge of the chip, and judging whether the detected target chip breaks edges or not based on the obtained defect image, namely, broken edge detection, wherein the implementation flow of broken edge detection in one embodiment of the application can refer to fig. 5, and fig. 5 is a schematic flow chart of the edge analysis provided by the embodiment of the application. After the image of the detection area is acquired by the related image acquisition device (camera in this embodiment), first, the coordinates of the binding rectangle corresponding to the target chip in the acquired image are determined, then an inspection line is generated according to the coordinates, and whether a continuously offset portion exists is determined according to the inspection line, so as to determine whether to break edges, and after the determination is completed, edge detection of the target chip is finished, and for a specific determination manner of the break edges, the following steps can be referred to.

On the other hand, the dead pixel area analysis is performed according to the obtained target chip image, and referring to fig. 6, fig. 6 is a schematic flow chart of the dead pixel processing provided in the embodiment of the present application, wherein the dead pixel is marked according to the position of each pixel in the obtained target chip image by the following dead pixel analysis method, and then the corresponding laser is controlled to move to the marked dead pixel for laser burning. In addition, whether dead pixels are burned or not is determined through image judgment to determine whether all dead pixels are processed or not, if so, dead pixel processing flow is finished, otherwise, the laser is controlled to move to the next dead pixel to burn out the laser until all dead pixel processing is finished.

In step S2, a binding rectangle of the target chip is matched in the detection area image according to a chip image template corresponding to the target chip in the detection area image.

Specifically, referring to fig. 7, fig. 7 is a schematic diagram illustrating execution of step S2 in a method for detecting a chip surface defect according to an embodiment of the present application, including an exemplary chip image template, a field of view for any one camera in a detection area, and binding rectangles corresponding to a plurality of target chips outlined by dashed lines in the detection area according to the chip image template. The chip image template is a standard chip image which accords with the relevant standard, namely a normal chip. In this embodiment, one or more target chips are matched in the detection area image according to the image of the normal chip, and information of the target chips in the detection area image is recorded with a bound rectangle.

The binding rectangle is not an actually existing rectangle, and is used for recording image information of the target chip in the detection area image, and at least records pixel value and coordinates of each pixel of the target chip in the detection area image and edge pixels of the target chip. I.e. the binding rectangle records not only the pixel value and coordinates of each pixel, but also which pixels belong to the edge of the target chip. For example, if the shape of the target chip is rectangular, the binding rectangle records not only the pixel values and coordinates of all pixels of the target chip in the first image, but also the edges of the target chip, i.e., the pixels corresponding to the four sides of the rectangle.

In this embodiment, according to the template image, the image matching algorithm is used to frame the images corresponding to one or more target chips in the detection area image, so as to obtain the following binding rectangle, and then the detection area image may be extracted according to the obtained binding rectangle to obtain the image of each target chip, i.e. one or more target chip images, where the information such as the position, the edge pixel, etc. of each target chip in the detection area image is recorded, so as to facilitate image extraction. The edge of the target chip image corresponds to the edge of the target chip, and the edge pixel point of the target chip image is taken as a detection point, which is taken as an example and not as a limitation, the detection area image can be cut according to the binding rectangle to obtain the target chip image, and the round of pixel points at the edge of the target chip image is taken as the detection point, namely:

Specifically, in this embodiment, the image matching algorithm adopted is pyramid gray value matching, which is an image processing technology and is mainly used in the fields of image matching and data fusion. The core idea is to represent and process the image at different resolution levels (i.e. different levels of the pyramid). The application of pyramid gray value matching in the present application is specifically described below:

Specifically, a gaussian pyramid is first constructed, and the gaussian pyramid is a set of image sequences obtained by subjecting an original image to continuous gaussian blurring and downsampling. Each layer of image is obtained by sampling after Gaussian blur is carried out on the next layer of image, so that the image size of each layer is the same, but the resolution is gradually reduced. In this embodiment, an image acquisition related device (such as a camera) is used as the bottom layer of the pyramid, and a series of images with gradually reduced resolution are generated through continuous downsampling operation, so as to form the upper layer of the pyramid. And calculating a normalization index for each layer of the constructed Gaussian pyramid, wherein the normalization index can be an NCC (Normalized Cross-Correlation) value, and the NCC is a statistical index for measuring the similarity between two images, and the closer the value is to 1, the better the matching is indicated. And determining the position information of the optimal matching point according to the NCC value obtained by each layer, wherein the position information is used for guiding the matching of the corresponding position point of each point in each target chip in the image in the original detection area image, and finally drawing binding rectangles of each target chip in the detection area image based on the matched result, wherein the binding rectangles frame the positions of the target chips, and the image of each target chip can be extracted according to the position information.

More specifically, after the detection area image in the field of view is acquired by the related image acquisition device, there may be a case where the angle of the target chip is inconsistent with the angle of the template chip in the template image, and in order to ensure the accuracy of the detection point, a step of adjusting the image angle is also required, which will be described in detail below:

Specifically, in the process of extracting the target chip image from the detection area image, there may be a case that the angle of the target chip is inconsistent with the angle of the template chip in the template image, as shown in fig. 2, the rotation angles corresponding to the actual placement modes of the plurality of target chips may be different, which may result in that the angle of the extracted target chip image is inconsistent with the angle of the template of the chip image, and if the processing is not performed, the positions of the target chip and the template chip may not be corresponding. For example, the coordinate system is established by taking the left lower corner of the target chip image and the left lower corner of the template chip image as the origin, and the same coordinates are adopted, and the point in the corresponding template image is the vertex at the left upper corner of the template chip, but the point in the corresponding target chip image may be the midpoint on the left side of the target chip.

Therefore, in this embodiment, the binding rectangle also records the rotation angle of the target chip, that is, the rotation angle of the target chip relative to the template chip, and rotates the target chip image according to the rotation angle of the binding rectangle until the rotation angle is consistent with the template image angle, after the angle is consistent, the same coordinates in the target chip image and the template chip image correspond to the same positions of the target chip and the template chip, for example, the origin (0, 0) in the target chip image and the template chip image both correspond to the vertices of the lower left corners of the target chip and the template chip.

In one embodiment of the present application, feature extraction may be used to remove other images unrelated to one or more target chips for which surface defect detection is required, and the feature extraction is specifically described below:

extracting target features of the chip image template;

And according to the target characteristics, positioning and matching are carried out in the detection area image so as to determine the binding rectangle corresponding to each target chip in the chip image template.

Specifically, the target features of the chip image template are extracted first, and the binding rectangle corresponding to each target chip is determined in the detection area image based on the target features of the chip image template. For example, a convolutional neural network model can be built, target features of the chip image templates are extracted to train the convolutional neural network model, a trained convolutional neural network model is obtained, and finally, the detection area images are input into the trained convolutional neural network model, and the binding rectangle corresponding to each target chip is obtained.

In step S3, a plurality of detection points are determined on the detection area image according to the binding rectangle.

Specifically, for each matched target chip, a plurality of detection points are determined on the detection area image according to the binding rectangle, the detection points are pixel points of the edge of the target chip in the detection area image, please refer to fig. 8, fig. 8 is an execution schematic diagram of step S3 in the chip surface defect detection method provided in the embodiment of the present application, detection points are set on the chip image template, and then according to the detection points set on the chip image template, the binding rectangle edge corresponding to each frame is correspondingly matched, which is understood to be only an example and not to represent the actual distribution mode of the detection points. The position of the target chip and the edge of the target chip can be determined in the detection area image according to the binding rectangle, after the edge of the target chip is determined, the detection points can be determined according to a preset selection rule, for example, all pixel points of the edge of the target chip in the detection area image can be used as detection points, and part of pixel points of the edge of the target chip in the detection area image can also be used as detection points, and it is understood that the more the detection points of the edge of the target chip are, the higher the detection accuracy is, but the detection speed is reduced, so that the selection rule of the detection points can be determined according to specific conditions, and the application is not limited to this.

In step S4, the detection points are continuously detected.

Specifically, referring to fig. 9, fig. 9 is a flowchart illustrating steps included in step S4 in the method for detecting a chip surface defect according to an embodiment of the present application, wherein whether the detection point is abnormal or not is determined by comparing a gray value of the detection point with a standard gray value, that is, comparing differences between edges of a target chip and a template chip on an image, so as to determine whether the edges of the target chip are abnormal, and specifically includes the following steps:

in step S41, determining whether a first difference value between a gray value corresponding to each detection point and a standard gray value is greater than a first difference threshold, where the standard gray value is a pixel gray value corresponding to each detection point in a binding rectangle of the chip image template;

in step S42, it is determined that the detection point where the first difference is greater than the first difference threshold is an offset point.

More specifically, referring to fig. 10, fig. 10 is a schematic diagram illustrating execution of step S4 in the method for detecting a chip surface defect according to the embodiment of the present application, including two sets of consecutive detection points including a serial connection point 1 and a serial connection point 2, wherein a black point is an offset point with a first difference value greater than a preset first difference threshold, and a white point is a non-offset point, i.e. a normal pixel point. In the application, the detection point corresponding to the target chip image is based on a preset detection sequence, the detection sequence can be adjusted according to the actual demands of related personnel, and also can be preset in related equipment, for example, one detection point is positioned at the top left corner of the target chip, and then the standard gray value corresponding to the detection point is the gray value of the top left corner of the template chip in the template image. If the first difference is greater than the first difference threshold, determining the detection point as an offset point, that is, determining that the detection point has an abnormality, and determining the detection point as an offset point, wherein the first difference may be obtained by subtracting a standard gray value from a gray value of the detection point and then taking an absolute value. The first difference threshold is a preset value, and can be determined according to practical situations, which is not limited by the present application.

In step S5, determining an offset score value of each offset point includes determining whether the first difference value of each offset point is greater than a second difference threshold, and determining that an offset score value corresponding to an offset point where the first difference value is not greater than the second difference threshold is a first score value, and that an offset score value corresponding to an offset point where the first difference value is greater than the second difference threshold is a second score value, where the first score value is less than the second score value.

Referring to fig. 11, fig. 11 is a flowchart illustrating steps included in step S5 in the method for detecting a chip surface defect according to an embodiment of the present application, and the step S5 specifically includes the following steps:

In step S51, determining whether the first difference value of each offset point is greater than a second difference threshold;

In step S521, determining an offset score corresponding to an offset point where the first difference is not greater than the second difference threshold as a first score;

in step S522, it is determined that the offset score corresponding to the offset point where the first difference is greater than the second difference threshold is a second score, where the first score is less than the second score.

Specifically, after each detection point is determined as an offset point, the offset degree of the offset point is further determined, a second difference threshold is preset in this embodiment, and the second difference threshold is used as a boundary, if the first difference value of the offset point is smaller than or equal to the second difference threshold, the offset degree of the offset point is determined to be lighter, and if the first difference value of the offset point is greater than the second difference threshold, the offset degree of the offset point is determined to be heavier, wherein the second difference threshold should be greater than the first difference threshold. It should be noted that if the first difference value of the single detection point exceeds the second difference threshold (for example, by more than two times), the offset score value corresponding to the offset point may be increased appropriately according to the actual situation.

In step S6, it is determined whether the total offset score of the consecutive serial offset points formed in the offset points reaches the edge collapse score, if the total offset score of the serial offset points reaches the edge collapse score, the edge collapse of the target chip is determined, and the total offset score is the sum of the offset score values corresponding to all the offset points in each serial offset point.

Specifically, for each target chip, after determining a plurality of detection points on the binding rectangle of the target chip, one detection point is used as a starting point to detect one by one, and if the continuous detection point is an offset point, the series offset point is formed.

More specifically, when forming the serial offset points, calculating the total offset value according to the offset score value corresponding to each offset point on the serial offset points is started, for example, as shown in fig. 12, fig. 12 is a schematic diagram illustrating execution of step S6 in the chip surface defect detection method according to the embodiment of the present application. For convenience of description, the offset points corresponding to the first score values are represented in gray, the offset points corresponding to the second score values are represented in black, and it is assumed that the serial offset point 1 is composed of 3 offset points of the first score values, the serial offset point 2 is composed of 2 offset points of the second score values, the serial offset point 3 is composed of 2 offset points of the first score values and 1 offset point of the second score values, the preset edge breakage score is 4, the first score value is 1, and the second score value is 2. In this case, the total offset score of the serial offset point 1 is 3, the total offset score of the serial offset point 2 is 4, and the total offset score of the serial offset point 3 is 4, i.e. the target chip 2 and the target chip 3 are broken. After determining that the corresponding target chip breaks edges, stopping detection of subsequent detection points and detection of dead points, and marking by laser irradiation so as to facilitate subsequent related personnel to pick out the broken edge chips.

In one embodiment of the present application, a counter may be set, and a certain detection point is taken as a starting point, and all detection points are traversed from the starting point in turn, where if the detection point is an offset point and the corresponding offset score value is 1, the counter is incremented by 1, and if the next detection point is also an offset point corresponding to the first offset score value, the counter is incremented by 1, and if an offset point corresponding to the second offset score value occurs, the counter is incremented by 2, and accumulation is gradually performed. It is noted that if the next detection point is not the offset point, the count value of the counter, that is, the offset total score is obtained, if the offset total score reaches the edge breakage score, the chip is determined to send the edge breakage and the detection is finished, if the offset total score does not reach the edge breakage score, the next detection point is continuously detected and the technical value of the counter is cleared until all detection points on the target chip image are detected.

Further, for the chip (e.g., the target chip 1 shown in fig. 10) that is not edge-broken after edge analysis and detection, the dead pixel area analysis may be further performed on the target chip, and the following specific description is performed:

Specifically, comparing the overall difference of the target chip image and the chip image template, namely comparing the whole target chip image with the whole template chip image, and judging whether the target chip has dead pixels or not based on a comparison result.

Firstly, judging whether a second difference value between each pixel point in the target chip image and a pixel point at a corresponding position in the chip image template is larger than a third difference value threshold, for example, subtracting the gray value of the pixel point at the corresponding position in the chip image template from the gray value of each pixel point in the target chip image, taking an absolute value of the difference value, obtaining the second difference value, and judging whether the second difference value is larger than the third difference value threshold.

And then, marking a plurality of pixel points which are in adjacent relation and have difference values larger than a third difference value threshold value in the target chip image as a dead pixel point group.

And finally, determining the area on the target chip corresponding to the dead pixel group as the dead pixel if the number of the pixels in the dead pixel group is larger than the dead pixel threshold value.

It can be understood that the bad pixels of the chip are shown as one or more groups of adjacent pixels in the image, so in this embodiment, it is first determined whether the second difference value corresponding to each pixel in the image of the target chip is greater than a third difference value threshold, if so, the pixel is considered to be abnormal, the adjacent abnormal pixels are marked as bad pixels, and if so, a small number of pixels are not representative of the bad pixels on the chip, possibly because of detection errors, image equipment and other reasons, the small number of pixels are abnormal, so the application also determines the number of the middle pixels of the bad pixels, and if the number is greater than the bad pixels threshold, the area on the target chip corresponding to the bad pixels is determined as bad. The third difference value threshold and the dead pixel threshold may be determined according to actual situations, which is not limited in the present application.

Further, after determining the dead pixels, an image area corresponding to the dead pixels may be determined on the image, so as to control the related laser to burn out one or more dead pixels, and this step is specifically described below:

Specifically, the larger the number of pixels in the dead pixel group is, the larger the corresponding dead pixel area is, and the higher preset laser power, the longer preset irradiation time and the larger preset light spot can be used; the fewer the number of pixels in the dead pixel group, the smaller the dead pixel area corresponding to the dead pixel group, and the lower preset laser power, the shorter preset irradiation time and the smaller preset light spot can be used.

More specifically, under the condition of larger dead spot area, laser with larger light spot can be adopted for pulse, but the mode is not applicable under the condition of smaller spacing of target chips, and the high temperature of the laser is likely to damage peripheral ICs, so that the power, pulse time and light spot size of the laser can be adjusted according to the spacing of the target chips so as to adapt to the dead spot pulse requirements of products with different specifications, the adjustment of the laser can be preset into a laser irradiation mode, and each laser irradiation module can be correspondingly provided with different laser power, irradiation time and light spot size in actual use.

In a second aspect of the present application, referring to fig. 13, fig. 13 is a schematic view of a virtual structure of a chip surface defect detecting device according to the present application, where the chip surface defect detecting device includes:

an image acquisition module 100 that acquires a detection area image including a target chip;

the rectangle matching module 200 matches the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image;

a detection point determining module 300 for determining a plurality of detection points on the detection area image according to the binding rectangle;

The offset point judging module 400 is configured to continuously detect the detection points, and includes judging whether a first difference value between a gray value corresponding to each detection point and a standard gray value is greater than a first difference threshold, and determining that a detection point where the first difference value is greater than the first difference threshold is an offset point, where the standard gray value is a gray value of a pixel point corresponding to each detection point in a binding rectangle of the chip image template;

an offset score determining module 500, configured to determine an offset score value of each offset point, including determining whether the first difference value of each offset point is greater than a second difference threshold, and determining an offset score value corresponding to an offset point where the first difference value is not greater than the second difference threshold as a first score value, and an offset score value corresponding to an offset point where the first difference value is greater than the second difference threshold as a second score value, where the first score value is less than the second score value;

The edge collapse determining module 600 determines whether the total offset score of the consecutive serial offset points reaches an edge collapse score, if the total offset score of the serial offset points reaches the edge collapse score, determining that the edge collapse occurs to the target chip, where the total offset score is the sum of the offset score values corresponding to all the offset points in each serial offset point.

Further, the rectangular matching module 200 further includes:

The image matching sub-module further includes:

For specific limitations of the chip surface defect detection device, reference may be made to the above limitations of the chip surface defect detection method, and no further description is given here. The above-described respective modules in the chip surface defect detecting device may be implemented in whole or in part by software, hardware, and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above device may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

The method for detecting the surface defects of the chip provided by the embodiment of the application can be applied to terminal equipment such as electronic equipment, computers, wearable equipment, vehicle-mounted equipment, tablet computers, notebook computers, netbooks, personal Digital Assistants (PDAs), augmented reality (augmented reality, AR)/Virtual Reality (VR) equipment, mobile phones and the like.

Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements steps of the various embodiments of the methods described above.

Embodiments of the present application provide a computer program product which, when run on a mobile terminal, causes the mobile terminal to perform steps that enable the various embodiments of the method described above to be carried out.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above-described embodiments, and may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium can include at least any entity or device capable of carrying computer program code to a camera device/terminal equipment, a recording medium, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of modules or elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The foregoing embodiments are merely for illustrating the technical solution of the present application, but not for limiting the same, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solution described in the foregoing embodiments may be modified or substituted for some of the technical features thereof, and that these modifications or substitutions should not depart from the spirit and scope of the technical solution of the embodiments of the present application and should be included in the protection scope of the present application.

Claims

1. The chip surface defect detection method is characterized by comprising the following steps of:

s1, acquiring a detection area image comprising a target chip;

s2, matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

S5, determining an offset score value of each offset point, wherein the offset score value comprises judging whether the first difference value of each offset point is larger than a second difference value threshold value, determining an offset score value corresponding to an offset point, of which the first difference value is not larger than the second difference value threshold value, as a first score value, and determining an offset score value corresponding to an offset point, of which the first difference value is larger than the second difference value threshold value, as a second score value, wherein the first score value is smaller than the second score value;

S6, judging whether the total offset scores of the serial offset points forming the continuity in the offset points reach the edge collapse score, if the total offset scores of the serial offset points reach the edge collapse score, determining that the target chip is subjected to edge collapse, wherein the total offset scores are the sum of offset score values corresponding to all offset points in each serial offset point;

After the step S6 of determining whether the total offset score of the consecutive serial offset points formed in the offset points reaches the edge collapse score, the chip which is confirmed to have no edge collapse after edge analysis and detection is further subjected to dead pixel area analysis and corresponding processing, including:

2. The method according to claim 1, wherein the step S2 of matching the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image comprises:

3. The method of claim 2, wherein the step of image matching the inspection area image according to the chip image template comprises:

4. The method of claim 2, wherein the step S3 of determining a plurality of detection points on the detection area image according to the binding rectangle includes:

5. The method for detecting a chip surface defect according to claim 1, wherein after the step of determining that the corresponding area of the pixel group on the target chip is a defective pixel if the pixel in the defective pixel group exceeds the defective pixel threshold, further comprises:

6. The method according to claim 1, wherein the step S2 of matching the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image comprises:

extracting target features of the chip image template;

7. A chip surface defect inspection apparatus for performing a chip surface defect inspection method as set forth in claim 1, comprising:

8. The chip surface defect detection apparatus of claim 7, wherein the rectangular matching module further comprises:

The image matching sub-module further includes:

9. A storage medium storing a computer program capable of being loaded by a processor and executing a method of chip surface defect detection according to any one of claims 1-6.