CN118645522A - Trench gate IGBT device and preparation method thereof - Google Patents

Abstract

The present invention discloses a trench gate IGBT device and a preparation method thereof, wherein the IGBT device is filled with polysilicon and a gate oxide layer located outside the polysilicon and close to the inner wall of the trench in the trench, a filling groove is provided on one or both sides of the polysilicon, the filling groove extends from the top of the polysilicon to the bottom of the polysilicon, a filling cavity is formed between the filling groove and the inner wall of the gate oxide layer, the filling cavity is filled with an insulating medium, and active areas abutting against the outer wall of the gate oxide layer are provided on both sides of the top of the trench. According to the trench gate IGBT device and the preparation method thereof of the present invention, by filling the trench with an insulating medium, the region where the insulating medium in the trench overlaps with the active area will not form an electron flow channel, thereby reducing the short-circuit current and improving the short-circuit capability of the device. By extending the insulating medium along the trench depth direction to the bottom of the polysilicon, the gate capacitance is effectively reduced and the switching speed of the device is improved.

Description

Trench gate IGBT device and preparation method thereof

Technical Field

The present invention belongs to the technical field of IGBT devices, and in particular relates to a trench gate IGBT device and a preparation method thereof.

Background Art

In the prior art, in order to pursue lower saturation voltage drop and switching loss, the number of trenches in the trench gate IGBT is increased, resulting in an increase in the corresponding channel density, which improves the current carrying capacity per unit area, thereby increasing the saturation current density of the device. Since the trench gate structure can eliminate the JFET resistance component when the planar gate IGBT is turned on, the on-state voltage drop of the IGBT will be further reduced as the trench density increases, which helps to reduce power loss and improve system efficiency. Through refined trench design, the Miller capacitance of the chip can be reduced, thereby reducing switching losses. This helps to increase the switching speed of the IGBT, making it more advantageous in high-frequency applications.

But at the same time, although the increase in trench density can increase the current density, it also increases the current of the IGBT during short circuit and reduces the short circuit resistance of the device.

Summary of the invention

The object of the present invention is to provide a trench gate IGBT device and a preparation method thereof, which can solve the problem that the short circuit resistance capability of the IGBT device decreases as the trench density increases.

In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides a trench gate IGBT device, including a substrate and a first conductive type drift region and a second conductive type body region sequentially formed on the substrate, the trench gate IGBT device also includes a first trench and a second trench penetrating the second conductive type body region and extending into the first conductive type drift region, the first trench is filled with a first polysilicon and a first gate oxide layer located outside the first polysilicon and close to the inner wall of the first trench, a filling groove is opened on one side or both sides of the first polysilicon, the filling groove extends from the top of the first polysilicon to the bottom of the first polysilicon, a filling cavity is formed between the filling groove and the inner wall of the first gate oxide layer, the filling cavity is filled with an insulating medium, and first conductive type source regions in contact with the outer wall of the first gate oxide layer are arranged on both sides of the top of the first trench, and the second trench is filled with a second polysilicon and a second gate oxide layer located outside the second polysilicon and close to the inner wall of the second trench.

In one or more embodiments of the present invention, the insulating medium includes silicon dioxide or silicon nitride.

In one or more embodiments of the present invention, a plurality of insulating media are provided along the length direction of the first trench.

In one or more embodiments of the present invention, two first trenches are provided, a plurality of filling trenches are arranged side by side on one side of the first polysilicon, and the filling trenches are located on a side close to another first trench.

In one or more embodiments of the present invention, the width of the insulating medium is smaller than the width of the first polysilicon.

In one or more embodiments of the present invention, the trench gate IGBT device further includes a carrier storage layer disposed between the first conductivity type drift region and the second conductivity type body region.

In one or more embodiments of the present invention, an insulating layer covering the second conductive type body region, the first conductive type source region, the first trench and the second trench is disposed on the second conductive type body region, a metal contact hole penetrating the insulating layer is opened on the insulating layer, a metal lead is disposed in the metal contact hole, the insulating layer is covered with a metal layer, the first conductive type source region and the second conductive type body region are in ohmic contact with the metal lead, and the metal lead is in ohmic contact with the metal layer.

A specific embodiment of the present invention also provides a method for preparing a trench gate IGBT device, comprising: step 1, providing a semiconductor substrate, wherein the semiconductor substrate is formed with a first conductive type drift region; step 2, forming a carrier storage layer above the first conductive type drift region by using a high energy injection technique; step 3, forming a first trench and a second trench on the substrate by etching; step 4, depositing a first gate oxide layer and a second gate oxide layer in the first trench and the second trench, respectively, and filling the first polysilicon and the second polysilicon; step 5, etching the polysilicon in the first trench, A filling groove is formed, and an insulating medium is filled in the filling cavity formed by the filling groove and the first gate oxide layer; step 6, second conductive type ions are injected into the substrate above the carrier storage layer and a well is pushed to form a second conductive type body region; step 7, first conductive type ions are injected into the second conductive type body region to form a first conductive type source region; step 8, an insulating layer is deposited above the second conductive type body region, and the insulating layer is etched to obtain a metal contact hole; step 9, metal is deposited in the metal contact hole to obtain a metal lead, and metal is deposited on the insulating layer to obtain a metal layer.

Compared with the prior art, the trench gate IGBT device and preparation method of the present invention fills the first trench with an insulating medium so that the region where the insulating medium in the trench overlaps with the source region of the first conductive type does not form an electron flow channel, thereby reducing the short-circuit current and improving the short-circuit capability of the device. By extending the insulating medium along the trench depth direction to the bottom of the first polysilicon, the gate capacitance is effectively reduced and the switching speed of the device is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a top view of a trench gate IGBT device in Embodiment 1 of the present invention.

FIG2 is a cross-sectional view taken along the line A-A of the trench gate IGBT device in Embodiment 1 of the present invention.

FIG3 is a top view of a trench gate IGBT device in Embodiment 2 of the present invention.

FIG4 is a cross-sectional view taken along the line A-A of the trench gate IGBT device in Embodiment 2 of the present invention.

5A to 5E are device structure diagrams in various steps of a method for preparing a trench gate IGBT device in one embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

Example 1

As shown in Figures 1 and 2, the trench gate IGBT device in one embodiment of the present invention includes a substrate and a first conductive type drift region 10, a carrier storage layer 20 and a second conductive type body region 30 formed in sequence on the substrate, and a first trench 51 and a second trench 52 that penetrate the second conductive type body region 30, the carrier storage layer 20 and extend into the first conductive type drift region 10.

Two first grooves 51 are provided, and two second grooves 52 are provided. The two first grooves 51 are parallel to each other, and the two first grooves 51 are located between the two second grooves 52 .

Each first trench 51 is filled with a first polysilicon 62 and a first gate oxide layer 61 located outside the first polysilicon 62 and close to the inner wall of the first trench 51. A filling groove is provided on one side of the first polysilicon 62, and the filling groove extends from the top of the first polysilicon 62 to the bottom of the first polysilicon 62. A filling cavity is formed between the filling groove and the inner wall of the first gate oxide layer 61, and the filling cavity is filled with an insulating medium 63. The first conductive type source region 40 abutting against the outer wall of the first gate oxide layer 61 is provided on both sides of the top of each first trench 51, and the first conductive type source region 40 is located in the second conductive type body region 30.

There are multiple filling grooves in each first groove 51 along the length direction of the first groove, that is, there are multiple insulating media along the length direction of the first groove, and the insulating media 63 in the two first grooves 51 are symmetrically arranged and evenly distributed along the length direction of the first groove 51.

Preferably, the filling grooves in the two first trenches 51 are both opened on the side of the first polysilicon 62 close to the other first trench 51, that is, the distance between the two corresponding insulating dielectrics 63 in the two first trenches 51 is the shortest. The width of the insulating dielectric 63 in each first trench 51 is smaller than the width of the first polysilicon 62.

In one embodiment, the insulating medium 63 includes silicon dioxide or silicon nitride. In other embodiments, the insulating medium 63 may also be made of other materials that can be insulated from the first polysilicon 62 .

The entire device is arranged in an axisymmetric manner, and the insulating medium 63 of the two first grooves 51 is located on both sides of the first conductive type source region 40 in the center of the device to form an overlapping area, so that the short-circuit current generated in the central area is minimized, and the short-circuit capacity of the device is improved to the greatest extent, with higher reliability and thermal stability. At the same time, since the insulating medium 63 is only provided on one side of the first groove 51, the manufacturing process of the device is relatively simple, and it is easy to achieve refined control, effectively controlling the manufacturing cost, and achieving a balance between obtaining good device performance and simplifying the production process and reducing costs.

As shown in FIG. 2 and FIG. 1 , each second trench 52 is filled with a second polysilicon 65 and a second gate oxide layer 64 located outside the second polysilicon 65 and closely attached to the inner wall of the second trench 52 .

In one embodiment, the first trench 51 is used to form a real gate, and the second trench 52 is used to form a virtual gate. By filling the insulating medium 63 in the real gate formed by the first trench 51, the region where the insulating medium 63 overlaps with the first conductive type source region 40 will not form an electron flow channel, thereby reducing the short-circuit current and improving the short-circuit capability of the IGBT device. By extending the insulating medium 63 along the trench depth direction to the bottom of the first polysilicon 62, the thickness of the insulating layer in the trench is increased, which can effectively reduce the gate capacitance and improve the switching speed of the device.

The setting of the virtual gate helps to reduce the charge storage effect during the switching process, thereby speeding up the switching speed, reducing switching losses, improving the conduction characteristics and improving thermal stability, and improving the overall efficiency of the device.

By adding the carrier storage layer 20, the second conductivity type carriers are prevented from entering the second conductivity type body region 30, so as to increase the concentration of the second conductivity type carriers at the top of the second conductivity type body region 30, thereby achieving an increase in current density and a decrease in power loss, and making the carrier distribution in the IGBT device closer to the optimal state.

As shown in FIG2 and FIG1 , an insulating layer 70 covering the second conductive type body region 30, the first conductive type source region 40, the first trench 51 and the second trench 52 is provided on the second conductive type body region 30, a metal contact hole penetrating the insulating layer 70 is provided on the insulating layer 70, a metal lead 81 is provided in the metal contact hole, a metal layer 82 is covered on the insulating layer 70, the first conductive type source region 40 and the second conductive type body region 30 are in ohmic contact with the metal lead 81, and the metal lead 81 is in ohmic contact with the metal layer 82. The metal layer 82 is used to form an emitter.

In a specific implementation, a second conductive type collector region and a collector electrode are further provided on the back side of the substrate. The specific forms of the second conductive type collector region and the collector electrode can be selected as required and only need to meet the function of the IGBT device.

It should be noted that IGBT devices include N-type power semiconductor devices and P-type power semiconductor devices. In the present application text, for N-type power semiconductor devices, the first conductivity type is N-type and the second conductivity type is P-type. For P-type semiconductor devices, the first conductivity type is P-type and the second conductivity type is N-type.

Example 2

As shown in FIG3 , compared with Embodiment 1, the trench gate IGBT device in this embodiment has filling grooves on both sides of the first polysilicon 62 of each first trench 51, and the filling cavity formed between the filling groove and the inner wall of the first gate oxide layer 61 is filled with an insulating medium 63. The rest of the structure of the trench gate IGBT device in this embodiment is exactly the same as that in Embodiment 1.

Preferably, the insulating medium 63 located on both sides of the first polysilicon 62 in each first trench 51 is symmetrically arranged and evenly distributed along the length direction of the first trench 51, and the insulating medium 63 in the two first trenches 51 is symmetrically arranged and evenly distributed along the length direction of the first trench 51. At this time, the first conductive type source region 40 in the entire device can form an overlapping area with the insulating medium 63, so that the short-circuit current of the entire device is reduced, thereby improving the short-circuit capability of the device.

The present invention also provides a method for preparing the trench gate IGBT device in Embodiment 1 and Embodiment 2, comprising the following steps:

Step 1: As shown in FIG. 5A , a semiconductor substrate is provided, on which a first conductivity type drift region 10 is formed.

Step 2: As shown in FIG. 5A , a carrier storage layer 20 is formed above the first conductive type drift region 10 using a high energy injection technique.

Step 3, as shown in FIG5B , a first trench 51 and a second trench 52 are formed on the substrate by etching. Specifically, the first trench 51 is used to form a real gate, and the second trench 52 is used to form a virtual gate. The number and specific form of the first trench 51 and the second trench 52 can be adjusted according to actual needs.

Step 4, as shown in FIG. 5B , a first gate oxide layer 61 and a second gate oxide layer 64 are deposited in the first trench 51 and the second trench 52, respectively, and the first polysilicon 62 and the second polysilicon 65 are filled. In actual operation, the gate oxide layer can be deposited using existing technology, such as a thermal oxidation process. After the polysilicon is filled, the polysilicon can also be etched back to remove excess polysilicon.

Step 5, as shown in FIG5C, the first polysilicon 62 in the first trench 51 is etched to form a filling groove, and the insulating medium 63 is filled in the filling cavity formed by the filling groove and the first gate oxide layer 61. Specifically, the filling groove extends from the top of the first polysilicon 62 to the bottom of the first polysilicon 62. When etching the filling groove, multiple filling grooves can be etched on the first polysilicon 62 as needed, and the specific shape and position of the filling groove can also be adjusted as needed. The figure only illustrates the case of grooving on one side of the first polysilicon 62 in Example 1. The filling method of the insulating medium 63 can also adopt existing process technology.

Step 6, as shown in FIG5D , the second conductivity type ions are implanted into the substrate above the carrier storage layer 20 and pushed into a trap to form a second conductivity type body region 30 . The bottom surface of the second conductivity type body region 30 is in contact with the top surface of the carrier storage layer 20 .

Step 7, as shown in FIG5D , first conductivity type ions are implanted into the second conductivity type body region 30 to form a first conductivity type source region. Specifically, the first conductivity type source region is disposed on both sides of the top of the first trench 51 and abuts against the outer wall of the first gate oxide layer 61 .

Step 8: As shown in FIG. 5E , an insulating layer 70 is deposited on the second conductive type body region 30 , and the insulating layer 70 is etched to obtain a metal contact hole.

Step 9, as shown in FIG. 5E , metal is deposited in the metal contact hole to obtain a metal lead 81, and metal is deposited on the insulating layer 70 to obtain a metal layer 82. Specifically, the second conductivity type body region 30 and the first conductivity type source region are in ohmic contact with the metal lead 81, and the metal lead 81 is in ohmic contact with the metal layer 82. The metal layer 82 is used to form an emitter. The metal lead 81 is preferably tungsten.

In a specific implementation, after the front side preparation of the above-mentioned IGBT device is completed, it is also necessary to form a second conductive type collector region and a collector electrode on the back side of the substrate through a semiconductor back side process. The semiconductor back side process includes: thinning the back side of the substrate, and then forming a collector region by injecting second conductive type ions. A back side metal layer is formed on the back side of the collector region, and the back side metal layer is used to form a collector electrode.

It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims (8)

1. A trench gate IGBT device, characterized in that it comprises a substrate and a first conductive type drift region and a second conductive type body region sequentially formed on the substrate, the trench gate IGBT device further comprising a first trench and a second trench penetrating the second conductive type body region and extending into the first conductive type drift region, the first trench being filled with a first polysilicon and a first gate oxide layer located outside the first polysilicon and close to an inner wall of the first trench, a filling groove being provided on one side or both sides of the first polysilicon, the filling groove extending from the top of the first polysilicon to the bottom of the first polysilicon, a filling cavity being formed between the filling groove and the inner wall of the first gate oxide layer, the filling cavity being filled with an insulating medium, first conductive type source regions in contact with an outer wall of the first gate oxide layer being provided on both sides of the top of the first trench, the second trench being filled with a second polysilicon and a second gate oxide layer located outside the second polysilicon and close to an inner wall of the second trench. 2 . The trench gate IGBT device according to claim 1 , wherein the insulating medium comprises silicon dioxide or silicon nitride. 3 . 3 . The trench gate IGBT device according to claim 1 , wherein a plurality of the insulating dielectrics are provided along the length direction of the first trench. 4 . The trench gate IGBT device according to claim 1 , wherein two first trenches are provided, a plurality of filling grooves are arranged side by side on one side of the first polysilicon, and the filling grooves are located on a side close to another first trench. 5 . The trench gate IGBT device according to claim 1 , wherein a width of the insulating medium is smaller than a width of the first polysilicon. 6 . The trench gate IGBT device according to claim 1 , further comprising a carrier storage layer disposed between the first conductivity type drift region and the second conductivity type body region. 7. The trench gate IGBT device according to claim 1 is characterized in that an insulating layer covering the second conductive type body region, the first conductive type source region, the first trench and the second trench is arranged on the second conductive type body region, a metal contact hole penetrating the insulating layer is opened on the insulating layer, a metal lead is arranged in the metal contact hole, the insulating layer is covered with a metal layer, the first conductive type source region and the second conductive type body region are in ohmic contact with the metal lead, and the metal lead is in ohmic contact with the metal layer. 8. A method for preparing a trench gate IGBT device, comprising: Step 1, providing a semiconductor substrate, wherein the semiconductor substrate is formed with a first conductivity type drift region; Step 2: forming a carrier storage layer above the first conductivity type drift region by using a high energy injection technique; Step 3, forming a first groove and a second groove on the substrate by etching; Step 4, depositing a first gate oxide layer and a second gate oxide layer in the first trench and the second trench respectively, and filling the first polysilicon and the second polysilicon; Step 5, etching the polysilicon in the first trench to form a filling groove, and filling the filling cavity formed by the filling groove and the first gate oxide layer with an insulating medium; Step 6, injecting second conductivity type ions into the substrate above the carrier storage layer and pushing the trap to form a second conductivity type body region; Step 7, implanting first conductivity type ions into the second conductivity type body region to form a first conductivity type source region; Step 8, depositing an insulating layer on the second conductive type body region, and etching the insulating layer to obtain a metal contact hole; Step 9: deposit metal in the metal contact hole to obtain a metal lead, and deposit metal on the insulating layer to obtain a metal layer.