CN118645475B - Method for forming semiconductor device - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor device, and relates to the field of semiconductor technology. The formation method includes: providing an initial semiconductor structure including a substrate, the substrate including a first region and a second region, a P-type transistor is formed in the first region, an N-type transistor is formed in the second region, the P-type transistor includes a first gate, a first source and a first drain, and the N-type transistor includes a second gate, a second source and a second drain; forming a first metal silicide layer on the top of the first gate, the first source, the first drain, the second gate, the second source, and the second drain respectively; forming a stress layer conformally covering the surface of the initial semiconductor structure having the first metal silicide layer, the stress layer includes silicon and nitrogen, and the ratio between silicon and nitrogen is greater than 3:4. By forming a stress layer with a high silicon content in the device, the stress in the P-type transistor and the N-type transistor can be balanced, and the resistance of the metal silicide layer in the device can be reduced.

Description

Method for forming semiconductor device

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device.

Background Art

In the field of semiconductor devices, as the characteristic line width of integrated circuits shrinks to below the nanometer level, the forces between the film layers inside the device are also changing, especially in the manufacturing process of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) devices. After the metal silicide is formed, a CESL (Contact Etch Stop Layer) film layer will be formed on the silicon wafer. This film layer will exert stress on the device structure located below it, and the stress can cause the lattice to change, thereby affecting the carrier mobility inside the device. The stress generated by the same film layer on PMOS (Positive-channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor field effect transistor, referred to as P-type transistor) devices and NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor field effect transistor, referred to as N-type transistor) devices has different effects on carrier mobility.

In CMOS devices, the formation of metal silicide is not only affected by temperature, but also by the stress generated by the stress film layer. Under different stresses, the phase change temperature of the atomic structure inside the metal silicide is different, resulting in different temperatures for the metal silicide to complete the phase change in the P-type transistor and the N-type transistor in the same CMOS device. When some metal silicides are at the temperature of phase change, other parts of the metal silicides have already undergone agglomeration defects, causing manufacturing defects of the device, which in turn affects the yield of the device.

It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

Summary of the invention

In view of this, a method for forming a semiconductor device is provided. The method can balance the stress on the N-type transistor and the P-type transistor by simultaneously covering the N-type transistor and the P-type transistor with a stress layer with a high silicon content, and can reduce the resistance of the metal silicide layer, thereby improving the performance and reliability of the device.

Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

According to one aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising:

Providing an initial semiconductor structure, the initial semiconductor structure comprising a substrate, the substrate comprising a first region and a second region, the first region forming a P-type transistor, the second region forming an N-type transistor, the P-type transistor comprising a first gate and a first source and a first drain located on both sides of the first gate, the N-type transistor comprising a second gate and a second source and a second drain located on both sides of the second gate;

forming a first metal silicide layer on top of the first gate, the first source, the first drain, the second gate, the second source, and the second drain respectively;

A stress layer is formed, and the stress layer conformally covers the surface of the initial semiconductor structure having the first metal silicide layer to form a target semiconductor structure, wherein the stress layer includes silicon and nitrogen elements, and the ratio between the silicon element and the nitrogen element is greater than 3:4.

In an exemplary embodiment of the present disclosure, the method further includes:

Performing a first heat treatment on the target semiconductor structure to diffuse the silicon element in the stress layer into the first metal silicide layer to form a second metal silicide layer;

The resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer.

In an exemplary embodiment of the present disclosure, the first heat treatment includes laser annealing, the temperature of the first heat treatment is greater than 700° C., and the time of the first heat treatment is 10 ns to 100 ms.

In an exemplary embodiment of the present disclosure, the forming of the first metal silicide layer includes:

forming a metal layer, wherein the metal layer conformally covers the surface of the initial semiconductor structure;

Performing a second heat treatment on the initial semiconductor structure having the metal layer so as to diffuse metal ions in the metal layer into the N-type transistor and the P-type transistor;

The remaining metal layer is removed.

In an exemplary embodiment of the present disclosure, the temperature of the second heat treatment is less than 750°C.

In an exemplary embodiment of the present disclosure, after forming the metal layer, the method further includes:

A barrier layer is formed, wherein the barrier layer conformally covers the surface of the metal layer.

In an exemplary embodiment of the present disclosure, the method further includes:

An isolation structure is formed in the substrate, wherein the isolation structure is used to separate the P-type transistor and the N-type transistor.

In an exemplary embodiment of the present disclosure, before forming the metal layer, the method further includes:

forming a passivation layer, wherein the passivation layer conformally covers the surface of the initial semiconductor structure;

forming a photoresist layer on the passivation layer;

The passivation layer is etched using the photoresist layer as a mask to form a sub-passivation layer, wherein the sub-passivation layer covers the surface of the isolation structure.

In an exemplary embodiment of the present disclosure, after forming the second metal silicide layer, the method further includes:

An insulating layer is formed, where the insulating layer covers the target semiconductor structure and fills a gap between the P-type transistor and the N-type transistor.

In an exemplary embodiment of the present disclosure, the ratio between silicon element and nitrogen element in the stress layer is 7:8-15:8.

In an exemplary embodiment of the present disclosure, the stress layer is formed by plasma enhanced chemical vapor deposition, chemical vapor deposition or atomic layer deposition.

In an exemplary embodiment of the present disclosure, a precursor for forming the stress layer includes silane and ammonia; or a precursor for forming the stress layer includes silane and nitrogen.

The present invention provides a method for forming a semiconductor device. The method forms a first metal silicide layer on an N-type transistor and a P-type transistor, and forms a stress layer on the first metal silicide layer. The ratio between silicon and nitrogen in the stress layer is greater than 3:4, so that the silicon content in the stress layer is relatively high. On the one hand, the stress layer can be used to balance the pressure in the P-type transistor and the N-type transistor. On the other hand, due to the high silicon content in the stress layer, the phase change temperature of the metal silicide in the P-type transistor and the N-type transistor can be balanced to form a uniform metal silicide layer with low resistivity, thereby avoiding the formation of agglomeration defects and improving the yield of the device.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG. 1 is a flow chart of a method for forming a semiconductor device in an exemplary embodiment of the present disclosure.

FIG. 2 is a schematic structural diagram of an initial semiconductor structure in an exemplary embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram of an initial semiconductor structure having a passivation layer in an exemplary embodiment of the present disclosure.

FIG. 4 is a schematic structural diagram of an initial semiconductor structure having a sub-passivation layer in an exemplary embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a device structure for forming a metal layer in an exemplary embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a device structure for forming a barrier layer in an exemplary embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a device structure for forming a first metal silicide layer in an exemplary embodiment of the present disclosure.

FIG. 8 is a schematic structural diagram of a target semiconductor structure in an exemplary embodiment of the present disclosure.

FIG. 9 is a schematic diagram of a device structure for forming a second metal silicide layer in an exemplary embodiment of the present disclosure.

FIG. 10 is a schematic diagram of a device structure for forming an insulating layer in an exemplary embodiment of the present disclosure.

The reference numerals are described as follows:

100, substrate; 210, N-type transistor; 211, second gate; 11, second gate oxide layer; 12, second gate layer; 13, second gate protection layer; 131, insulating material layer; 132, dielectric layer; 212, second source; 213, second drain; 220, P-type transistor; 221, first gate; 21, first gate oxide layer; 22, first gate layer; 23, first gate protection layer; 222, first source; 223, first drain; 310, first metal silicide layer; 320, second metal silicide layer; 330, metal layer; 400, stress layer; 500, blocking layer; 600, passivation layer; 610, photoresist layer; 601, sub-passivation layer; 700, insulating layer; 1000, isolation structure; A, first region; B, second region.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements/components/etc. may exist in addition to the listed elements/components/etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

In related technologies, CMOS devices are widely used in modern microelectronics as an integrated circuit technology, especially in microprocessors, memories and other digital logic circuits, which combine N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors. CMOS devices have the characteristics of low power consumption and high performance.

With the continuous advancement of semiconductor technology, the size of CMOS devices continues to shrink, which puts higher requirements on the CMOS process. At present, in order to reduce the short channel effect and other problems caused by the miniaturization of device size, a metal silicide layer is usually formed on the surface of the device, and further heat treatment process can be used to diffuse the silicon ions inside the device into the formed metal silicide layer to form a metal silicide layer with a lower resistivity, so as to reduce the contact resistance of the device.

After the metal silicide layer is formed, a CESL film layer is also formed on the device to provide a basis for the subsequent device manufacturing. The CESL film layer will produce stress on the device, especially for P-type transistors, whose source and drain can be formed using silicon germanium (SiGe) process. Under the action of stress, the carrier migration amount inside the silicon germanium film layer is greatly improved, but the stress will affect the phase change of the metal silicide layer. Among them, for P-type transistors, the greater the stress, the lower the phase change temperature of the metal silicide layer, and it can form a low-resistance metal silicide layer at a lower temperature. N-type transistors require a higher temperature to complete the transformation of the low-resistance metal silicide layer. Increasing the temperature will cause the low-resistance metal silicide layer formed first in the P-type transistor area to have agglomeration defects, thereby affecting the performance of the device.

Based on this, an embodiment of the present disclosure provides a method for forming a semiconductor device, as shown in FIG. 1 , in combination with FIGS. 2 to 10 , the method includes: step S10 to step S30 .

Wherein, step S10: providing an initial semiconductor structure, the initial semiconductor structure includes a substrate 100, the substrate 100 includes a first region A and a second region B, a P-type transistor 220 is formed in the first region A, an N-type transistor 210 is formed in the second region B, the P-type transistor 220 includes a first gate 221 and a first source 222 and a first drain 223 located on both sides of the first gate 221, and the N-type transistor 210 includes a second gate 211 and a second source 212 and a second drain 213 located on both sides of the second gate 211;

Step S20: forming a first metal silicide layer 310 on the top of the first gate 221 , the first source 222 , the first drain 223 , the second gate 211 , the second source 212 , and the second drain 213 , respectively;

Step S30: forming a stress layer 400, which conformally covers the surface of the initial semiconductor structure having the first metal silicide layer 310 to form a target semiconductor structure, wherein the stress layer 400 includes silicon and nitrogen elements, and the ratio between silicon and nitrogen elements is greater than 3:4.

The present disclosure provides a method for forming a semiconductor device. The method forms a first metal silicide layer 310 on an N-type transistor 210 and a P-type transistor 220, and forms a stress layer 400 on the first metal silicide layer 310. The ratio between silicon and nitrogen in the stress layer 400 is greater than 3:4, so that the silicon content in the stress layer 400 is relatively high. On the one hand, the stress layer 400 can be used to balance the pressure in the P-type transistor and the N-type transistor. On the other hand, due to the high silicon content in the stress layer 400, the phase change temperature of the metal silicide in the P-type transistor and the N-type transistor can be balanced to form a uniform metal silicide layer with a low resistivity, thereby avoiding the formation of agglomeration defects and improving the yield of the device.

The following will describe in detail the steps of the method for forming a semiconductor device according to the embodiment of the present disclosure in conjunction with the accompanying drawings:

In an embodiment provided in the present disclosure, as shown in FIG. 2 , in step S10 , an initial semiconductor structure is provided, the initial semiconductor structure includes a substrate 100 , the substrate 100 includes a first region A and a second region B, the first region A is formed with a P-type transistor 220 , and the second region B is formed with an N-type transistor 210 .

In the embodiment provided in the present disclosure, the substrate 100 may include at least one first region A and at least one second region B. Each first region A and each second region B may be defined and divided on the substrate 100 according to the actual structural requirements of the device. Although in the embodiment of the present disclosure, a P-type transistor 220 is formed on a first region A and an N-type transistor 210 is formed on a second region B as an example, it does not limit the number and arrangement of the first region A, the second region B, the P-type transistor 220, and the N-type transistor 210 on the substrate 100.

The substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a germanium silicon (GeSi) substrate, SOI (Silicon On Insulator), SOS (Silicon-on-Sapphire) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate 100 as a P-type silicon (Si) substrate as an example. Of course, for other types of substrates 100, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.

The substrate 100 includes a first region A, which may be an N-type well formed on the substrate 100 . A P-type transistor 220 is formed in the first region A. The P-type transistor 220 includes a first gate 221 and a first source 222 and a first drain 223 located on both sides of the first gate 221 .

As shown in Figure 2, forming a P-type transistor 220 in the first area A may include: performing epitaxial growth on the first area A of the substrate 100 to form an epitaxial film layer crystal-matched with the substrate 100; doping P-type impurity elements into the substrate 100 having the epitaxial film layer to form a first source 222 and a first drain 223 on the substrate 100; forming a first gate oxide layer 21 between the first source 222 and the first drain 223; forming a first gate layer 22 on the first gate oxide layer 21; forming a first gate protection layer 23 on the sidewall jointly formed by the first gate layer 22 and the first gate oxide layer 21, and the first gate oxide layer 21, the first gate layer 22 and the first gate protection layer 23 jointly constitute the first gate 221.

Among them, the P-type impurity element can be a Group III element, for example, it can be boron (B), aluminum (Al), gallium (Ga), indium (In) or thallium (Tl), etc. In the present disclosure, in order to achieve a better doping effect, increase the diffusion rate of the impurity element in the silicon substrate 100, and facilitate the control of the manufacturing process, boron (B) element can be selected as the P-type impurity element, but the specific doping element in the P-type transistor 220 can be selected from other elements according to process requirements and device design requirements.

The epitaxial film layer can be formed by methods such as Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE), and the size of the epitaxial film layer and the method used can be selected and adjusted according to the actual design requirements of the device.

The first gate oxide layer 21 may be silicon dioxide (SiO ₂ ) or other high-K dielectric material layer, such as one or more of hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ) or yttrium oxide (Y ₂ O ₃ ). It may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE) or plasma enhanced chemical vapor deposition (PECVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the first gate oxide layer 21 .

The first gate layer 22 is formed on the surface of the first gate oxide layer 21. The first gate layer 22 can be polysilicon (poly) or other metal materials, such as one or more of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), cobalt (Co), nickel (Ni), ruthenium (Ru) or iridium (Ir). It can be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, photolithography or etching, and can be selected according to the material and other characteristics of the first gate layer 22. In the embodiment provided in the present disclosure, the first gate layer 22 is polysilicon as an example for explanation, but it should be noted that the first gate layer 22 of the present disclosure can also be made of materials other than polysilicon.

The first gate protection layer 23 is formed on the sidewall formed by the first gate oxide layer 21 and the first gate layer 22. The first gate protection layer 23 may include at least one insulating material layer 131 and at least one dielectric layer 132 sequentially formed along the sidewall direction away from the first gate layer 22. Of course, the first gate protection layer 23 may also be formed by one insulating material layer 131 or one dielectric layer 132 according to the actual structural requirements of the device. If there are multiple insulating material layers 131 and multiple dielectric layers 132, the multiple insulating material layers 131 and the multiple dielectric layers 132 are alternately distributed on the sidewall of the first gate layer 22 in sequence along the sidewall direction away from the first gate layer 22.

The insulating material layer 131 in the first gate protection layer 23 may be silicon dioxide (SiO ₂ ) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ) or yttrium oxide (Y ₂ O ₃ ). It may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method may be adaptively selected and adjusted according to the material characteristics of the insulating material layer 131 .

The dielectric layer 132 may be made of materials such as silicon nitride (Si ₃ N ₄ ) and may be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the dielectric layer 132 may also be formed by other materials and processes according to the actual structural requirements of the device.

The substrate 100 includes a second region B, which may be a P-type well formed on the substrate 100 . An N-type transistor 210 is formed in the second region B. The N-type transistor 210 includes a second gate 211 and a second source 212 and a second drain 213 located on both sides of the second gate 211 .

As shown in Figure 2, forming an N-type transistor 210 in the second region B may include: doping N-type impurity elements into the second region B of the substrate 100 to form a second source 212 and a second drain 213 on the substrate 100; forming a second gate oxide layer 11 between the second source 212 and the second drain 213; forming a second gate layer 12 on the second gate oxide layer 11; forming a second gate protection layer 13 on the sidewall jointly formed by the second gate layer 12 and the second gate oxide layer 11, and the second gate oxide layer 11, the second gate layer 12 and the second gate protection layer 13 together constitute the second gate 211.

Among them, the N-type impurity element can be a V group element, for example, it can be phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc. The specific doping element in the N-type transistor 210 can select other elements according to the process requirements and device design requirements. In addition, the second gate 211 in the N-type transistor 210 includes a second gate oxide layer 11, a second gate layer 12, and a second gate protection layer 13, and the materials and manufacturing processes used in each film layer of the second gate 211 and the first gate 221 are the same or substantially the same, which will not be repeated here.

In an embodiment provided by the present disclosure, as shown in FIG. 2 , before forming a P-type transistor 220 and an N-type transistor 210 on a substrate 100 , the method further includes: forming an isolation structure 1000 in the substrate 100 , the isolation structure 1000 being used to separate the P-type transistor 220 and the N-type transistor 210 . Among them, the isolation structure 1000 may be a shallow trench isolation structure formed in the substrate 100 , which may prevent current leakage between devices and improve the performance and reliability of the device. Specifically, a region for forming the isolation structure 1000 may be defined on the substrate 100 by photolithography, and a shallow trench may be etched in the defined region by dry or wet etching; an insulating material, such as silicon oxide (SiO ₂ ), may be filled in the shallow trench to form an isolation film layer in the shallow trench; and then a planarization process may be performed to expose the surface of the substrate 100 . The number of the isolation structures 1000 is at least one, and when the number is multiple, the multiple isolation structures 1000 may be distributed in an array on the substrate 100 .

In the embodiment provided by the present disclosure, in order to avoid damage or destruction to the isolation structure 1000 in the subsequent device manufacturing process, thereby affecting the reliability of the device, after forming the P-type transistor 220 and the N-type transistor 210 on the substrate 100, as shown in FIG3, the formation method further includes: forming a passivation layer 600, the passivation layer 600 conformally covers the surface of the initial semiconductor structure; forming a photoresist layer 610 on the passivation layer 600; using the photoresist layer 610 as a mask, etching the passivation layer 600 to form a sub-passivation layer 601, the sub-passivation layer 601 covers the surface of the isolation structure 1000. By forming the sub-passivation layer 601 on the surface of the isolation structure 1000, as shown in FIG4, in the subsequent process, the isolation structure 1000 can be prevented from being damaged, thereby ensuring the integrity of the isolation structure 1000.

Among them, the sub-passivation layer 601 is obtained by etching the passivation layer 600, and the materials of the two are the same. Both can be made of materials such as silicon nitride ( _{Si3N4 )} . Among them, the passivation layer 600 can be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the passivation layer 600 can also be formed by other materials and process methods according to the actual structural requirements of the device.

In the embodiment provided in the present disclosure, in step S20, as shown in FIG. 7 , a first metal silicide layer 310 is formed on the top of the first gate 221 , the first source 222 , the first drain 223 , the second gate 211 , the second source 212 , and the second drain 213 , respectively.

As shown in FIG. 5 , forming the first metal silicide layer 310 includes: forming a metal layer 330, wherein the metal layer 330 conformally covers the surface of the initial semiconductor structure; performing a second heat treatment on the initial semiconductor structure having the metal layer 330 so that the metal ions in the metal layer 330 diffuse into the N-type transistor 210 and the P-type transistor 220; and removing the remaining metal layer 330.

After forming the metal layer 330, in order to avoid the influence of external impurities on the metal layer 330, especially to avoid the oxidation of the metal layer 330 by oxygen, after forming the metal layer 330, as shown in FIG6, the method further includes: forming a barrier layer 500, and the barrier layer 500 is conformally covered on the surface of the metal layer 330. Among them, the barrier layer 500 can be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc., which can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) and other methods. The specific material and formation process of the barrier layer 500 can be adaptively selected and adjusted according to the device process design. Taking the barrier layer 500 as titanium nitride (TiN) as an example, the thickness of the barrier layer 500 can be 5nm~15nm, for example, the barrier layer 500 can be 5nm, 8nm, 10nm, 13nm, 15nm, etc. The thickness of the barrier layer 500 can be selected according to the actual requirements of the device process.

Among them, in order to transform the silicon element in the substrate 100 from a crystalline state to an amorphous structure, that is, to increase the mobility of silicon ions so that the silicon ions can enter other film layers by diffusion and the like, before forming the metal layer 330, the method may also include: using ion implantation to activate the silicon ions in the substrate 100, especially the silicon ions in the first gate layer 22, the second gate layer 12, the first source 222, the first drain 223, the second source 212 and the second drain 213. In subsequent processes, the silicon ions in the above-mentioned film layers can combine with other ions to form different molecular structures.

In addition, in order to increase the reaction area of the first gate 221 and the second gate 211, part of the first gate protection layer 23 and part of the second gate protection layer 13 may be appropriately removed to expose the sidewalls of the tops of the first gate layer 22 and the second gate layer 12. Furthermore, in order to better provide a basis for subsequent processes, the device may be cleaned to remove contaminants on the device surface to ensure the cleanliness of the device surface and provide a good structural basis for subsequent film layer formation.

A metal layer 330 is formed on the surface of the initial semiconductor structure, wherein the metal layer 330 may be a cobalt (Co) film layer, or may be made of metal nickel (Ni). The present disclosure is illustrative with the metal layer 330 being a cobalt (Co) film layer, and for other metal materials, the embodiments provided in the present disclosure need to be adaptively deformed or adjusted to obtain subsequent process steps.

The thickness of the metal layer 330 (cobalt) can be 5nm to 20nm, for example, 5nm, 10nm, 15nm, 20nm, etc. The metal layer 330 can be formed on the surface of the initial semiconductor structure by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other methods. The initial semiconductor structure with the metal layer 330 is subjected to a second heat treatment so that the metal ions in the metal layer 330 diffuse into the N-type transistor 210 and the P-type transistor 220 with free silicon ions to form a first metal silicide layer 310 on top of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212, and the second drain 213.

After forming the first metal silicide layer 310, it is necessary to remove the remaining metal layer 330 and the barrier layer 500. The barrier layer 500 may be removed by dry etching or wet etching, and then the remaining metal layer 330 may be removed. The removal method may be selected according to actual process requirements.

The first metal silicide layer 310 may include dicobalt silicon (Co ₂ Si) and cobalt silicon (CoSi), and the thickness of the first metal silicide layer 310 may be 5nm to 30nm, for example, 5nm, 8nm, 15nm, 20nm, 22nm, 25nm, 29nm or 30nm, etc. The thickness of the first metal silicide layer 310 formed is different according to the different ratios between dicobalt silicon (Co ₂ Si) and cobalt silicon (CoSi) in the first metal silicide layer 310. In this article, thickness refers to the size of the film layer in the direction perpendicular to the substrate 100, wherein the above thickness may refer to one of the maximum thickness, the minimum thickness or the average thickness, and any of the above three thicknesses may be used for the comparison and measurement of the thicknesses of different film layers.

The temperature of the second heat treatment is less than 750°C. Specifically, the second heat treatment process may include a first sub-heat treatment and a second sub-heat treatment, wherein the first sub-heat treatment includes: at a temperature of 250°C to 410°C, using cobalt ions in the metal layer 330 as a diffusion source, so that cobalt ions are doped into the N-type transistor 210 and the P-type transistor 220, especially at the top of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212, and the second drain 213, the concentration of cobalt ions is high, and more dicobalt silicon (Co ₂ Si) is formed. The second sub-heat treatment includes: at a temperature of 410°C to 700°C, the cobalt ions continue to be used as a diffusion source, further diffused into the N-type transistor 210 and the P-type transistor 220, and cobalt silicon (CoSi) is formed in the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212, and the second drain 213. After the second heat treatment, dicobaltized silicon (Co ₂ Si) and cobaltized silicon (CoSi) can exist in the first metal silicide layer 310 at the same time. The resistivity of dicobaltized silicon (Co ₂ Si) and cobaltized silicon (CoSi) are both high, and the resistance value of the formed first metal silicide is also large. The temperature range of the first sub-heat treatment and the second sub-heat treatment in the second heat treatment is only shown as an exemplary embodiment. In the actual heat treatment process, the above temperature range does not have a strict limit and can be adaptively adjusted according to the actual process requirements.

As the temperature of the heat treatment further increases, such as when the temperature increases to greater than 700°C, at this time, the silicon ions in the device diffuse into the first metal silicide layer 310 as a diffusion source, and the formed dicobalt silicon (Co ₂ Si) and cobalt silicon (CoSi) continue to combine with the silicon ions to form cobalt disilicide (CoSi ₂ ). The resistivity of cobalt disilicide (CoSi ₂ ) is smaller than that of dicobalt silicon (Co ₂ Si) and cobalt silicon (CoSi). The resistance value of cobalt disilicide (CoSi ₂ ) is small, which can effectively reduce the contact resistance and improve the overall electrical performance of the device.

However, the inventors have found that in a CMOS device, after the stress layer 400 is formed, the N-type transistor 210 and the P-type transistor 220 have a large difference in the carrier mobility due to the stress. At the same time, under different stresses, the diffusion efficiency of silicon ions in the P-type transistor 220 and the N-type transistor 210 into the first metal silicide layer 310 is different, resulting in different phase change temperatures of the metal silicide layer. When the first metal silicide layer 310 in the N-type transistor 210 undergoes a phase change, a higher temperature condition is required. Under this temperature condition, the P-type transistor 220 has completed the phase change process and formed a metal silicide film layer with a low resistance phase. In particular, after the stress layer 400 is formed on the device, the metal silicide film layer with a low resistance phase in the P-type transistor 220 agglomerates due to the dual effects of high temperature and stress, forming agglomeration defects, and cannot form a metal silicide film layer with good performance, resulting in a decrease in the overall performance of the device. The phase change refers to the transformation of molecules from dicobalt silicon (Co ₂ Si) or cobalt silicon (CoSi) to cobalt disilicide (CoSi ₂ ) in the metal silicide layer.

Therefore, in order to avoid the difference in process conditions for forming the metal silicide film layer in the first region A and the second region B of the substrate 100, in step S30, as shown in FIG8, a stress layer 400 is formed, and the stress layer 400 conformally covers the surface of the initial semiconductor structure having the first metal silicide layer 310 to form a target semiconductor structure, wherein the stress layer 400 includes silicon and nitrogen, and the ratio between the silicon and nitrogen is greater than 3:4. Due to the high content of silicon in the stress layer 400, the tensile stress inside the film layer can be increased, the compressive stress generated in the P-type transistor 220 can be balanced, and the agglomeration defect of the metal silicide film layer in the P-type transistor 220 can be avoided. At the same time, the electron mobility inside the N-type transistor 210 can be increased by the stress generated by the stress layer 400. In addition, the silicon in the stress layer 400 can also be used as a silicon source to further diffuse into the first metal silicide layer 310, which is conducive to the formation of a low-resistance metal silicide film layer.

In the embodiment provided by the present disclosure, the ratio between silicon and nitrogen in the stress layer 400 may be 7:8-15:8, for example, the silicon-nitrogen ratio may be 7:8, 8:8, 9:8, 10:8, 11:8, 12:8, 13:8, 14:8, 15:8, etc. For example, the stress layer 400 may be Si ₄ N ₄ , Si ₅ N ₄ , etc. The thickness of the stress layer 400 may be 10 nm (nanometer)-60 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, etc.

The precursor for forming the stress layer 400 may include silane (SiH ₄ ) and _ammonia (NH ₃ ), and the reaction process thereof is SiH ₄ +NH ₃ → _SixNy + _H2 ↑, wherein X≥Y. The precursor for forming the stress layer 400 may also include silane (SiH ₄ ) and nitrogen (N ₂ ), and the reaction process thereof is SiH ₄ +N ₂ → _SixNy + _H2 ↑, wherein X≥Y. In the above two embodiments, the hydrogen generated during the reaction may be discharged or collected for recycling. The precursor may also be a substance including silicon _ions and nitrogen _ions , and the reaction process thereof is Si ⁺ +N ^— → _SixNy , wherein X≥Y. The specific substance type of the precursor may be selected from different types of substances according to the change of the formation method.

It should be noted that, during the reaction process, in order to control the composition and performance of the stress layer 400, auxiliary gas or doping elements, such as hydrogen, oxygen, etc., may be introduced to improve the performance of the stress layer 400. In addition, other combinations of precursors may be used to form a stress layer 400 with a high silicon content, but they must be combined with corresponding process formation methods and reaction conditions such as temperature, pressure, and flow rate.

The stress layer 400 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE), sputtering or sol-gel method. For example, chemical vapor deposition (CVD) can effectively control the silicon content in the stress layer 400 by using precursors and adjusting the flow ratio and reaction conditions (such as temperature, pressure, etc.) of the precursors. Plasma enhanced chemical vapor deposition (PECVD) can introduce plasma on the basis of CVD to reduce the deposition temperature and improve the quality of the film layer, and more accurately control the composition and structure of the stress layer 400. Atomic layer deposition (ALD) can accurately control the thickness and composition of the stress layer 400 by alternately introducing silicon and nitrogen precursors and performing self-limiting surface reactions in each cycle. Sputtering can form the stress layer 400 by using silicon and nitrogen targets and sputtering materials onto the surface of the device under the bombardment of high-energy particles. The silicon content of the stress layer 400 can be controlled by adjusting the sputtering parameters. The sol-gel method can prepare a precursor solution of the stress layer 400 with a high silicon content through a sol-gel process, and then coat the solution on the surface of the device by spin coating, dipping or spraying, and form the stress layer 400 by heat treatment.

The first metal silicide layer 310 may include dicobalt silicon (Co ₂ Si), cobalt silicon (CoSi), or a mixture of dicobalt silicon (Co ₂ Si) and cobalt silicon (CoSi). Meanwhile, since the temperature can reach about 700° C. during the second sub-heat treatment process, under this temperature condition, silicon ions in the device substrate 100 actually diffuse into the first metal silicide layer 310 as diffusion sources, and low-resistance cobalt disilicide (CoSi ₂ ) also exists in the first metal silicide layer 310 . However, since the diffusion of silicon ions is inhibited by the boundary and the temperature condition, the low-resistance cobalt disilicide (CoSi ₂ ) exists at the bottom of the first metal silicide layer 310 and cannot diffuse to the top thereof, that is, the top of the first metal silicide layer 310 still exists in the form of high-resistance dicobalt silicon (Co ₂ Si) or cobalt silicon (CoSi).

In order to reduce the resistivity in the metal silicide layer, as shown in FIG9 , the formation method further includes: performing a first heat treatment on the target semiconductor structure to diffuse the silicon element in the stress layer 400 into the first metal silicide layer 310 to form a second metal silicide layer 320; wherein the resistivity of the second metal silicide layer 320 is less than the resistivity of the first metal silicide layer 310. The second metal silicide film layer may include cobalt disilicide (CoSi ₂ ), and the thickness of the second metal silicide layer 320 may be 15 nm to 55 nm, for example, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, etc.

Since the silicon content in the stress layer 400 is relatively high, the stress layer 400 can be used as a silicon source, that is, the silicon ions in the stress layer 400 diffuse into the first metal silicide film layer under the process conditions of the first heat treatment to increase the silicon ion content at the top of the first metal silicide layer 310, so as to promote the transformation of the metal silicide from a high resistance phase to a low resistance phase. At the same time, the silicon ions inside the device diffuse into the first metal silicide layer 310 at the same time, and through the simultaneous action of two silicon sources, a second metal silicide layer 320 with uniform cobalt disilicide (CoSi ₂ ) is formed, which improves the agglomeration defects formed in the P-type transistor 220 due to the dual effects of stress and high temperature, and balances the stress between the P-type transistor 220 and the N-type transistor 210. The formed second metal silicide layer 320 has a small resistivity and good electrical properties.

Wherein, the first heat treatment may include laser annealing treatment, the temperature of the first heat treatment is greater than 700°C, and the time of the first heat treatment is 10ns~100ms. Since the first heat treatment process needs to promote the diffusion of silicon ions in the device and silicon ions in the stress layer 400 into the first metal silicide layer 310, it is necessary to provide high temperature conditions, such as the temperature of the first heat treatment can be 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C or even higher temperatures. The time of the first heat treatment can also be different according to the temperature in the temperature condition. The first heat treatment time can be in the nanosecond level to the millisecond level. For example, under the condition of higher temperature, the processing time can be appropriately shortened; under the condition of lower temperature, the processing time can be appropriately increased. The first heat treatment may be a laser annealing process, which can rapidly heat to 1100°C or above and activate silicon atoms to enter the lattice position within the first metal silicide layer 310, thereby changing the resistance phase of the metal silicide. The laser annealing process can also reduce thermal damage to surrounding film layers.

In the embodiment provided by the present disclosure, in order to prevent capacitive coupling and short circuit between the P-type transistor 220 and the N-type transistor 210, after forming the second metal silicide layer 320, as shown in FIG10, the formation method may further include: forming an insulating layer 700, the insulating layer 700 covers the target semiconductor structure and fills the gap between the P-type transistor 220 and the N-type transistor 210. After forming the insulating layer 700, the formation method may further include: performing a planarization process on the insulating layer 700.

Among them, the insulating layer 700 can be silicon dioxide (SiO ₂ ) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ) or yttrium oxide (Y ₂ O ₃ ), etc. It can be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method can be adaptively selected and adjusted according to the characteristics of the material of the insulating layer 700 .

The insulating layer 700 may be planarized by chemical mechanical polishing (CMP) to provide a good structural foundation for subsequent process steps and ensure the isolation reliability of the device.

The present disclosure provides a method for forming a semiconductor device. The method forms a first metal silicide layer 310 on an N-type transistor 210 and a P-type transistor 220, and forms a stress layer 400 with a high silicon content on the first metal silicide layer 310. On the one hand, the stress layer 400 can balance the pressure in the PMOS and NMOS. On the other hand, since the silicon content in the stress layer 400 is high, the phase change temperature of the metal silicide in the PMOS and NMOS can be balanced to form a uniform metal silicide layer with a low resistivity, thereby avoiding the formation of agglomeration defects and improving the yield of the device.

It should be noted that, although the steps of the method for forming a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and/or one step may be decomposed into multiple steps, etc.

The present disclosure also provides a semiconductor device, as shown in FIG10 , which can be manufactured using the above-mentioned method for forming a semiconductor device. The semiconductor device has a metal silicide film layer with a relatively low resistivity, and the stress layer 400 can better balance the stress between the P-type transistor 220 and the N-type transistor 210 inside it, and the device as a whole has better performance and higher yield.

The semiconductor device provided by the present disclosure can be applied to dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc. Of course, it can also be applied to other storage devices not listed here, which will not be listed one by one.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims (9)

1. A method of forming a semiconductor device, comprising:

Providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, the substrate comprises a first region and a second region, a P-type transistor is formed in the first region, an N-type transistor is formed in the second region, the P-type transistor comprises a first grid, a first source electrode and a first drain electrode which are positioned on two sides of the first grid, and the N-type transistor comprises a second grid, a second source electrode and a second drain electrode which are positioned on two sides of the second grid;

forming an isolation structure in the substrate, wherein the isolation structure is used for isolating the P-type transistor and the N-type transistor;

forming a passivation layer which covers the surface of the initial semiconductor structure in a conformal manner;

Forming a photoresist layer on the passivation layer;

Etching the passivation layer by taking the photoresist layer as a mask to form a sub-passivation layer, wherein the sub-passivation layer covers the surface of the isolation structure;

forming first metal silicide layers on top of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode respectively;

Forming a stress layer which covers the surface of the initial semiconductor structure with the first metal silicide layer in a conformal manner to form a target semiconductor structure, wherein the stress layer comprises silicon elements and nitrogen elements, and the ratio between the silicon elements and the nitrogen elements is greater than 3:4;

performing first heat treatment on the target semiconductor structure to diffuse silicon element in the stress layer into the first metal silicide layer to form a second metal silicide layer;

wherein the resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer.

2. The method of forming a semiconductor device according to claim 1, wherein the first heat treatment includes a laser annealing treatment, the temperature of the first heat treatment is greater than 700 ℃, and the time of the first heat treatment is 10ns to 100ms.

3. The method of forming a semiconductor device according to claim 1, wherein the forming a first metal silicide layer comprises:

forming a metal layer which is conformal and covers the surface of the initial semiconductor structure;

Performing a second heat treatment on the initial semiconductor structure with the metal layer to diffuse metal ions in the metal layer into the N-type transistor and the P-type transistor;

And removing the residual metal layer.

4. The method for forming a semiconductor device according to claim 3, wherein a temperature of the second heat treatment is less than 750 ℃.

5. The method for forming a semiconductor device according to claim 4, wherein after the forming of the metal layer, the method further comprises:

and forming a barrier layer which is conformal to cover the surface of the metal layer.

6. The method of forming a semiconductor device of claim 1, wherein after the forming the second metal silicide layer, the method further comprises:

An insulating layer is formed that covers the target semiconductor structure and fills a gap between the P-type transistor and the N-type transistor.

7. The method of forming a semiconductor device according to claim 1, wherein a ratio between silicon element and nitrogen element in the stress layer is 7:8 to 15:8.

8. The method of forming a semiconductor device according to any one of claims 1 to 7, wherein the stress layer is formed by a plasma enhanced chemical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method.

9. The method for forming a semiconductor device according to any one of claims 1 to 7, wherein a precursor for forming the stress layer includes silane and ammonia; or precursors for forming the stress layer include silane and nitrogen.