CN118645472A - Method for preparing a semiconductor device - Google Patents

Abstract

The present invention provides a method for preparing a semiconductor device, comprising the following steps: providing a semiconductor substrate, wherein a groove in the semiconductor substrate penetrates a dielectric layer and an etching stop layer, and exposes a bottom metal layer; injecting silicon elements into the surface of the dielectric layer and the sidewalls of the groove near the opening, and filling metal materials in the groove to form a metal material layer, wherein the metal material layer covers the surface of the dielectric layer, and the metal material layer contacts the bottom metal layer; and removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process. The present invention injects silicon elements into the sidewalls at the opening of the groove, so that the dielectric layer at the opening of the groove is silicon-rich, and at the same time forms a metal thin layer on the sidewalls of the opening of the groove, so that the adhesion between the metal material at the opening of the groove and the dielectric layer is strong, and there is no gap at the opening of the groove, which prevents the bottom metal layer from being corroded by the grinding slurry during the chemical mechanical polishing process, thereby improving the yield and performance of the semiconductor device.

Description

Method for preparing a semiconductor device

Technical Field

The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device.

Background Art

Currently, in the middle-end of line (MEOL) node of advanced production technology, the process of metal contact structure is as follows:

First, as shown in FIG1 , a semiconductor substrate is provided, the semiconductor substrate includes a bottom metal layer 1, an etch stop layer 2 and a dielectric layer 3 sequentially arranged on the substrate, a groove 4 is formed in the semiconductor substrate, the groove 4 penetrates the dielectric layer 3 and the etch stop layer 2, and exposes the bottom metal layer 1; then, as shown in FIG2 , a tungsten material is filled in the groove 4 by a selective tungsten filling process to form a tungsten material filling layer 5. Since the tungsten material filling layer 5 is filled from bottom to top, the adhesion between the tungsten material and the dielectric layer 3 at the side wall of the groove 4 is poor, resulting in a gap 41 between the tungsten material filling layer 5 and the side wall of the groove 4. Finally, the tungsten material outside the groove 4 is subjected to CMP (chemical mechanical polishing process) to flatten the surface of the semiconductor device. In this process, the CMP slurry (the slurry is an acidic slurry) can easily enter the bottom of the groove 4 from the gap 41, react with the bottom metal layer 1, and form an etched cavity 11 (as shown in FIG3-FIG4), thereby affecting the performance and yield of the semiconductor device.

Summary of the invention

The object of the present invention is to provide a method for preparing a semiconductor device, which can solve the problem of poor adhesion between a tungsten material and a dielectric layer on a groove sidewall in a selective tungsten filling process.

In order to solve the above problems, the present invention provides a method for preparing a semiconductor device, comprising the following steps:

A semiconductor substrate is provided, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove is formed in the semiconductor substrate, the groove passes through the dielectric layer and the etch stop layer and exposes the bottom metal layer;

Injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material to form a metal material layer, wherein the metal material layer also covers the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer;

The metal material layer on the surface of the dielectric layer is removed by a chemical mechanical polishing process.

Optionally, the specific method of “injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material, wherein the metal material covers the surface of the dielectric layer” is:

Performing a silicon ion implantation process to implant silicon elements on the surface of the dielectric layer and on the sidewalls of the groove near the opening to form a silicon-rich dielectric film layer;

A metal material is selectively filled in the groove by a CVD process, and a metal material is deposited on the silicon-rich dielectric film layer to form a metal material layer.

Furthermore, the length of the silicon-rich dielectric film layer on the sidewall of the groove accounts for 10% to 80% of the total depth of the groove.

Furthermore, the reaction gases of the CVD process include: WF6 and H2.

Optionally, the specific method of “injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material, wherein the metal material covers the surface of the dielectric layer” is:

forming a first metal material layer in the groove by a CVD process, wherein the first metal material layer fills a portion of the depth of the groove, and the first metal material contacts the bottom metal layer;

Performing a silicon ion implantation process to implant silicon elements on the surface of the dielectric layer and on the sidewalls of the groove near the opening to form a silicon-rich dielectric film layer;

A metal material is deposited in the groove by a CVD process and at the same time on the surface of the silicon-rich dielectric layer at the sidewall of the groove to form a second metal material layer, wherein the second metal material layer is located above the first metal material layer and fills the entire groove above the first metal material layer.

Furthermore, the height of the first metal material layer is greater than the thickness of the etch stop layer and less than the total depth of the groove.

Furthermore, the height of the first metal material layer is 5 nm to 40 nm greater than the thickness of the etch stop layer.

Furthermore, the reaction gases of the CVD process when forming the first metal material layer include: WF6 and H2; the reaction gases of the CVD process when forming the second metal material layer include: WF6 and H2.

Furthermore, the process parameters for silicon ion implantation are: an angle θ between the ion implantation direction and the vertical direction is 20° to 75°, an ion implantation energy is 1 KeV to 60 KeV, and an ion implantation dose is 1E14 cm ^-2 to 1E16 cm ^-2 .

Optionally, the material of the bottom metal layer is at least one of tungsten, cobalt, copper, titanium, ruthenium, aluminum, and molybdenum; the material of the etch stop layer includes silicon nitride, the material of the dielectric layer includes silicon oxide, and the material of the metal material layer is metal tungsten.

Compared with the prior art, the present invention has the following unexpected technical effects:

The present invention provides a method for preparing a semiconductor device, comprising the following steps: providing a semiconductor substrate, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove formed in the semiconductor substrate, the groove penetrating the dielectric layer and the etch stop layer, and exposing the bottom metal layer; injecting silicon elements into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling metal materials in the groove to form a metal material layer, the metal material layer also covers the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer; removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process. The present invention injects silicon elements into the sidewalls at the opening of the groove, so that the dielectric layer at the opening of the groove is silicon-rich, which makes it possible to form a metal thin layer on the sidewalls at the opening of the groove while filling the metal material, so that the adhesion between the metal material and the dielectric layer at the opening of the groove is strong after the metal is filled, and there is no gap between the metal material and the dielectric layer at the opening of the groove, which makes it possible to prevent the bottom metal layer from being corroded by the grinding slurry during the chemical mechanical polishing process, thereby improving the yield and performance of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a semiconductor substrate of a semiconductor device.

FIG. 2 is a schematic diagram of the structure of a semiconductor device after tungsten filling.

FIG. 3 is a schematic diagram of the structure of a semiconductor device after CMP.

FIG. 4 is a schematic diagram of the structure of a semiconductor device when corrosion voids are formed.

FIG. 5 is a schematic diagram of the structure of a semiconductor substrate provided in Embodiment 1 of the present invention.

FIG. 6 is a schematic diagram of the structure of the first embodiment of the present invention after the groove is formed.

FIG. 7 is a schematic diagram of the structure of the first embodiment of the present invention during the silicon ion implantation process.

FIG8 is a schematic diagram of the structure of the first embodiment of the present invention at the initial stage of the CVD process.

FIG. 9 is a schematic diagram of the structure of the first embodiment of the present invention after the CVD process.

FIG. 10 is a schematic diagram of the structure of the first embodiment of the present invention after forming an adhesion layer and an auxiliary metal film layer.

FIG. 11 is a schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention.

FIG. 12 is a schematic diagram of the structure of the second embodiment of the present invention after forming the first metal material layer.

FIG. 13 is a schematic diagram of the structure of the second embodiment of the present invention during the silicon ion implantation process.

FIG. 14 is a schematic structural diagram of the second embodiment of the present invention at the initial stage of forming the second metal material layer.

FIG. 15 is a schematic diagram of the structure of the second embodiment of the present invention after forming the second metal material layer.

Description of reference numerals:

In Figures 1 to 4:

1-bottom metal layer; 11-corrosion cavity; 2-etching stop layer; 3-dielectric layer; 4-groove; 41-gap; 5-tungsten material filling layer;

In Figures 5 to 15:

101 - bottom metal layer; 201 - groove; 210 - etching stop layer; 220 - dielectric layer; 221 - silicon-rich dielectric film layer; 300 - metal contact structure; 310 - metal material layer; 311 - first metal material layer; 312 - second metal material layer; 320 - adhesion layer; 330 - auxiliary metal film layer.

DETAILED DESCRIPTION

The following is a further detailed description of a method for preparing a semiconductor device of the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

The present invention provides a method for preparing a semiconductor device, comprising the following steps:

Step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, wherein a groove is formed in the semiconductor substrate, the groove penetrates the dielectric layer and the etch stop layer and exposes the bottom metal layer;

Step S2: injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material to form a metal material layer, wherein the metal material layer also covers the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer;

Step S3: removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process.

The present invention injects silicon elements into the side walls at the groove opening so that the dielectric layer at the groove opening is silicon-rich, which allows a thin metal layer to be formed on the side walls at the groove opening while filling the metal material, so that after the metal is filled, the adhesion between the metal material and the dielectric layer at the groove opening is strong, and there is no gap between the metal material and the dielectric layer at the groove opening, which prevents the grinding slurry from corroding the bottom metal layer during the chemical mechanical polishing process, thereby improving the yield and performance of the semiconductor device.

Embodiment 1

This embodiment provides a method for preparing a semiconductor device, comprising the following steps:

Step S11: providing a semiconductor substrate, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove is formed in the semiconductor substrate, the groove penetrates the dielectric layer and the etch stop layer and exposes the bottom metal layer;

Step S12: injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and then filling the groove with metal material to form a metal material layer, wherein the metal material layer also covers the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer;

Step S13: removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process.

A method for manufacturing a semiconductor device provided in this embodiment is described in detail below in conjunction with FIG. 5 to FIG. 11 .

Please refer to Figures 5 and 6. First, step S11 is performed to provide a semiconductor substrate, which includes a bottom metal layer 101, an etch stop layer 210 and a dielectric layer 220 arranged in sequence on the substrate. A groove 201 is formed in the semiconductor substrate, and the groove 201 passes through the dielectric layer 220 and the etch stop layer 210 to expose the bottom metal layer 101.

The specific steps of this step are:

As shown in FIG5 , first, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a substrate.

Next, a bottom metal layer 101, an etch stop layer 210 and a dielectric layer 220 are sequentially deposited on the surface of the substrate. The material of the bottom metal layer 101 may be at least one of tungsten, cobalt, copper, titanium, ruthenium, aluminum and molybdenum. The material of the etch stop layer 210 includes but is not limited to silicon nitride, and the material of the dielectric layer 220 includes but is not limited to silicon oxide.

The substrate may be a silicon substrate, and a device, such as a MOS transistor, may be formed in the substrate. In this embodiment, a source region and a drain region are formed in the substrate, and a gate structure is formed on the substrate between the source region and the drain region. The bottom metal layer 101 may be located on the surface of the source region and the surface of the drain region. The bottom metal layer 101 may be a metal film layer on the surface of the substrate, or may be a conductive contact column (i.e., the lower half of the plug) on the surface of the substrate and having a preset length, and the groove 201 formed subsequently is located above it, and the metal filling material filled in the groove 201 forms a complete metal contact (i.e., the plug) with it (the conductive contact column).

As shown in FIG. 6 , the dielectric layer 220 and the etch stop layer 210 are then etched through an etching process to expose the bottom metal layer 101 and form a groove 201 .

Please refer to Figures 7-10, and then perform step S12 to inject silicon elements into the surface of the dielectric layer 220 and the side walls of the groove 201 near the opening, and then fill the groove 201 with metal material to form a metal material layer 310. The metal material layer 310 also covers the surface of the dielectric layer 220, and the metal material layer 310 is in contact with the bottom metal layer 101.

The specific steps of this step are:

As shown in FIG7 , first, a silicon ion implantation process is performed to implant silicon elements on the surface of the dielectric layer 220 and the sidewalls of the groove 201 near the opening, and a silicon-rich dielectric film layer 221 is formed on the surface of the dielectric layer 220 and the sidewalls of the groove 201 near the opening. The parameters of the silicon ion implantation process in this step are: the angle θ between the ion implantation direction and the vertical direction is 20°~75°, the ion implantation energy is 1KeV~60 KeV, and the ion implantation dose is 1E14cm ^-2 ~1E16cm ^-2 . After ion implantation, the length of the silicon-rich dielectric film layer 221 on the sidewall of the groove 201 (i.e., the length in the direction from the groove opening toward the bottom of the groove 201) accounts for 10%~80% of the total depth of the groove 201.

As shown in FIGS. 8 and 9, metal material is selectively filled in the groove 201 by a CVD process, and metal material is deposited on the silicon-rich dielectric film layer 221, thereby forming a metal material layer 310. As shown in FIG8, at the beginning of the CVD process, metal material is gradually deposited from bottom to top in the groove 201, and at the same time, a metal film layer is deposited on the silicon-rich dielectric film layer 221. As shown in FIG9, as the CVD process proceeds, the metal material fills the groove 201 from bottom to top and merges with the metal film layer at the sidewall at the opening, and further fills the groove 201. This allows the metal material layer 310 to have good adhesion with the dielectric layer 220 at the sidewall of the groove 201, so that there is no gap between the metal material layer 310 and the dielectric layer 220 at the opening of the groove 201, which avoids the problem of corrosion of the bottom metal layer 101 during subsequent CMP.

The reaction gases of the CVD process include: WF6 and H2.

In this step: during the CVD process, since metal materials (such as metal tungsten) can form tungsten film layers on different substrates, the nucleation delay time of metal materials on different substrates is different, resulting in different deposition rates on different substrates. Specifically, for example, the nucleation delay time is short on the surface of metals and metal compounds, and the nucleation delay time is long on the surface of dielectric layer 220 such as SIO2, SIN, etc., and its essence is: since WF6 in the reaction gas and the elements on the surface of the substrate will undergo a substitution reaction in the early stage of nucleation to form an initial nucleation layer, and the difficulty of the substitution reaction (the level of chemical reaction energy) determines the speed of nucleation, for example: the substitution reaction of WF6+metal (such as W, Co, Cu) to obtain W+AFx (metal fluoride) is relatively easy to occur; the substitution reaction of WF6+dielectric material (such as SiO2, SiN) to obtain W+SiF4 is difficult to occur, and the reason is that the Si-O bond or Si-N bond in the dielectric is very stable.

Since silicon ion implantation changes the surface properties of part of the dielectric layer 220, a silicon-rich surface can be formed in a certain area (i.e., a silicon-rich dielectric film layer 221 is formed), so that during the CVD process, the WF6+dielectric material (such as SiO2, SiN) in the reaction gas obtains W+SiF4, which is a relatively difficult reaction to occur, and becomes a more likely reaction of WF6+Si to obtain W+SiF4, so that nucleation is formed faster on the surface of the silicon-rich dielectric film layer 221, and then conformal CVD W growth is performed (as shown in FIG8). Silicon ions can promote the nucleation of WF6 on the surface of the semiconductor substrate.

As shown in FIG. 10 , an adhesion layer 320 and an auxiliary metal film layer 330 are then sequentially formed on the metal material layer 310. The adhesion layer 320 includes a titanium nitride layer or includes a titanium layer and a titanium nitride layer sequentially from bottom to top. The adhesion layer 320 can form a flat, continuous and well-adhesive film layer on the surface of the metal material layer 310 to avoid the problem of the auxiliary metal film layer 330 falling off during subsequent grinding. The material of the auxiliary metal film layer 330 is the same as that of the metal material layer 310, for example, both are metal tungsten. The auxiliary metal film layer 330 can increase the thickness of the metal material layer 310 and form a flat metal structure layer to increase the process window of the subsequent CMP process.

Please refer to FIG. 11 , and then perform step S13 to remove the metal material layer 310 on the surface of the dielectric layer 220 by chemical mechanical polishing. In detail, the auxiliary metal film layer 330, the adhesion layer 320, the metal material layer 310 outside the groove 201, and the silicon-rich dielectric film layer 221 are removed in sequence by chemical mechanical polishing to obtain the metal contact structure 300. The sidewall of the groove 201 still has a partial length of the silicon-rich dielectric film layer, so that the metal contact structure 300 can be in close contact with the dielectric layer 220 at the opening of the groove 201.

Embodiment 2

Step S22 of the method for preparing a semiconductor device of this embodiment is different from step S12 of the first embodiment, step S21 of the method for preparing a semiconductor device of this embodiment is the same as step S11 of the first embodiment, and step S23 of the method for preparing a semiconductor device of this embodiment is the same as step S13 of the first embodiment. Therefore, the method for preparing a semiconductor device of this embodiment includes the following steps:

Step S21: providing a semiconductor substrate, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove is formed in the semiconductor substrate, the groove penetrates the dielectric layer and the etch stop layer and exposes the bottom metal layer;

Step S22: filling a portion of the height of the groove with metal material, then injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and then filling the remaining portion of the groove with metal material to form a metal material layer, wherein the metal material layer also covers the surface of the dielectric layer;

Step S23: removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process.

Please refer to FIG. 12 to FIG. 15 , step S22 specifically includes the following steps:

As shown in FIG12 , first, a first metal material layer 311 is formed in the groove 201 by a CVD process, the first metal material layer 311 fills a portion of the depth of the groove 201, the height of the first metal material layer 311 is greater than the thickness of the etch stop layer 210 and less than the total depth of the groove 201, and further, the height of the first metal material layer 311 is 5 nm to 40 nm greater than the thickness of the etch stop layer 210. The reaction gases of the CVD process when forming the first metal material layer 311 include: WF6 and H2.

As shown in FIG13 , then, a silicon ion implantation process is performed to implant silicon elements on the surface of the dielectric layer 220 and the sidewalls of the groove 201 near the opening, and a silicon-rich dielectric film layer 221 is formed on the surface of the dielectric layer 220 and the sidewalls of the groove 201 near the opening. The parameters of the silicon ion implantation process in this step are: the angle between the ion implantation direction and the vertical direction is 20°~75°, the ion implantation energy is 1KeV~60 KeV, and the ion implantation dose is 1E14cm ^-2 ~1E16cm ^-2 . After ion implantation, the length of the silicon-rich dielectric film layer 221 on the sidewall of the groove 201 (i.e., the length in the direction from the opening of the groove 201 toward the bottom of the groove 201) accounts for 10%~80% of the total depth of the groove 201, and at the same time, the length of the silicon-rich dielectric film layer 221 on the sidewall of the groove 201 is less than the difference between the total depth of the groove 201 and the height of the first metal material layer 311.

As shown in Figures 14 and 15, then, a metal material is deposited in the groove 201 through a CVD process and at the same time, a metal material is deposited on the surface of the silicon-rich dielectric layer 220 on the side wall of the groove 201 to form a second metal material layer 312, wherein the second metal material layer 312 is located above the first metal material layer 311 and fills the entire groove 201 above the first metal material layer 311.

As shown in FIG14, at the beginning of forming the second metal material layer 312, the first metal material layer 311 deposits metal material from bottom to top on the first metal material layer 311 in the groove 201, and at the same time deposits metal material on the surface of the silicon-rich dielectric film layer 221 at the side wall of the opening of the groove 201. As shown in FIG15, as the process proceeds, the metal material fills the groove 201 below the silicon-rich dielectric film layer 221 at the side wall, and the metal material on the inner wall of the silicon-rich dielectric film layer 221 at the side wall, and further fills the groove 201, until the entire groove 201 is filled with metal, and the second metal material layer 312 is obtained. Step S22 of this embodiment forms the first metal material layer 311 first, then performs an ion implantation process on the side wall at the opening of the groove 201, and finally further fills the groove 201 to avoid premature sealing of the opening of the groove 201 during metal filling. Among them, the first metal material layer 311 and the second metal material layer 312 together constitute the metal material layer 310. The reaction gases of the CVD process when forming the second metal material layer 312 include: WF6 and H2.

In summary, the present invention provides a method for preparing a semiconductor device, comprising the following steps: providing a semiconductor substrate, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove being formed in the semiconductor substrate, the groove penetrating the dielectric layer and the etch stop layer and exposing the bottom metal layer; injecting silicon elements into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material to form a metal material layer, the metal material layer also covering the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer; removing the metal material layer on the surface of the dielectric layer by a chemical mechanical polishing process. The present invention injects silicon elements into the side walls at the groove opening so that the dielectric layer at the groove opening is silicon-rich, which allows a thin metal layer to be formed on the side walls at the groove opening while filling the metal material, so that after the metal is filled, the adhesion between the metal material and the dielectric layer at the groove opening is strong, and there is no gap between the metal material and the dielectric layer at the groove opening, which prevents the grinding slurry from corroding the bottom metal layer during the chemical mechanical polishing process, thereby improving the yield and performance of the semiconductor device.

In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims (10)

1. A method for preparing a semiconductor device, characterized in that it comprises the following steps: A semiconductor substrate is provided, the semiconductor substrate comprising a bottom metal layer, an etch stop layer and a dielectric layer sequentially arranged on the substrate, a groove is formed in the semiconductor substrate, the groove passes through the dielectric layer and the etch stop layer and exposes the bottom metal layer; Injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material to form a metal material layer, wherein the metal material layer also covers the surface of the dielectric layer, and the metal material layer is in contact with the bottom metal layer; The metal material layer on the surface of the dielectric layer is removed by a chemical mechanical polishing process. 2. The method for preparing a semiconductor device according to claim 1, characterized in that "silicon is injected into the surface of the dielectric layer and the sidewall of the groove near the opening, and a metal material is filled in the groove, and the metal material covers the surface of the dielectric layer". The specific method is: Performing a silicon ion implantation process to implant silicon elements on the surface of the dielectric layer and on the sidewalls of the groove near the opening to form a silicon-rich dielectric film layer; A metal material is selectively filled in the groove by a CVD process, and a metal material is deposited on the silicon-rich dielectric film layer to form a metal material layer. 3. The method for preparing a semiconductor device as described in claim 2 is characterized in that the length of the silicon-rich dielectric film layer on the sidewall of the groove accounts for 10% to 80% of the total depth of the groove. 4. The method for preparing a semiconductor device as claimed in claim 2, characterized in that the reaction gases of the CVD process include: WF6 and H2. 5. The method for preparing a semiconductor device according to claim 1, characterized in that the specific method of "injecting silicon into the surface of the dielectric layer and the sidewall of the groove near the opening, and filling the groove with metal material, wherein the metal material covers the surface of the dielectric layer" is: forming a first metal material layer in the groove by a CVD process, wherein the first metal material layer fills a portion of the depth of the groove, and the first metal material contacts the bottom metal layer; Performing a silicon ion implantation process to implant silicon elements on the surface of the dielectric layer and on the sidewalls of the groove near the opening to form a silicon-rich dielectric film layer; A metal material is deposited in the groove by a CVD process and at the same time on the surface of the silicon-rich dielectric layer at the sidewall of the groove to form a second metal material layer, wherein the second metal material layer is located above the first metal material layer and fills the entire groove above the first metal material layer. 6 . The method for manufacturing a semiconductor device according to claim 5 , wherein a height of the first metal material layer is greater than a thickness of the etch stop layer and less than a total depth of the groove. 7 . The method for preparing a semiconductor device according to claim 6 , wherein a height of the first metal material layer is 5 nm to 40 nm greater than a thickness of the etch stop layer. 8. The method for preparing a semiconductor device as described in claim 5 is characterized in that the reaction gases of the CVD process when forming the first metal material layer include: WF6 and H2; the reaction gases of the CVD process when forming the second metal material layer include: WF6 and H2. 9. The method for preparing a semiconductor device according to claim 2 or 3, characterized in that the process parameters during silicon ion implantation are: the angle θ between the ion implantation direction and the vertical direction is 20°~75°, the ion implantation energy is 1KeV~60 KeV, and the ion implantation dose is 1E14cm ^-2 ~1E16cm ^-2 . 10. The method for preparing a semiconductor device as described in claim 1 is characterized in that the material of the bottom metal layer is at least one of tungsten, cobalt, copper, titanium, ruthenium, aluminum, and molybdenum; the material of the etch stop layer includes silicon nitride, the material of the dielectric layer includes silicon oxide, and the material of the metal material layer is metal tungsten.