CN118641931B - Method for locating integrated circuit design defects based on electrical rule detection - Google Patents
Method for locating integrated circuit design defects based on electrical rule detection Download PDFInfo
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Abstract
本发明提供基于电气规则检测实现定位集成电路设计缺陷的方法，涉及缺陷定位技术领域，包括：获取目标集成电路进行电路设计的设计需求及对应电气规则标准，确定电路设计对应的第一电气规则；将第一电气规则输入到对应检测工具从而对目标集成电路进行实时检测：基于实时检测结果进行第一分析，从而确定目标集成电路的第一缺陷定位；获取第一缺陷定位对应设计信息，并基于设计信息及对应缺陷类型进行缺陷修正，从而对目标集成电路进行智能优化。通过对集成电路的需求进行分析，从而确定对应电气规则，并进行电路检验，确定缺陷定位，可以使得电气规则更能够满足目标集成电路的需求，从而能够更加精准的实现缺陷定位。
The present invention provides a method for locating integrated circuit design defects based on electrical rule detection, which relates to the field of defect location technology, including: obtaining the design requirements and corresponding electrical rule standards for circuit design of a target integrated circuit, and determining the first electrical rule corresponding to the circuit design; inputting the first electrical rule into a corresponding detection tool to perform real-time detection on the target integrated circuit: performing a first analysis based on the real-time detection result, thereby determining the first defect location of the target integrated circuit; obtaining the design information corresponding to the first defect location, and performing defect correction based on the design information and the corresponding defect type, thereby performing intelligent optimization on the target integrated circuit. By analyzing the requirements of the integrated circuit, thereby determining the corresponding electrical rules, and performing circuit inspection to determine the defect location, the electrical rules can be made more able to meet the requirements of the target integrated circuit, thereby enabling more accurate defect location.
Description
Technical Field
The invention relates to the technical field of defect positioning, in particular to a method for realizing positioning of integrated circuit design defects based on electrical rule detection.
Background
At present, integrated circuits are a core component of the information technology industry, a key force leading to a new technological and industrial revolution, and have become a strategic point in high-tech competition in all countries around the world. However, during the production process, defects often occur in the design of the integrated circuit due to some errors, and these defects may adversely affect the reliability and functionality of the integrated circuit, even seriously affect the performance and service life of the integrated circuit, so defect detection is an indispensable link in the production process of the integrated circuit.
However, existing defect inspection is often supported by manual bonding devices, which are time consuming, inefficient, and not prone to finding integrated circuit root cause problems, thereby limiting throughput.
Accordingly, the present invention provides a method for locating integrated circuit design defects based on electrical rule detection.
Disclosure of Invention
The invention provides a method for realizing positioning of integrated circuit design defects based on electrical rule detection, which is used for solving the problems of slower circuit design period caused by longer defect positioning verification time and wider positioning range in the prior art.
The invention provides a method for realizing positioning of integrated circuit design defects based on electrical rule detection, which comprises the following steps:
Step 1, obtaining the design requirement of a target integrated circuit for circuit design and a corresponding electrical rule standard, and determining a first electrical rule corresponding to the circuit design;
step 2, inputting a first electrical rule into a corresponding detection tool so as to detect the target integrated circuit in real time:
step 3, performing first analysis based on the real-time detection result so as to determine first defect positioning of the target integrated circuit;
and 4, acquiring design information corresponding to the first defect positioning, and performing defect correction based on the design information and the corresponding defect type, so as to intelligently optimize the target integrated circuit.
According to the invention, the first electrical rule corresponding to the circuit design is determined by acquiring the design requirement of the target integrated circuit for circuit design and the corresponding electrical rule standard, and the method comprises the following steps:
Step 11, obtaining the design requirement of the target integrated circuit for circuit design, thereby determining the circuit topology structure of the target integrated circuit, simultaneously obtaining the electrical rule standard for circuit design, and carrying out data processing to obtain a first reference data set;
step 12, data processing is carried out based on the external circuit environment of the target integrated circuit, preset circuit power consumption and preset circuit efficiency, so as to obtain a second reference data set;
and step 13, determining a first electrical rule of the target integrated circuit for circuit design based on the first reference data set and the second reference data set.
According to the invention, the first electrical rule is input into a corresponding detection tool so as to detect the design of the integrated circuit in real time, and the method comprises the following steps:
step 21, setting electrical rule detection attributes in corresponding detection tools based on the first electrical rules, and setting standard detection parameters and standard detection thresholds in the corresponding detection tools based on the design requirements of circuit design to obtain the first detection tools;
step 22, synthesizing to obtain a first detection set of the target integrated circuit based on the performance to be detected of the target integrated circuit;
Step 23, detecting each performance to be detected in the first detection set in real time based on the first detection tool, so as to obtain an initial detection result of the target integrated circuit;
step 24, performing simulation on the target integrated circuit based on a preset circuit simulation tool so as to obtain a simulation detection result of the target integrated circuit;
And step 25, synthesizing the initial detection result and the simulation detection result, and optimizing the result to obtain the real-time detection result of the target integrated circuit design.
The method for comprehensively obtaining the first detection set of the target integrated circuit based on the performance to be detected of the target integrated circuit comprises the following steps:
step 221, acquiring a real-time circuit operation image of a target integrated circuit, and extracting initial characteristic information of all pixel points in the real-time circuit operation image;
step 222, extracting detection related information from the initial characteristic information of each pixel point based on the performance type of the performance to be detected to obtain first characteristic information;
and 223, synthesizing the first characteristic information of each pixel point of the target integrated circuit to obtain a first detection set of the target integrated circuit.
Before the first analysis based on the real-time detection result, the method further comprises the step of judging the stability of the target integrated circuit, and specifically comprises the following steps:
step 01, randomly extracting any type of circuit simulation data of a target integrated circuit in any circuit section in a simulation detection result;
step 02, inputting circuit simulation data into the same coordinate system, and connecting each sub-simulation data to obtain a first simulation broken line;
Step 03, performing curve fitting on the first simulated broken line to obtain a first fitted curve, and analyzing the fluctuation condition of the first fitted curve;
if the curve fluctuation of the first fitting curve is smaller than the preset maximum fluctuation, judging that the target integrated circuit is stable;
otherwise, the target integrated circuit is judged to be unstable, and circuit early warning is directly carried out.
According to the invention, the first analysis is performed based on the real-time detection result, so as to determine the first defect positioning of the target integrated circuit, which comprises the following steps:
step 31, obtaining a first detection comparison table based on the real-time detection result and the standard detection parameters;
Step 32, comparing the real-time detection results of the corresponding performance types in the first detection comparison table with the standard detection parameters one by one, so as to determine a first comparison difference value;
step 33, comparing the first comparison difference value with the maximum error difference value of the corresponding performance type, thereby extracting the first comparison difference value larger than the maximum error difference value and obtaining a second comparison difference value set;
step 34, extracting real-time detection sub-results and corresponding performance types corresponding to the second comparison difference set from the first detection comparison table to obtain a first defect detection set;
Step 35, extracting the defect position and the defect influence range of each defect detection sub-result in the first defect detection set, and screening the defect reason of the corresponding difference value from the defect database based on the corresponding second comparison difference value, so as to obtain a second defect detection set by combining the corresponding defect position and the defect influence range;
wherein each subset in the second defect detection set comprises a defect position, a defect influence range and a corresponding defect reason of the same defect detection sub-result;
step 36, performing data processing and conversion based on the defect position, the defect influence range and the corresponding defect reason of each second defect detection subset in the second defect detection set, so as to determine a second defect index of each second defect detection subset;
step 37, sorting each second defect detection subset in the second defect detection set based on the second defect index to obtain a second ordered defect detection set;
step 38, obtaining an ordered first defect positioning set based on the defect positions corresponding to each second defect detection subset in the second ordered defect detection set.
According to the invention, the first defect positioning corresponding design information is obtained, and defect correction is performed based on the design information and the corresponding defect type, so that intelligent optimization is performed on the target integrated circuit, and the method comprises the following steps:
step 41, acquiring a second defect detection subset corresponding to the first defect positioning, so as to determine a defect correction scheme for the current first defect positioning by combining design information related to the corresponding defect position;
step 42, performing defect correction on the defect positions corresponding to the first defect positioning based on the defect correction scheme, and obtaining optimized detection parameters of the target integrated circuit for circuit design based on the defect correction results of all the first defect positioning;
And 43, optimizing the circuit design result of the target integrated circuit based on the optimized detection parameters.
After the intelligent optimization of the target integrated circuit is carried out, the method further comprises the steps of detecting again based on the optimized integrated circuit, including:
step 51, detecting the performance to be detected in the optimized integrated circuit in real time based on the first detection tool to obtain a second detection result of the target integrated circuit;
Step 54, analyzing the second detection result to determine whether the optimized integrated circuit design has a design defect;
If so, positioning the design defect and optimizing the integrated circuit again;
Otherwise, judging that the current integrated circuit has no design defect.
According to the method for realizing the positioning of the design defects of the integrated circuit based on the electrical rule detection, the requirements of the integrated circuit are analyzed, so that the corresponding electrical rule is determined, the circuit is tested, the defect positioning is determined, the electrical rule can meet the requirements of a target integrated circuit, and the defect positioning can be realized more accurately.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for implementing locating integrated circuit design defects based on electrical rule detection provided by an embodiment of the present invention;
FIG. 2 is a flow chart of real-time inspection of an integrated circuit design according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1:
The embodiment of the invention provides a method for realizing positioning of integrated circuit design defects based on electrical rule detection, which is shown in fig. 1 and comprises the following steps:
Step 1, obtaining the design requirement of a target integrated circuit for circuit design and a corresponding electrical rule standard, and determining a first electrical rule corresponding to the circuit design;
step 2, inputting a first electrical rule into a corresponding detection tool so as to detect the target integrated circuit in real time:
step 3, performing first analysis based on the real-time detection result so as to determine first defect positioning of the target integrated circuit;
and 4, acquiring design information corresponding to the first defect positioning, and performing defect correction based on the design information and the corresponding defect type, so as to intelligently optimize the target integrated circuit.
In this embodiment, the design requirements include functional requirements, power requirements, input/output requirements, anti-interference capability, reliability principles, specificity principles, correctness principles, and the like.
In this embodiment, the electrical rule standard refers to a standard for performing an electrical rule corresponding to a circuit design, and includes a device classification requirement standard, a drawing standardization standard, a wiring standardization standard, and the like.
In this embodiment, the first electrical rule refers to an electrical rule that meets the design requirement of the target integrated circuit and the electrical rule standard, for example, the first electrical rule includes that the minimum safety distance between devices is 6um, the minimum aperture is 3um, and so on.
In this embodiment, the first analysis refers to a process of comparing the real-time detection result with the standard detection parameters, and comparing the difference value of each sub-result, so as to perform a difference analysis on each difference value.
In this embodiment, the first defect localization means that a design defect is determined according to the analysis result, thereby localizing the defect.
In this embodiment, defect correction refers to performing defect correction on a defect located by a first defect according to design information corresponding to the first defect location and a corresponding defect type, where the defect correction method includes temperature compensation circuit correction, noise filtering, adjusting a transmission signal to be a differential signal, and the like, where defect correction schemes corresponding to different defect types are also different.
The technical scheme has the beneficial effects that the requirements of the integrated circuit are analyzed, so that the corresponding electrical rule is determined, the circuit is tested, the defect positioning is determined, the electrical rule can meet the requirements of the target integrated circuit, and the defect positioning can be realized more accurately.
Example 2:
Based on the embodiment 1, the method for obtaining the design requirement of the target integrated circuit for circuit design and the corresponding electrical rule standard, and determining the first electrical rule corresponding to the circuit design includes:
Step 11, obtaining the design requirement of the target integrated circuit for circuit design, thereby determining the circuit topology structure of the target integrated circuit, simultaneously obtaining the electrical rule standard for circuit design, and carrying out data processing to obtain a first reference data set;
step 12, data processing is carried out based on the external circuit environment of the target integrated circuit, preset circuit power consumption and preset circuit efficiency, so as to obtain a second reference data set;
and step 13, determining a first electrical rule of the target integrated circuit for circuit design based on the first reference data set and the second reference data set.
In this embodiment, the design requirements include functional requirements, power requirements, input/output requirements, anti-interference capability, reliability principles, specificity principles, correctness principles, and the like.
In this embodiment, the circuit topology refers to the manner and arrangement order of interconnections between the elements in the circuit, which are determined according to the design requirements of the target integrated circuit.
In this embodiment, the electrical rule standard refers to an electrical rule that meets the target integrated circuit, which is determined according to the design requirement of the target integrated circuit and the electrical rule standard, for example, the first electrical rule includes that the minimum safety distance between devices is 6um, the minimum aperture is 3um, and so on.
In this embodiment, the first reference data set refers to a data set obtained by performing data processing on connection data in a circuit topology structure and rule data in an electrical rule standard.
In the embodiment, the external environment of the circuit refers to an external environment of the target integrated circuit for circuit operation, wherein the external environment of the circuit comprises environmental factors such as ambient temperature, ambient humidity, external electromagnetic field and the like which influence the operation of the target integrated circuit, and the preset circuit power consumption and the preset circuit efficiency are determined according to the circuit simulation result of the target integrated circuit.
In this embodiment, the second reference data set is a data set obtained by performing data processing on a circuit external environment, preset circuit power consumption and preset circuit efficiency of the target integrated circuit.
In this embodiment, the first electrical rule refers to an electrical rule that meets the design requirement of the target integrated circuit and the electrical rule standard, for example, the first electrical rule includes that the minimum safety distance between devices is 6um, the minimum aperture is 3um, and so on.
The technical scheme has the beneficial effects that the design requirement of the circuit design and the electrical rule standard are analyzed, so that the electrical rule which is more matched with the integrated circuit is obtained, and the defect positioning of the integrated circuit is more accurate.
Example 3:
Based on the embodiment 2, the first electrical rule is input to the corresponding inspection tool to inspect the integrated circuit design in real time, as shown in fig. 2, including:
step 21, setting electrical rule detection attributes in corresponding detection tools based on the first electrical rules, and setting standard detection parameters and standard detection thresholds in the corresponding detection tools based on the design requirements of circuit design to obtain the first detection tools;
step 22, synthesizing to obtain a first detection set of the target integrated circuit based on the performance to be detected of the target integrated circuit;
Step 23, detecting each performance to be detected in the first detection set in real time based on the first detection tool, so as to obtain an initial detection result of the target integrated circuit;
step 24, performing simulation on the target integrated circuit based on a preset circuit simulation tool so as to obtain a simulation detection result of the target integrated circuit;
And step 25, synthesizing the initial detection result and the simulation detection result, and optimizing the result to obtain the real-time detection result of the target integrated circuit design.
In the embodiment, the detection attribute refers to a detection attribute for detecting the electrical rule, which is set in the corresponding detection tool according to the first electrical rule, wherein the detection attribute comprises an aperture, a minimum safety distance, copper-clad settings and the like.
In this embodiment, the standard detection parameter and the standard detection threshold refer to a standard detection parameter and a standard detection threshold corresponding to the electrical rule detection of the integrated circuit of the same type as the target integrated circuit.
In this embodiment, the first inspection tool is an inspection tool obtained after setting standard inspection parameters and standard inspection thresholds in the corresponding inspection tools based on design requirements of circuit design.
In this embodiment, the performance to be detected includes integration level, operating voltage, operating temperature, power consumption, clock frequency, reliability, logic function, packaging mode, and the like.
In this embodiment, the first detection set refers to a detection data set obtained by integrating the performance to be detected of the target integrated circuit.
In this embodiment, the initial detection result refers to real-time detection data obtained after the performance to be detected of the target integrated circuit is detected according to the first detection tool.
In this embodiment, the simulation test result refers to a simulation result obtained by performing simulation on the target integrated circuit according to a preset circuit simulation tool.
In this embodiment, the real-time detection result is obtained by integrating the initial detection result with the simulation detection result and optimizing the result.
The technical scheme has the beneficial effects that the integrated circuit design is detected based on the electrical rule, and a more accurate detection result can be obtained by combining the detection result of simulation, so that the defect positioning of the design is more accurate and effective.
Example 4:
based on embodiment 3, the first detection set of the target integrated circuit is obtained by integrating the to-be-detected performances of the target integrated circuit, including:
step 221, acquiring a real-time circuit operation image of a target integrated circuit, and extracting initial characteristic information of all pixel points in the real-time circuit operation image;
step 222, extracting detection related information from the initial characteristic information of each pixel point based on the performance type of the performance to be detected to obtain first characteristic information;
and 223, synthesizing the first characteristic information of each pixel point of the target integrated circuit to obtain a first detection set of the target integrated circuit.
In this embodiment, the real-time circuit operation image refers to a real-time operation image of the target integrated circuit for circuit operation.
In this embodiment, the initial feature information refers to feature information of each pixel point in the running image of the real-time circuit.
In this embodiment, the performance type refers to a type corresponding to the integration level, the operating voltage, the operating temperature, the power consumption, the clock frequency, the reliability, the logic function, and the packaging mode waiting for detecting the performance.
In this embodiment, the first feature information is obtained after extracting, from the initial feature information, feature information corresponding to the performance to be detected, which corresponds to the type according to the performance type.
In this embodiment, the first detection set refers to a detection data set obtained by integrating the first feature information of the target integrated circuit.
The technical scheme has the beneficial effects that the information extraction is carried out on the real-time circuit operation image of the integrated circuit design, and the information extraction result is detected based on the electrical rule, so that a more accurate detection result can be obtained by combining the detection result of simulation, and the design defect positioning is more accurate and effective.
Example 5:
based on the embodiment 3, the determination of the stability of the target integrated circuit specifically includes:
step 01, randomly extracting any type of circuit simulation data of a target integrated circuit in any circuit section in a simulation detection result;
step 02, inputting circuit simulation data into the same coordinate system, and connecting each sub-simulation data to obtain a first simulation broken line;
Step 03, performing curve fitting on the first simulated broken line to obtain a first fitted curve, and analyzing the fluctuation condition of the first fitted curve;
if the curve fluctuation of the first fitting curve is smaller than the preset maximum fluctuation, judging that the target integrated circuit is stable;
otherwise, the target integrated circuit is judged to be unstable, and circuit early warning is directly carried out.
In this embodiment, the circuit simulation data refers to any type of simulation data in any circuit section in the simulation test result.
In this embodiment, the first analog polyline refers to an analog polyline obtained by inputting circuit analog data into the same coordinate system and performing data connection on adjacent analog data.
In this embodiment, the first fitting curve refers to a fitting curve obtained by fitting the first simulated polyline according to a curve fitting manner.
In this embodiment, the preset maximum fluctuation is determined according to the maximum instability that the target price integrated circuit can withstand, where the preset maximum fluctuation is determined according to the maximum slope difference between each slope in the first fitting curve, and the fluctuation range of the preset maximum fluctuation is between (0,0.1).
The technical scheme has the beneficial effects that the stability of the integrated circuit is judged, so that the part with the stability higher than the preset maximum fluctuation is pre-warned, the analysis data for detecting and analyzing the integrated circuit can be reduced, and the analysis efficiency is improved.
Example 6:
based on the embodiment 5, a first analysis is performed based on the real-time detection result to determine a first defect location of the target integrated circuit, including:
step 31, obtaining a first detection comparison table based on the real-time detection result and the standard detection parameters;
Step 32, comparing the real-time detection results of the corresponding performance types in the first detection comparison table with the standard detection parameters one by one, so as to determine a first comparison difference value;
step 33, comparing the first comparison difference value with the maximum error difference value of the corresponding performance type, thereby extracting the first comparison difference value larger than the maximum error difference value and obtaining a second comparison difference value set;
step 34, extracting real-time detection sub-results and corresponding performance types corresponding to the second comparison difference set from the first detection comparison table to obtain a first defect detection set;
Step 35, extracting the defect position and the defect influence range of each defect detection sub-result in the first defect detection set, and screening the defect reason of the corresponding difference value from the defect database based on the corresponding second comparison difference value, so as to obtain a second defect detection set by combining the corresponding defect position and the defect influence range;
wherein each subset in the second defect detection set comprises a defect position, a defect influence range and a corresponding defect reason of the same defect detection sub-result;
step 36, performing data processing and conversion based on the defect position, the defect influence range and the corresponding defect reason of each second defect detection subset in the second defect detection set, so as to determine a second defect index of each second defect detection subset;
step 37, sorting each second defect detection subset in the second defect detection set based on the second defect index to obtain a second ordered defect detection set;
step 38, obtaining an ordered first defect positioning set based on the defect positions corresponding to each second defect detection subset in the second ordered defect detection set.
In this embodiment, the first detection comparison table is obtained by filling the real-time detection result and the standard detection parameter into the same table, where the first column of the first detection comparison table is a parameter type, the second column is a real-time detection result, the third column is a standard detection parameter, and each row represents a sub-parameter of the same performance type.
In this embodiment, the first comparison value refers to a comparison difference determined by comparing the real-time detection result of the same row in the first detection comparison table with the standard detection parameter.
In this embodiment, the maximum error value refers to the maximum error value between the real-time detection result and the standard detection parameter, where the performance types are different, and the corresponding maximum error values are also different.
In this embodiment, the second comparison difference set refers to a comparison difference set obtained by extracting a first comparison difference value having a first comparison difference value greater than a maximum error-prone difference value of a corresponding type.
In this embodiment, the first defect detection set is obtained by extracting a real-time detection sub-result and a corresponding detection type corresponding to the second comparison difference set from the first detection comparison table.
In this embodiment, the defect position refers to a defect position corresponding to the defect detection sub-result, and the defect influence range is a defect influence range of each defect detection sub-result determined according to a defect cause and the defect position, where the defect cause includes a power supply capability problem, an impedance matching problem, a start-up impact problem, an interface design problem, a power control problem, a layout problem, a signal integrity problem, and the like.
In this embodiment, each subset of the second defect detection sets includes a defect location, a defect influence range, and a corresponding defect cause of the same defect detection sub-result.
In this embodiment, the second defect index refers to the influence of each defect detection sub-result comprehensively determined according to the defect position, the defect term influence range, the defect cause, and the like on the circuit design of the target integrated circuit, where the larger the influence is, the larger the second defect index is, for example, the second defect index corresponding to the interface design problem is larger than the second defect index corresponding to the signal integrity problem.
In this embodiment, the larger the second defect index, the more serious the defect corresponding to the defect position.
In this embodiment, the second ordered defect detection set refers to a detection set obtained by sorting each subset of the second defect detection sets according to the size of the second defect index corresponding to each defect detection sub-result.
In this embodiment, the first defect locating set refers to determining design defects according to analysis results, so as to locate the defects.
The technical scheme has the beneficial effects that the defect positioning is determined by comparing and analyzing the circuit detection result and the standard detection result, so that the defect positioning can be realized more accurately.
Example 7:
Based on embodiment 6, the intelligent optimization of the target integrated circuit includes:
step 41, acquiring a second defect detection subset corresponding to the first defect positioning, so as to determine a defect correction scheme for the current first defect positioning by combining design information related to the corresponding defect position;
step 42, performing defect correction on the defect positions corresponding to the first defect positioning based on the defect correction scheme, and obtaining optimized detection parameters of the target integrated circuit for circuit design based on the defect correction results of all the first defect positioning;
And 43, optimizing the circuit design result of the target integrated circuit based on the optimized detection parameters.
In this embodiment, the second defect detection subset refers to a defect detection subset that includes a defect position, a defect influence range, and a corresponding defect cause of the same defect detection sub-result in the second defect detection set.
In this embodiment, the defect correction scheme refers to a defect correction scheme for determining the current first defect location according to the design information related to the defect position corresponding to the second defect detection subset, where the defect correction scheme includes temperature compensation circuit correction, noise filtering, and adjusting the transmission signal to be a differential signal.
In this embodiment, defect correction refers to performing defect correction on a defect located by a first defect according to design information corresponding to the first defect location and a corresponding defect type, where the defect correction method includes temperature compensation circuit correction, noise filtering, adjusting a transmission signal to be a differential signal, and the like, where defect correction schemes corresponding to different defect types are also different.
In this embodiment, the optimized detection parameter refers to a detection parameter for performing circuit design on the target integrated circuit obtained based on the defect correction result of all the first defect locations after performing defect correction on the defect location corresponding to the first defect location based on the defect correction scheme.
The technical scheme has the beneficial effects that the defect correction is carried out on the defect at the corresponding position of the defect positioning, so that the working efficiency of the target integrated circuit is higher, and the working capacity of the integrated circuit is improved.
Example 8:
based on embodiment 7, re-inspection based on the optimized integrated circuit is performed, including:
step 51, detecting the performance to be detected in the optimized integrated circuit in real time based on the first detection tool to obtain a second detection result of the target integrated circuit;
Step 54, analyzing the second detection result to determine whether the optimized integrated circuit design has a design defect;
If so, positioning the design defect and optimizing the integrated circuit again;
Otherwise, judging that the current integrated circuit has no design defect.
In this embodiment, the second detection result refers to detection data obtained by detecting the performance to be detected in the optimized integrated circuit in real time based on the first detection tool.
The technical scheme has the beneficial effects that whether the design defect exists in the optimization result of the target integrated circuit or not can be determined by detecting the optimized integrated circuit, so that the detection efficiency of defect positioning detection is improved.
The foregoing embodiments are merely for illustrating the technical solution of the present invention, but not for limiting the same, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present invention in essence.
Claims (4)
1. The method for realizing positioning of the design defect of the integrated circuit based on the electrical rule detection is characterized by comprising the following steps:
Step 1, obtaining the design requirement of a target integrated circuit for circuit design and a corresponding electrical rule standard, and determining a first electrical rule corresponding to the circuit design;
step 2, inputting a first electrical rule into a corresponding detection tool so as to detect the target integrated circuit in real time:
step 3, performing first analysis based on the real-time detection result so as to determine first defect positioning of the target integrated circuit;
Step 4, obtaining design information corresponding to the first defect positioning, and performing defect correction based on the design information and the corresponding defect type, so as to perform intelligent optimization on the target integrated circuit;
the method for determining the first electrical rule corresponding to the circuit design includes the steps of:
Step 11, obtaining the design requirement of the target integrated circuit for circuit design, thereby determining the circuit topology structure of the target integrated circuit, simultaneously obtaining the electrical rule standard for circuit design, and carrying out data processing to obtain a first reference data set;
step 12, data processing is carried out based on the external circuit environment of the target integrated circuit, preset circuit power consumption and preset circuit efficiency, so as to obtain a second reference data set;
step 13, determining a first electrical rule of circuit design of the target integrated circuit based on the first reference data set and the second reference data set;
wherein inputting the first electrical rule to the corresponding inspection tool to inspect the integrated circuit design in real time comprises:
step 21, setting electrical rule detection attributes in corresponding detection tools based on the first electrical rules, and setting standard detection parameters and standard detection thresholds in the corresponding detection tools based on the design requirements of circuit design to obtain the first detection tools;
step 22, synthesizing to obtain a first detection set of the target integrated circuit based on the performance to be detected of the target integrated circuit;
Step 23, detecting each performance to be detected in the first detection set in real time based on the first detection tool, so as to obtain an initial detection result of the target integrated circuit;
step 24, performing simulation on the target integrated circuit based on a preset circuit simulation tool so as to obtain a simulation detection result of the target integrated circuit;
Step 25, synthesizing the initial detection result and the simulation detection result, and optimizing the result to obtain a real-time detection result of the target integrated circuit design;
the method for comprehensively obtaining the first detection set of the target integrated circuit based on the performance to be detected of the target integrated circuit comprises the following steps:
step 221, acquiring a real-time circuit operation image of a target integrated circuit, and extracting initial characteristic information of all pixel points in the real-time circuit operation image;
step 222, extracting detection related information from the initial characteristic information of each pixel point based on the performance type of the performance to be detected to obtain first characteristic information;
Step 223, synthesizing the first characteristic information of each pixel point of the target integrated circuit to obtain a first detection set of the target integrated circuit;
wherein performing a first analysis based on the real-time detection result to determine a first defect location of the target integrated circuit comprises:
step 31, obtaining a first detection comparison table based on the real-time detection result and the standard detection parameters;
Step 32, comparing the real-time detection results of the corresponding performance types in the first detection comparison table with the standard detection parameters one by one, so as to determine a first comparison difference value;
step 33, comparing the first comparison difference value with the maximum error difference value of the corresponding performance type, thereby extracting the first comparison difference value larger than the maximum error difference value and obtaining a second comparison difference value set;
step 34, extracting real-time detection sub-results and corresponding performance types corresponding to the second comparison difference set from the first detection comparison table to obtain a first defect detection set;
Step 35, extracting the defect position and the defect influence range of each defect detection sub-result in the first defect detection set, and screening the defect reason of the corresponding difference value from the defect database based on the corresponding second comparison difference value, so as to obtain a second defect detection set by combining the corresponding defect position and the defect influence range;
wherein each subset in the second defect detection set comprises a defect position, a defect influence range and a corresponding defect reason of the same defect detection sub-result;
step 36, performing data processing and conversion based on the defect position, the defect influence range and the corresponding defect reason of each second defect detection subset in the second defect detection set, so as to determine a second defect index of each second defect detection subset;
step 37, sorting each second defect detection subset in the second defect detection set based on the second defect index to obtain a second ordered defect detection set;
step 38, obtaining an ordered first defect positioning set based on the defect positions corresponding to each second defect detection subset in the second ordered defect detection set.
2. The method for locating integrated circuit design defects based on electrical rule detection of claim 1, further comprising determining stability of the target integrated circuit prior to the first analysis based on the real-time detection result, specifically comprising:
step 01, randomly extracting any type of circuit simulation data of a target integrated circuit in any circuit section in a simulation detection result;
step 02, inputting circuit simulation data into the same coordinate system, and connecting each sub-simulation data to obtain a first simulation broken line;
Step 03, performing curve fitting on the first simulated broken line to obtain a first fitted curve, and analyzing the fluctuation condition of the first fitted curve;
if the curve fluctuation of the first fitting curve is smaller than the preset maximum fluctuation, judging that the target integrated circuit is stable;
otherwise, the target integrated circuit is judged to be unstable, and circuit early warning is directly carried out.
3. The method for implementing integrated circuit design defect localization based on electrical rule detection of claim 1, wherein obtaining first defect localization corresponding design information and performing defect correction based on the design information and a corresponding defect type to perform intelligent optimization on the target integrated circuit comprises:
step 41, acquiring a second defect detection subset corresponding to the first defect positioning, so as to determine a defect correction scheme for the current first defect positioning by combining design information related to the corresponding defect position;
step 42, performing defect correction on the defect positions corresponding to the first defect positioning based on the defect correction scheme, and obtaining optimized detection parameters of the target integrated circuit for circuit design based on the defect correction results of all the first defect positioning;
And 43, intelligently optimizing the circuit design result of the target integrated circuit based on the optimized detection parameters.
4. The method for implementing integrated circuit design defect localization based on electrical rule detection as set forth in claim 3, further comprising, after intelligent optimization of the target integrated circuit, re-detecting based on the optimized integrated circuit, comprising:
step 51, detecting the performance to be detected in the optimized integrated circuit in real time based on the first detection tool to obtain a second detection result of the target integrated circuit;
Step 54, analyzing the second detection result to determine whether the optimized integrated circuit design has a design defect;
If so, positioning the design defect and optimizing the integrated circuit again;
Otherwise, judging that the current integrated circuit has no design defect.
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