CN118629999A - Semiconductor device and method for forming the same - Google Patents

Abstract

Embodiments include devices. The device includes: an interposer; a package substrate; and conductive connectors that bond the package substrate to the interposer. Each of the conductive connectors has a convex sidewall. A first subset of the conductive connectors is disposed in a center of the package substrate in a top view. A second subset of the conductive connectors is disposed in an edge/corner of the package substrate in a top view. Each of the second subset of the conductive connectors has a greater height than each of the first subset of the conductive connectors. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method for forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background Art

The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative semiconductor die packaging technologies has emerged.

Summary of the invention

Some embodiments of the present application provide a semiconductor device, including: an interposer; a packaging substrate; and conductive connectors, joining the packaging substrate to the interposer, each of the conductive connectors having a convex sidewall, a first subset of the conductive connectors being arranged in the center of the packaging substrate in a top view, a second subset of the conductive connectors being arranged in an edge/corner of the packaging substrate in the top view, each of the second subset of the conductive connectors having a height greater than that of each of the first subset of the conductive connectors.

Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first reflowable connector on a packaging substrate, the first reflowable connector being disposed in a first region of the packaging substrate; after forming the first reflowable connector, forming a second reflowable connector on the packaging substrate, the second reflowable connector being disposed in a second region of the packaging substrate, the second reflowable connector having a height greater than that of the first reflowable connector; forming a reflowable layer on an interposer; making each of the first reflowable connector and the second reflowable connector contact the corresponding reflowable layer; and reflowing the first reflowable connector, the second reflowable connector, and the reflowable layer to bond the packaging substrate to the interposer.

Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first reflowable connector on a first subset of bonding pads of a packaging substrate, the first reflowable connector being disposed in the center of the packaging substrate in a top view; forming a second reflowable connector on a second subset of the bonding pads of the packaging substrate, the second reflowable connector being disposed in an edge/corner of the packaging substrate in the top view, the second reflowable connector having a height greater than that of the first reflowable connector; after forming the first reflowable connector and the second reflowable connector, placing the packaging substrate on an interposer; and reflowing the first reflowable connector and the second reflowable connector to bond the packaging substrate to the interposer.

BRIEF DESCRIPTION OF THE DRAWINGS

When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

FIG. 1 is a cross-sectional view of an integrated circuit die.

2A-2B are cross-sectional views of a die stack.

3-14 are views of intermediate stages in the fabrication of an integrated circuit package, according to some embodiments.

15-19 are schematic cross-sectional views of a process for bonding a package substrate to an interposer wafer in accordance with some embodiments.

20A-20B are top views of integrated circuit packages according to some embodiments.

21-22 are schematic cross-sectional views of a process for bonding a package substrate to an interposer wafer in accordance with some embodiments.

23A-23B are top views of integrated circuit packages according to some embodiments.

24-25 are schematic cross-sectional views of a process for bonding a package substrate to an interposer wafer in accordance with some embodiments.

26A-26B are top views of integrated circuit packages according to some embodiments.

27-28 are schematic cross-sectional views of a process for bonding a package substrate to an interposer wafer in accordance with some embodiments.

29A-29B are top views of integrated circuit packages according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and/or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

According to various embodiments, a package substrate is joined to an interposer wafer (e.g., a wafer including an interposer) using conductive connectors having different heights. Specifically, conductive connectors in regions of the package substrate having a large amount of warpage have a greater height than conductive connectors in regions of the package substrate having a small amount of warpage. Forming conductive connectors (e.g., solder connectors) having different heights may reduce the effects of warpage during joining of the package substrate to the interposer wafer. Thus, the quality of the conductive connectors may be improved, such as by reducing the risk of forming a cold solder joint and/or reducing the risk of solder necking.

FIG. 1 is a cross-sectional view of an integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC) die, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. The integrated circuit die 50 may be formed in a wafer, which may include different die regions, and the die regions are divided in subsequent steps to form multiple integrated circuit dies 50. The integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, a die connector 56, and a dielectric layer 58.

The semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the surface facing upward in FIG. 1 ) and an inactive surface (e.g., the surface facing downward in FIG. 1 ). The device is located at the active surface of the semiconductor substrate 52. The device may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. The inactive surface may be free of devices.

The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layer include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. The metallization layer may include conductive vias and/or wires to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The metallization layer of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

Die connector 56 is located at front side 50F of integrated circuit die 50. Die connector 56 may be a conductive post, pad, etc. that makes an external connection. Die connector 56 is located in and/or on interconnect structure 54. For example, die connector 56 may be part of an upper metallization layer of interconnect structure 54. Die connector 56 may be formed of a metal such as copper, aluminum, etc., and may be formed by, for example, plating, etc.

Optionally, during the formation of the integrated circuit die 50, a solder area (not shown separately) can be provided on the die connector 56. The solder area can be used to implement a chip probe (CP) test on the integrated circuit die 50. For example, the solder area can be a solder ball, a solder bump, etc., which is used to attach a chip probe to the die connector 56. The chip probe test can be implemented on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 (which is a KGD) that undergoes subsequent processing is packaged, and the die that does not pass the chip probe test is not packaged. After the test, the solder area can be removed.

The dielectric layer 58 is located at the front side 50F of the integrated circuit die 50. The dielectric layer 58 is located in and/or on the interconnect structure 54. For example, the dielectric layer 58 can be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 laterally seals the die connector 56. The dielectric layer 58 can be an oxide, a nitride, a carbide, a polymer, etc., or a combination thereof. The dielectric layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. Initially, the dielectric layer 58 can bury the die connector 56 so that the top surface of the dielectric layer 58 is located above the top surface of the die connector 56. The die connector 56 can be exposed through the dielectric layer 58. Exposing the die connector 56 can remove any solder area that may be present on the die connector 56. The removal process can be applied to each layer to remove excess material above the die connector 56. The removal process can be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. After the planarization process, the top surfaces of the die connect 56 and the dielectric layer 58 are coplanar (within process variations) and exposed at the front side 50F of the integrated circuit die 50 .

2A-2B are cross-sectional views of die stacks 60A, 60B, respectively. Die stacks 60A, 60B may each have a single function (e.g., a logic device, a memory die, etc.), or may have multiple functions. In some embodiments, die stack 60A is a logic device such as a system on an integrated chip (SoIC) device, and die stack 60B is a memory device such as a high bandwidth memory (HBM) device.

As shown in FIG. 2A , the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to the memory die and converts commands between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded so that the active surfaces face each other (e.g., "face-to-face" bonding). A conductive via 62 may be formed through one of the integrated circuit dies 50 so that an external connection to the die stack 60A may be made. The conductive via 62 may be a through substrate via (TSV), such as a through silicon via, etc. In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., an interface die). The conductive via 62 extends through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54.

2B , the die stack 60B is a stacked device including a plurality of semiconductor substrates 52. For example, the die stack 60B may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) device, a high bandwidth memory (HBM) device, etc. Each of the semiconductor substrates 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected by conductive vias 62, such as TSVs.

3 to 14 are views of intermediate stages in the manufacture of an integrated circuit package 200 according to some embodiments. A plurality of package regions 100P are shown, and an integrated circuit package 200 is formed in each of the package regions 100P. An interposer wafer 100 is formed. The interposer wafer 100 includes an interposer in each package region 100P. An integrated circuit device 202 is bonded to the interposer wafer 100. The interposer in each package region 100P may include an interconnect die 120 for interconnecting the integrated circuit devices 202 in the corresponding package region 100P. Then, a package substrate 220 is mounted to the interposer wafer 100. Specifically, the package substrate 220 is attached in each package region 100P. The package region 100P is then segmented to form integrated circuit packages 200, each of which includes segmented portions of the interposer wafer 100 (e.g., an interposer) and the package substrate 220. In an embodiment, the integrated circuit package 200 is a chip on wafer on a substrate. Packages such as CoWoS-L packages, but it should be understood that embodiments may be applied to other 3DIC packages.

3 , a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102 . The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 102 at the same time.

The release layer 104 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be flush and may have a high degree of planarity.

In FIG. 4 , a through hole 106 is formed above the carrier substrate 102 (e.g., on the release layer 104). As an example of forming the through hole 106, a seed layer (not shown) is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sublayers formed of different materials. In an embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD, etc. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 106. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or chemical plating, etc. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. The portion of the photoresist and the seed layer on which no conductive material is formed is removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material form the via 106.

The interconnect die 120 is attached to the carrier substrate 102. Each interconnect die 120 may be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. In the illustrated embodiment, one interconnect die 120 is attached in each package region 100P. It should be understood that any desired number of interconnect dies 120 may be placed in the package region 100P. The interconnect die 120 may be placed by, for example, a pick-and-place process. Each interconnect die 120 includes a substrate 122, wherein a conductive component is formed in and/or on the substrate 122. The substrate 122 may include a semiconductor substrate, one or more dielectric layers, etc. In addition, each interconnect die 120 may include a substrate through hole (TSV) 124 extending into or through the substrate 122, and may be coupled to the conductive component of the interconnect die 120. In the illustrated embodiment, the TSV 124 is exposed at the back side of the interconnect die 120. In another embodiment, the substrate 122 may cover the TSV 124 at the back side of the interconnect die 120.

In the embodiment where the interconnection die 120 is an LSI, the interconnection die 120 can be a bridge structure including a die bridge 126. The die bridge 126 can be a metallization layer formed in and/or on, for example, a substrate 122, and is used to interconnect integrated circuit devices (described later) to each other. Therefore, LSI can be used to directly connect integrated circuit devices and allow communication between integrated circuit devices. In such an embodiment, the interconnection die 120 can be placed in an area between the integrated circuit devices that are subsequently joined, so that each of the interconnection die 120 overlaps with the integrated circuit device above. In some embodiments, the interconnection die 120 can also include a logic device and/or a memory device. The interconnection die 120 is attached to the carrier substrate 102 so that the die bridge 126 faces the carrier substrate 102.

In FIG5 , an encapsulant 130 is formed on and around the various components. After formation, the encapsulant 130 seals the through-hole 106 and the interconnect die 120. The encapsulant 130 may be a molding compound, an epoxy resin, or the like. The encapsulant 130 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102, thereby burying or covering the through-hole 106 and/or the interconnect die 120. The encapsulant 130 is also formed in the gap region between the interconnect die 120 and the through-hole 106. The encapsulant 130 may be applied in a liquid or semi-liquid form and then subsequently cured.

A planarization process may optionally be performed on the encapsulant 130 to expose the vias 106 and the TSVs 124. The planarization process may also remove material of the vias 106, the substrate 122, and/or the TSVs 124 until the TSVs 124 and the vias 106 are exposed. The top surfaces of the vias 106, the substrate 122, the TSVs 124, and the encapsulant 130 are substantially coplanar (within process variations) after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, planarization may be omitted, for example, if the vias 106 and/or the TSVs 124 are already exposed.

6, a front side redistribution structure 140 is formed on the top surface of the encapsulant 130, the vias 106, and the interconnect die 120 (e.g., substrate 122). The front side redistribution structure 140 includes a dielectric layer 142 and a metallization layer 144 (sometimes referred to as a redistribution layer or a redistribution line) between the dielectric layers 142. Thus, the front side redistribution structure 140 includes a plurality of metallization layers 144 separated from each other by respective dielectric layers 142. The metallization layers 144 of the front side redistribution structure 140 are connected to the vias 106 and the interconnect die 120 (e.g., TSV 124).

In some embodiments, dielectric layer 142 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, etc., which can be patterned using a photolithographic mask. In other embodiments, dielectric layer 142 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, PSG; etc. The dielectric layer 142 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After each dielectric layer 142 is formed, it is then patterned to expose the underlying conductive features, such as portions of the underlying vias 106, TSVs 124, and/or metallization layers 144. Patterning may be implemented by an acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 142 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 142 is a photosensitive material, the dielectric layer 142 may be developed after exposure.

Each of the metallization layers 144 includes a conductive via and/or a conductor. The conductive via extends through the corresponding dielectric layer 142, and the conductor extends along the corresponding dielectric layer 142. As an example of forming the metallization layer 144, a seed layer (not shown) is formed above the corresponding lower component. For example, the seed layer can be formed on the corresponding dielectric layer 142 and in an opening through the corresponding dielectric layer 142. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above the titanium layer and the titanium layer. The seed layer can be formed using a deposition process, such as PVD, etc. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 144. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from a seed layer. The conductive material can include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material form a metallization layer 144 for one level of the front side redistribution structure 140.

Front side redistribution structure 140 is shown as an example. More or fewer dielectric layers 142 and metallization layers 144 than shown may be formed by repeating or omitting previously described steps.

An under bump metal (UBM) 146 is formed for external connection to the front side redistribution structure 140. The UBM 146 has a bump portion located on and extending along the main surface of the upper dielectric layer 142 of the front side redistribution structure 140, and has a through hole portion extending through the upper dielectric layer 142 of the front side redistribution structure 140 to physically and electrically couple the upper metallization layer 144 of the front side redistribution structure 140. Thus, the UBM 146 is electrically connected to the through via 106 and the interconnect die 120 (e.g., TSV 124). The UBM 146 may be formed of the same material as the metallization layer 144 and may be formed by a similar process as the metallization layer 144. In some embodiments, the UBM 146 has a different size than the metallization layer 144.

7 , carrier substrate peeling is performed to separate (or “peel”) carrier substrate 102 from interposer wafer 100. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed.

In FIG8 , the interposer wafer 100 is flipped over to prepare for processing the back side of the interposer wafer 100. The interposer wafer 100 can be placed on a carrier substrate 152 or other suitable support structure for subsequent processing. In some embodiments, the carrier substrate 152 is a substrate such as a bulk semiconductor or a glass substrate. The carrier substrate 152 is attached to the front side of the interposer wafer 100. The carrier substrate 152 can be attached by a bonding layer (not shown separately), which can be removed from the structure together with the carrier substrate 152 after processing. In some embodiments, the bonding layer includes an oxide layer, such as a silicon oxide layer. In some embodiments, the bonding layer includes an adhesive, such as a suitable epoxy resin, etc.

In some embodiments, a buffer layer 154 is formed between the carrier substrate 152 and the front side redistribution structure 140. The buffer layer 154 may be formed of an insulating material, such as silicon oxide, silicon nitride, a molding compound, an epoxy resin, etc. The buffer layer 154 covers and protects the UBM 146. A planarization process may be optionally performed on the buffer layer 154 to form a planar surface to which the carrier substrate 152 may be bonded. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc.

9, a backside redistribution structure 160 is formed on the bottom surface of the encapsulant 130, the vias 106, and the interconnect die 120 (e.g., the substrate 122). The backside redistribution structure 160 includes a dielectric layer 162 and a metallization layer 164 in a similar manner to the frontside redistribution structure 140. The backside redistribution structure 160 can be formed by a process similar to the frontside redistribution structure 140.

The metallization layer 164 is connected to the vias 106 and the interconnect die 120 (e.g., the die bridge 126). In addition, the metallization layer 164 may include die connectors to which the integrated circuit device will be bonded. The backside redistribution structure 160 is shown as an example. More or fewer dielectric layers 162 and metallization layers 164 than shown may be formed in the backside redistribution structure 160.

In FIG. 10 , the integrated circuit device 202 is bonded to the back side of the interposer wafer 100 (e.g., bonded to the back side redistribution structure 160). A plurality of integrated circuit devices 202 are placed adjacent to each other in each package region 100P. The integrated circuit devices 202 in each package region 100P may include a logic device 202A and a memory device 202B. The logic device 202A and the memory device 202B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the logic device 202A may be formed by a more advanced process node than the memory device 202B.

Each logic device 202A may be a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), a microcontroller, etc. The logic device 202A may be an integrated circuit die (similar to the integrated circuit die 50 described with respect to FIG. 1 ) or may be a die stack (similar to the die stack 60A described with respect to FIG. 2A ). In some embodiments, the logic device 202A is an integrated circuit die, such as a system on chip (SoC) die. In some embodiments, the logic device 202A is a die stack, such as a system on integrated chip (SoIC) device.

Each memory device 202B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The memory device 202B may be an integrated circuit die (similar to the integrated circuit die 50 described with respect to FIG. 1 ) or may be a die stack (similar to the die stack 60B described with respect to FIG. 2B ). In some embodiments, the memory device 202B is a die stack, such as a high bandwidth memory (HBM) device.

In the illustrated embodiment, the integrated circuit device 202 is bonded to the interposer wafer 100 using solder bonding, such as using conductive connectors 204. The integrated circuit device 202 can be placed on the backside redistribution structure 160 using, for example, a pick-and-place tool. The conductive connector 204 can be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 204 is formed by initially forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the conductive connector 204 into a desired bump shape. Bonding the integrated circuit device 202 to the interposer wafer 100 can include placing the integrated circuit device 202 on the interposer wafer 100 and reflowing the conductive connector 204. The die connector 206 is located at the front side of the integrated circuit device 202. The conductive connectors 204 form joints between the die connectors 206 of the integrated circuit devices 202 and the die connectors of the backside redistribution structure 160 , thereby electrically connecting the interposer of the interposer wafer 100 to the integrated circuit devices 202 .

An underfill 210 may be formed around the conductive connectors 204 and between the interposer wafer 100 and the integrated circuit device 202. The underfill 210 may reduce stress and protect joints resulting from reflow of the conductive connectors 204. The underfill 210 may be formed of an underfill material, such as a molding compound, an epoxy resin, etc. The underfill 210 may be formed by a capillary flow process after the integrated circuit device 202 is bonded to the interposer wafer 100, or may be formed by a suitable deposition method before the integrated circuit device 202 is bonded to the interposer wafer 100. The underfill 210 may be applied in a liquid or semi-liquid form and then subsequently cured.

In FIG. 11 , an encapsulant 212 is formed on and around the various components. After formation, the encapsulant 212 seals the underfill 210 (if present) and the integrated circuit device 202. The encapsulant 212 may be a molding compound, an epoxy resin, or the like. The encapsulant 212 may be applied by compression molding, transfer molding, or the like, and formed over the interposer wafer 100, thereby burying or covering the integrated circuit device 202. The encapsulant 212 is also formed in the gap areas between the underfill 210 (if present) and/or the integrated circuit device 202. The encapsulant 212 may be applied in a liquid or semi-liquid form and then subsequently cured.

Optionally, the encapsulant 212 may be thinned (not separately shown) to expose the integrated circuit device 202. The thinning process may be a grinding process, chemical mechanical polishing (CMP), etch back, a combination thereof, etc. After the thinning process, the top surfaces of the integrated circuit device 202 and the encapsulant 212 are substantially coplanar (within process variations). The thinning is performed until a desired amount of the integrated circuit device 202 and the encapsulant 212 have been removed.

In FIG. 12 , carrier removal is performed to remove carrier substrate 152 from front-side redistribution structure 140. In embodiments where carrier substrate 152 is attached to front-side redistribution structure 140 by a bonding layer such as an oxide layer or adhesive, the removal process may include a grinding process applied to carrier substrate 152 and the bonding layer. The structure is then flipped over and placed on a tape (not shown separately). The tape may be supported by a suitable frame. Buffer layer 154 (when present) is also removed to expose UBM 146. Buffer layer 154 may be removed by a suitable etching process, etc.

In FIG. 13 , a plurality of package substrates 220 are bonded to the interposer wafer 100 . Each package substrate 220 is bonded to a corresponding interposer in a corresponding package region 100P. Each package substrate 220 includes a substrate core 222 , which may be formed of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, or the like may also be used. In addition, the substrate core 222 may be an SOI substrate. Typically, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 222 is an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or optionally other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminated materials may be used for the substrate core 222 .

The substrate core 222 may include active devices and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements for the design of the system. The devices may be formed using any suitable method. In some embodiments, the substrate core 222 is substantially free of active devices and passive devices.

The substrate core 222 may also include metallization layers and vias (not shown separately). Each package substrate 220 also includes bonding pads 224 located above the metallization layers and vias of the substrate core 222. The metallization layers may be formed above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the vias interconnect the conductive material layers and may be formed by any suitable process (such as deposition, inlay, etc.). In some embodiments, the substrate core 222 has up to six dielectric layers and metallization layers.

The package substrate 220 can be bonded to the interposer wafer 100 using conductive connectors 226. The formation of the conductive connectors 226 will be described in more detail later with respect to FIGS. 15 to 19. The conductive connectors 226 connect the interposer wafer 100 (including the metallization layer of the front-side redistribution structure 140) to the package substrate 220 (including the metallization layer of the substrate core 222). Thus, the package substrate 220 is electrically connected to the integrated circuit devices 202 in the corresponding package region 100P. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not separately shown in FIG. 13, but see FIGS. 15 to 19) are bonded to the interposer wafer 100, such as to the same surface of the interposer wafer 100 as the conductive connectors 226.

In some embodiments, an underfill (not separately shown) is formed between the interposer wafer 100 and the package substrate 220, surrounding the conductive connectors 226 and the UBM 146. The underfill may be formed by a capillary flow process after bonding the package substrate 220, or may be formed by a suitable deposition method before bonding the package substrate 220. The underfill may be a continuous material extending from the front side redistribution structures 140 to each of the package substrate 220.

In FIG. 14 , the segmentation process is performed by cutting along the scribe line area between the package areas 100P. The segmentation process may include sawing, dicing, etc. The segmentation process separates the package areas 100P from each other. The resulting, segmented integrated circuit packages 200 come from the package areas 100P. The segmentation process forms the interposer 230 from the segmented portions of the interposer wafer 100. Due to the segmentation process, the outer sidewalls of the interposer 230 and the sealant 212 are laterally coterminal (within process variations). The width of the package substrate 220 may be less than or similar to the width of the interposer 230.

15 to 19 are schematic cross-sectional views of a process for bonding a package substrate 220 to an interposer wafer 100 according to some embodiments. One package region 100P (e.g., a package substrate 220 and a corresponding interposer 230) is shown, and some components are omitted from FIGS. 15 to 19 for clarity of illustration. The package substrate 220 may have a large thickness. For example, the package substrate 220 may include a plurality of metallization layers, thereby having a large thickness. The package substrate 220 may be at a high risk of warpage due to its large thickness. In some embodiments, the package substrate 220 has a warpage of up to 134 μm. In this case, the warpage amount of the package substrate 220 refers to the difference between the minimum distance between the package substrate 220 and the interposer 230 and the maximum distance between the package substrate 220 and the interposer 230. In order to reduce the effect of warpage during bonding to the interposer wafer 100, the conductive connector 226 (e.g., a solder connector) is formed to have different heights. The height of the conductive connector 226 can be controlled by controlling the volume of the conductive connector 226 and/or the width of the bonding pad 224. Specifically, the conductive connector 226 can have a larger height in areas where the package substrate 220 has a large amount of warpage, while the conductive connector 226 can have a small height in areas where the package substrate 220 has a small amount of warpage. The quality of the conductive connector 226 can thus be improved, such as by reducing the risk of forming a cold solder joint and/or reducing the risk of solder necking.

In some embodiments, the conductive connector 226 with a smaller height is located in the inner region of the package substrate 220, while the conductive connector 226 with a larger height is located in the outer region of the package substrate 220. In other embodiments, the conductive connector 226 with a smaller height is located in the outer region of the package substrate 220, while the conductive connector 226 with a larger height is located in the inner region of the package substrate 220. The inner region of the package substrate 220 is the center of the package substrate 220. The outer region of the package substrate 220 is the edge/corner of the package substrate 220. Specifically, the outer region of the package substrate 220 may be an edge of the package substrate 220, may be a corner of the package substrate 220, or may be a combination thereof. The conductive connector 226 in the outer region of the package substrate 220 may be arranged around the conductive connector 226 in the inner region of the package substrate 220.

In FIG. 15 , a first reflowable connection 250A is formed on a first subset of bonding pads 224A of a package substrate 220. The first reflowable connection 250A may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the first reflowable connection 250A is formed by forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. The first bonding pads 224A are disposed in an area of the package substrate 220 having a small amount of warpage, such as in the center of the package substrate 220 in this embodiment.

In FIG. 16 , a second reflowable connection 250B is formed on a second subset of bonding pads 224B of the package substrate 220. The second reflowable connection 250B may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the second reflowable connection 250B is formed by forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. The second bonding pads 224B are disposed in an area of the package substrate 220 having a large amount of warpage, such as at the edge/corner of the package substrate 220 in this embodiment. The second bonding pads 224B may be disposed around the first bonding pads 224A.

In some embodiments, the material (e.g., solder) of the first reflowable connector 250A and the second reflowable connector 250B is initially formed by the previously described method. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. Therefore, when forming the first reflowable connector 250A and the second reflowable connector 250B, a single reflow can be performed.

In this embodiment, the height of the conductive connection 226 (see FIG. 19) is controlled by controlling the volume of the first reflowable connection 250A and the second reflowable connection 250B. At the same time, the first bonding pad 224A and the second bonding pad 224B have the same width. The second reflowable connection 250B has a larger volume than the first reflowable connection 250A. In some embodiments, the ratio of the volume of the second reflowable connection 250B to the volume of the first reflowable connection 250A is in the range of 0.3 to 3. The second reflowable connection 250B has a larger height than the first reflowable connection 250A. In some embodiments, the ratio of the height of the second reflowable connection 250B to the height of the first reflowable connection 250A is in the range of 1.1 to 1.7, such as in the range of 1.1 to 1.5. In some embodiments, a ratio of the width of the second reflowable connection 250B to the width of the first reflowable connection 250A is in a range of 1.1 to 1.7, such as in a range of 1.1 to 1.5.

In FIG17 , a reflowable layer 254 is formed on the UBM 146 of the interposer 230. The reflowable layer 254 may be formed of a conductive paste, such as a solder paste, a solder-bismuth paste, a silver paste, etc., which may be dispensed in a printing process. In addition, passive devices 256 may be bonded to some of the UBMs 146 of the interposer 230, as previously described.

In FIG. 18 , the package substrate 220 is placed on the front side of the interposer wafer 100. The reflowable connectors 250 (including the first reflowable connector 250A and the second reflowable connector 250B) are aligned with the corresponding reflowable layer 254 (if present) and the UBM 146. Since the second reflowable connector 250B has a larger volume than the first reflowable connector 250A, the second reflowable connector 250B may be able to physically contact the corresponding reflowable layer 254 even when the package substrate 220 is warped. Similarly, the first reflowable connector 250A may physically contact the corresponding reflowable layer 254. Therefore, there may be no gap between the reflowable layer 254 and any corresponding reflowable connector 250 (including the first reflowable connector 250A and the second reflowable connector 250B).

In some embodiments, the subset of the reflowable layer 254B in contact with the second reflowable connector 250B has a larger volume than the subset of the reflowable layer 254A in contact with the first reflowable connector 250A. For example, the reflowable layer 254B can be wider and/or thicker than the reflowable layer 254A. Thus, the risk of a gap forming between the reflowable layer 254B and the second reflowable connector 250B can be reduced.

In FIG19 , the reflowable layer 254 and the reflowable connector 250 are reflowed to form the conductive connector 226. The reflowable layer 254 and the reflowable connector 250 can be reflowed by a suitable annealing process. During the reflow, the material of the reflowable layer 254 mixes with the material of the reflowable connector 250 to form the conductive connector 226. The resulting conductive connector 226 can be a ball grid array (BGA) connector, a solder ball, a controlled collapse chip connection (C4) bump, etc.

Since the second reflowable connector 250B has a larger volume than the first reflowable connector 250A, the subset of the second conductive connector 226B coupled to the second bonding pad 224B has a larger volume and a larger height than the subset of the first conductive connector 226A coupled to the first bonding pad 224A. The height of the second conductive connector 226B can be less than twice the height of the first conductive connector 226A. In some embodiments, the ratio of the height of the second conductive connector 226B to the height of the first conductive connector 226A is in the range of 1.1 to 1.7, such as in the range of 1.1 to 1.5. Such a height ratio can help avoid solder necking and/or cold solder joints. In some embodiments, the height of the first conductive connector 226A is in the range of 50μm to 600μm, and the height of the second conductive connector 226B is in the range of 250μm to 800μm. The height of the conductive connector 226 is measured in the direction extending between the interposer 230 and the package substrate 220.

The second conductive connector 226B and the second bonding pad 224B are arranged in an area where the package substrate 220 has more warpage than the area where the first conductive connector 226A and the first bonding pad 224A are arranged. The increased height of the second conductive connector 226B helps to compensate for the warpage of the package substrate 220 in the warpage area. Therefore, the risk of the conductive connector 226 becoming a cold solder joint and/or experiencing solder necking can be reduced. Due to avoiding solder necking, each of the conductive connectors 226 (including the second conductive connector 226B) can have a convex sidewall. Therefore, the quality of the conductive connector 226 can be enhanced, and the reliability of the integrated circuit package 200 can be improved.

20A-20B are top views of an integrated circuit package 200 including the package substrate 220 of FIG. 19 according to some embodiments. Specifically, FIG. 20A shows the layout of the conductive connector 226, while FIG. 20B shows the layout of the bonding pad 224. The second conductive connector 226B is formed in the edge/corner of the package substrate 220, while the first conductive connector 226A is formed in the center of the package substrate 220. In this embodiment where the height of the conductive connector 226 (see FIG. 18) is controlled by controlling the volume of the conductive connector 226, the second bonding pad 224 (including the first bonding pad 224A and the second bonding pad 224B) has the same width. The width of the second conductive connector 226B is greater than the width of the first conductive connector 226A.

21-22 are schematic cross-sectional views of a process for bonding a package substrate 220 to an interposer wafer 100 according to some embodiments. One package region 100P (eg, a package substrate 220 and a corresponding interposer 230) is shown, and some components are omitted from FIGS.

In FIG21 , a first reflowable connection 250A is formed on a first subset of first bonding pads 224A of a package substrate 220. The first reflowable connection 250A may be formed in a manner similar to that described with respect to FIG15 . In addition, a second reflowable connection 250B is formed on a second subset of second bonding pads 224B of the package substrate 220. The second reflowable connection 250B may be formed in a manner similar to that described with respect to FIG16 . A reflowable layer 254 is formed on the UBM 146 of the interposer 230. The reflowable layer 254 may be formed in a manner similar to that described with respect to FIG17 .

In this embodiment, the height of the conductive connector 226 (see FIG. 22) is controlled by controlling the width of the bonding pad 224. At the same time, the first reflowable connector 250A and the second reflowable connector 250B have the same volume. The second bonding pad 224B has a smaller width than the first bonding pad 224A. In some embodiments, the ratio of the width of the second bonding pad 224B to the width of the first bonding pad 224A is in the range of 0.5 to 0.8. Since the second bonding pad 224B has a smaller width than the first bonding pad 224A, the second reflowable connector 250B has a smaller width and a larger height than the first reflowable connector 250A. In some embodiments, the ratio of the height of the second reflowable connector 250B to the height of the first reflowable connector 250A is in the range of 1.1 to 1.7, such as in the range of 1.1 to 1.5. In some embodiments, the ratio of the width of the second reflowable connection 250B to the width of the first reflowable connection 250A is in the range of 0.4 to 2.5.

22, the reflowable layer 254 and the reflowable connector 250 are reflowed to form the conductive connector 226. The reflowable layer 254 and the reflowable connector 250 may be reflowed in a manner similar to that described with respect to FIG.

Since the second bonding pad 224B has a smaller width than the first bonding pad 224A, the second conductive connector 226B coupled to the second bonding pad 224B has a greater height than the first conductive connector 226A coupled to the first bonding pad 224A. The height of the second conductive connector 226B can be less than twice the height of the first conductive connector 226A. In some embodiments, the ratio of the height of the second conductive connector 226B to the height of the first conductive connector 226A is in the range of 1.1 to 1.7, such as in the range of 1.1 to 1.5. Such a height ratio can help avoid solder necking and/or cold solder joints. In some embodiments, the height of the first conductive connector 226A is in the range of 50μm to 600μm, and the height of the second conductive connector 226B is in the range of 250μm to 800μm. The height of the conductive connector 226 is measured in the direction extending between the interposer 230 and the package substrate 220.

23A-23B are top views of an integrated circuit package 200 including a package substrate 220 of FIG. 22 according to some embodiments. Specifically, FIG. 23A shows a layout of a conductive connector 226, while FIG. 23B shows a layout of a bonding pad 224. A second conductive connector 226B is formed in an edge/corner of the package substrate 220, while a first conductive connector 226A is formed in the center of the package substrate 220. In this embodiment where the height of the conductive connector 226 (see FIG. 22) is controlled by controlling the width of the bonding pad 224, the conductive connector 226 (including the first conductive connector 226A and the second conductive connector 226B) has the same volume. The width of the second bonding pad 224B is greater than the width of the first bonding pad 224A.

24-25 are schematic cross-sectional views of a process for bonding a package substrate 220 to an interposer wafer 100 according to some embodiments. One package region 100P (e.g., a package substrate 220 and a corresponding interposer 230) is shown, and some components are omitted from FIGS. 24-25 for clarity of illustration. This embodiment is similar to the embodiment of FIGS. 21-22, except that the height of the conductive connector 226 (see FIG. 25) is controlled by controlling the width of the bonding pad 224 and also controlling the volume of the first reflowable connector 250A and the second reflowable connector 250B. Therefore, the second conductive connector 226B has a larger volume than the first conductive connector 226A, and the second bonding pad 224B has a smaller width than the first bonding pad 224A.

26A-26B are top views of an integrated circuit package 200 including the package substrate 220 of FIG. 25 according to some embodiments. Specifically, FIG. 26A shows a layout of the conductive connector 226, and FIG. 26B shows a layout of the bonding pad 224. The second conductive connector 226B and the second bonding pad 224B are formed in the edge/corner of the package substrate 220, while the first conductive connector 226A and the first bonding pad 224A are formed in the center of the package substrate 220. Up to half of the second conductive connectors 226B can have a larger volume than the first conductive connector 226A, and up to half of the second bonding pads 224B can have a smaller width than the first bonding pad 224A. The width of the second conductive connector 226B is greater than the width of the first conductive connector 226A.

27-28 are schematic cross-sectional views of a process for bonding a package substrate 220 to an interposer wafer 100 according to some embodiments. One package region 100P (e.g., a package substrate 220 and a corresponding interposer 230) is shown, and some components are omitted from FIGS. 27-28 for clarity of illustration. This embodiment is similar to that of FIGS. 24-25, except that the package substrate 220 has a large amount of warpage in the center. Therefore, a second conductive connector 226B having an increased height is formed at the center of the package substrate 220.

29A-29B are top views of an integrated circuit package 200 including the package substrate 220 of FIG. 28 according to some embodiments. Specifically, FIG. 29A shows a layout of the conductive connector 226, while FIG. 29B shows a layout of the bonding pad 224. The second conductive connector 226B and the second bonding pad 224B are formed in the center of the package substrate 220, while the first conductive connector 226A and the first bonding pad 224A are formed in the edge/corner of the package substrate 220. Up to half of the second conductive connectors 226B may have a larger volume than the first conductive connector 226A, and up to half of the second bonding pads 224B may have a smaller width than the first bonding pad 224A. The width of the second conductive connector 226B is greater than the width of the first conductive connector 226A.

Embodiments can achieve advantages. As previously described, the second reflowable connector 250B can have a larger volume than the first reflowable connector 250A, and/or the second bonding pad 224B can have a smaller width than the first bonding pad 224A. This can make the second conductive connector 226B have a greater height than the first conductive connector 226A. Forming conductive connectors 226 (e.g., solder connectors) with different heights can reduce the impact of warping during bonding the package substrate 220 to the interposer wafer 100. Therefore, the risk of forming a cold solder joint and/or the risk of solder necking can be reduced. Due to avoiding solder necking, each of the conductive connectors 226 (including the second conductive connector 226B) can have a convex sidewall. Therefore, the quality of the conductive connector 226 can be improved.

In an embodiment, a device includes: an interposer; a package substrate; and conductive connectors that bond the package substrate to the interposer, each of the conductive connectors having a convex sidewall, a first subset of the conductive connectors being disposed in a center of the package substrate in a top view, a second subset of the conductive connectors being disposed in an edge/corner of the package substrate in a top view, each of the second subset of the conductive connectors having a height greater than each of the first subset of the conductive connectors. In some embodiments of the device, the height of the second subset of the conductive connectors is less than twice the height of the first subset of the conductive connectors. In some embodiments of the device, the second subset of the conductive connectors has a larger volume than the first subset of the conductive connectors. In some embodiments of the device, the second subset of the conductive connectors has the same volume as the first subset of the conductive connectors. In some embodiments of the device, the package substrate includes bonding pads, the first subset of the bonding pads being coupled to the first subset of the conductive connectors, the second subset of the bonding pads being coupled to the second subset of the conductive connectors, the first subset of the bonding pads having a width greater than the second subset of the bonding pads. In some embodiments of the device, the packaging substrate includes bonding pads, a first subset of the bonding pads are coupled to a first subset of the conductive connectors, a second subset of the bonding pads are coupled to a second subset of the conductive connectors, and the first subset of the bonding pads have the same width as the second subset of the bonding pads.

In an embodiment, a method includes: forming a first reflowable connector on a packaging substrate, the first reflowable connector being disposed in a first region of the packaging substrate; after forming the first reflowable connector, forming a second reflowable connector on the packaging substrate, the second reflowable connector being disposed in a second region of the packaging substrate, the second reflowable connector having a height greater than the first reflowable connector; forming a reflowable layer on an interposer; contacting each of the first reflowable connector and the second reflowable connector with a corresponding reflowable layer; and reflowing the first reflowable connector, the second reflowable connector, and the reflowable layer to bond the packaging substrate to the interposer. In some embodiments of the method, the first region is the center of the packaging substrate in a top view, and the second region is an edge/corner of the packaging substrate in a top view. In some embodiments of the method, the first region is an edge/corner of the packaging substrate in a top view, and the second region is the center of the packaging substrate in a top view. In some embodiments of the method, a first reflowable connector is in contact with a first subset of the reflowable layer, a second reflowable connector is in contact with a second subset of the reflowable layer, and forming the reflowable layer includes: printing the first subset of the reflowable layer to a first thickness; and printing the second subset of the reflowable layer to a second thickness, the second thickness being greater than the first thickness. In some embodiments of the method, the first reflowable connector is formed on a first subset of bonding pads of a packaging substrate, the second reflowable connector is formed on a second subset of bonding pads of the packaging substrate, the second reflowable connector has a larger volume than the first reflowable connector, and the first subset of bonding pads has the same width as the second subset of bonding pads. In some embodiments of the method, the first reflowable connector is formed on a first subset of bonding pads of a packaging substrate, the second reflowable connector is formed on a second subset of bonding pads of the packaging substrate, the second reflowable connector has the same volume as the first reflowable connector, and the first subset of bonding pads has a larger width than the second subset of bonding pads. In some embodiments of the method, a first reflowable connector is formed on a first subset of bonding pads of a packaging substrate, a second reflowable connector is formed on a second subset of bonding pads of the packaging substrate, the second reflowable connector has a larger volume than the first reflowable connector, and the first subset of bonding pads has a larger width than the second subset of bonding pads.

In an embodiment, a method includes: forming a first reflowable connector on a first subset of bonding pads of a packaging substrate, the first reflowable connector being disposed in a center of the packaging substrate in a top view; forming a second reflowable connector on a second subset of bonding pads of the packaging substrate, the second reflowable connector being disposed in an edge/corner of the packaging substrate in a top view, the second reflowable connector having a greater height than the first reflowable connector; placing the packaging substrate on an interposer after forming the first reflowable connector and the second reflowable connector; and reflowing the first reflowable connector and the second reflowable connector to bond the packaging substrate to the interposer. In some embodiments of the method, the second reflowable connector has a greater volume than the first reflowable connector, and the first subset of bonding pads has the same width as the second subset of bonding pads. In some embodiments of the method, the second reflowable connector has the same volume as the first reflowable connector, and the first subset of bonding pads has a greater width than the second subset of bonding pads. In some embodiments of the method, the second reflowable connector has a larger volume than the first reflowable connector, and the first subset of the bonding pads has a larger width than the second subset of the bonding pads. In some embodiments of the method, the interposer includes a reflowable layer, the first subset of the reflowable layer contacts the first reflowable connector, the second subset of the reflowable layer contacts the second reflowable connector, the first reflowable connector and the first subset of the reflowable layer are reflowed to form a first conductive connector, the second reflowable connector and the second subset of the reflowable layer are reflowed to form a second conductive connector, and the second height of the second conductive connector is greater than the first height of the first conductive connector. In some embodiments of the method, the interposer includes a reflowable layer, the first subset of the reflowable layer contacts the first reflowable connector, the second subset of the reflowable layer contacts the second reflowable connector, and the second subset of the reflowable layer is thicker than the first subset of the reflowable layer. In some embodiments of the method, the interposer includes a reflowable layer, a first subset of the reflowable layer contacts the first reflowable connector, a second subset of the reflowable layer contacts the second reflowable connector, and the second subset of the reflowable layer is wider than the first subset of the reflowable layer.

Some embodiments of the present application provide a semiconductor device, including: an interposer; a packaging substrate; and conductive connectors, joining the packaging substrate to the interposer, each of the conductive connectors having a convex sidewall, a first subset of the conductive connectors being arranged in the center of the packaging substrate in a top view, a second subset of the conductive connectors being arranged in an edge/corner of the packaging substrate in the top view, each of the second subset of the conductive connectors having a height greater than that of each of the first subset of the conductive connectors.

In some embodiments, a height of the second subset of the conductive connectors is less than twice a height of the first subset of the conductive connectors.

In some embodiments, the second subset of the conductive connections has a larger volume than the first subset of the conductive connections.

In some embodiments, the second subset of the conductive connectors has the same volume as the first subset of the conductive connectors.

In some embodiments, the packaging substrate includes bonding pads, a first subset of the bonding pads are coupled to the first subset of the conductive connectors, a second subset of the bonding pads are coupled to the second subset of the conductive connectors, and the first subset of the bonding pads have a larger width than the second subset of the bonding pads.

In some embodiments, the packaging substrate includes bonding pads, a first subset of the bonding pads are coupled to the first subset of the conductive connectors, a second subset of the bonding pads are coupled to the second subset of the conductive connectors, and the first subset of the bonding pads have the same width as the second subset of the bonding pads.

Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first reflowable connector on a packaging substrate, the first reflowable connector being disposed in a first region of the packaging substrate; after forming the first reflowable connector, forming a second reflowable connector on the packaging substrate, the second reflowable connector being disposed in a second region of the packaging substrate, the second reflowable connector having a height greater than that of the first reflowable connector; forming a reflowable layer on an interposer; making each of the first reflowable connector and the second reflowable connector contact the corresponding reflowable layer; and reflowing the first reflowable connector, the second reflowable connector, and the reflowable layer to bond the packaging substrate to the interposer.

In some embodiments, the first region is a center of the packaging substrate in a top view, and the second region is an edge/corner of the packaging substrate in the top view.

In some embodiments, the first region is an edge/corner of the packaging substrate in a top view, and the second region is a center of the packaging substrate in the top view.

In some embodiments, the first reflowable connector contacts a first subset of the reflowable layer, the second reflowable connector contacts a second subset of the reflowable layer, and forming the reflowable layer includes: printing the first subset of the reflowable layer to a first thickness; and printing the second subset of the reflowable layer to a second thickness, the second thickness being greater than the first thickness.

In some embodiments, the first reflowable connector is formed on a first subset of bonding pads of the packaging substrate, the second reflowable connector is formed on a second subset of the bonding pads of the packaging substrate, the second reflowable connector has a larger volume than the first reflowable connector, and the first subset of bonding pads has the same width as the second subset of bonding pads.

In some embodiments, the first reflowable connector is formed on a first subset of bonding pads of the packaging substrate, the second reflowable connector is formed on a second subset of the bonding pads of the packaging substrate, the second reflowable connector has the same volume as the first reflowable connector, and the first subset of bonding pads has a larger width than the second subset of bonding pads.

In some embodiments, the first reflowable connector is formed on a first subset of bonding pads of the packaging substrate, the second reflowable connector is formed on a second subset of the bonding pads of the packaging substrate, the second reflowable connector has a larger volume than the first reflowable connector, and the first subset of bonding pads has a larger width than the second subset of bonding pads.

Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first reflowable connector on a first subset of bonding pads of a packaging substrate, the first reflowable connector being disposed in the center of the packaging substrate in a top view; forming a second reflowable connector on a second subset of the bonding pads of the packaging substrate, the second reflowable connector being disposed in an edge/corner of the packaging substrate in the top view, the second reflowable connector having a height greater than that of the first reflowable connector; after forming the first reflowable connector and the second reflowable connector, placing the packaging substrate on an interposer; and reflowing the first reflowable connector and the second reflowable connector to bond the packaging substrate to the interposer.

In some embodiments, the second reflowable connection has a larger volume than the first reflowable connection, and the first subset of the bond pads has the same width as the second subset of the bond pads.

In some embodiments, the second reflowable connection has a same volume as the first reflowable connection, and the first subset of the bond pads has a greater width than the second subset of the bond pads.

In some embodiments, the second reflowable connection has a larger volume than the first reflowable connection, and the first subset of the bond pads has a larger width than the second subset of the bond pads.

In some embodiments, the interposer includes a reflowable layer, a first subset of the reflowable layer contacts the first reflowable connector, a second subset of the reflowable layer contacts the second reflowable connector, the first reflowable connector and the first subset of the reflowable layer are reflowed to form a first conductive connector, the second reflowable connector and the second subset of the reflowable layer are reflowed to form a second conductive connector, and a second height of the second conductive connector is greater than the first height of the first conductive connector.

In some embodiments, the interposer includes a reflowable layer, a first subset of the reflowable layer contacts the first reflowable connector, a second subset of the reflowable layer contacts the second reflowable connector, and the second subset of the reflowable layer is thicker than the first subset of the reflowable layer.

In some embodiments, the interposer includes a reflowable layer, a first subset of the reflowable layer contacts the first reflowable connector, a second subset of the reflowable layer contacts the second reflowable connector, and the second subset of the reflowable layer is wider than the first subset of the reflowable layer.

The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims (10)

1. A semiconductor device, comprising: Intermediary layer; a packaging substrate; and Conductive connectors are provided to bond the package substrate to the interposer, each of the conductive connectors having a convex sidewall, a first subset of the conductive connectors being disposed in the center of the package substrate in a top view, a second subset of the conductive connectors being disposed in an edge/corner of the package substrate in the top view, each of the second subset of the conductive connectors having a greater height than each of the first subset of the conductive connectors. 2 . The semiconductor device of claim 1 , wherein a height of the second subset of the conductive connections is less than twice a height of the first subset of the conductive connections. 3 . The semiconductor device of claim 1 , wherein the second subset of the conductive connections has a larger volume than the first subset of the conductive connections. 4 . The semiconductor device of claim 1 , wherein the second subset of the conductive connections has the same volume as the first subset of the conductive connections. 5. The semiconductor device of claim 1 , wherein the packaging substrate comprises bonding pads, a first subset of the bonding pads being coupled to the first subset of the conductive connectors, a second subset of the bonding pads being coupled to the second subset of the conductive connectors, and the first subset of the bonding pads having a greater width than the second subset of the bonding pads. 6. The semiconductor device of claim 1 , wherein the packaging substrate comprises bonding pads, a first subset of the bonding pads being coupled to the first subset of the conductive connectors, a second subset of the bonding pads being coupled to the second subset of the conductive connectors, and the first subset of the bonding pads having the same width as the second subset of the bonding pads. 7. A method for forming a semiconductor device, comprising: forming a first reflowable connector on a packaging substrate, the first reflowable connector being disposed in a first region of the packaging substrate; After forming the first reflowable connector, forming a second reflowable connector on the packaging substrate, the second reflowable connector being disposed in a second region of the packaging substrate, the second reflowable connector having a greater height than the first reflowable connector; forming a reflowable layer on the interposer; contacting each of the first reflowable connection and the second reflowable connection with a corresponding reflowable layer; and The first reflowable connector, the second reflowable connector, and the reflowable layer are reflowed to bond the package substrate to the interposer. 8 . The method of claim 7 , wherein the first region is a center of the package substrate in a top view, and the second region is an edge/corner of the package substrate in the top view. 9 . The method of claim 7 , wherein the first region is an edge/corner of the package substrate in a top view, and the second region is a center of the package substrate in the top view. 10. A method of forming a semiconductor device, comprising: forming a first reflowable connector on a first subset of bond pads of a package substrate, the first reflowable connector being disposed in a center of the package substrate in a top view; forming a second reflowable connector on a second subset of the bond pads of the package substrate, the second reflowable connector being disposed in an edge/corner of the package substrate in the top view, the second reflowable connector having a greater height than the first reflowable connector; After forming the first reflowable connector and the second reflowable connector, placing the package substrate on an interposer; and The first and second reflowable connectors are reflowed to bond the package substrate to the interposer.