CN118627460A - Back-end design method, device, equipment and storage medium - Google Patents

Abstract

The present application discloses a back-end design method, device, equipment and storage medium. The back-end design method includes: generating an initial layout of several standard components, wherein the several standard components include multiple timing components, and the clock signal input end of each timing component is used to connect with the clock signal output end of the clock source; determining the target positions corresponding to each timing component, the length difference between the first clock paths of any two target positions is less than a preset threshold, and the first clock path of the target position is the clock path between the clock source and the target position; adjusting each timing component to the corresponding target position; and performing clock tree synthesis processing on the adjusted initial layout. In the above manner, the time difference of the clock signal transmitted to each timing component can be reduced, thereby accelerating the timing convergence and shortening the development cycle.

Description

Back-end design method, device, equipment and storage medium

Technical Field

The present application relates to the technical field of integrated circuit design, and in particular to a back-end design method, device, equipment and storage medium.

Background Art

Integrated circuit (or chip) design includes front-end design and back-end design, and the quality of back-end design directly determines whether the chip can meet functional and performance requirements. Back-end design usually includes several key processes: Floorplan, Placement, CTS (Clock Tree Synthesis) and Routing. Among them, the Floorplan stage mainly lays out the I/O Pad and macro cells of the chip, and plans the power supply; the Placement stage automatically places each standard cell according to the circuit structure and logical relationship described in the netlist; the CTS stage mainly balances the delay of each clock path to achieve the purpose of timing convergence.

Since the timing of integrated circuits usually needs to meet the requirements set by R&D personnel, and with the continuous development of integrated circuits, the structure of integrated circuits is becoming more and more complex, resulting in the problem of timing closure of integrated circuits becoming a difficult point in the back-end design process. If the timing closure of integrated circuits can be accelerated, it will help shorten the development cycle of integrated circuits.

Summary of the invention

The main technical problem solved by the present application is to provide a back-end design method, device, equipment and computer-readable storage medium, which can accelerate the timing convergence of integrated circuits, thereby shortening the design cycle of integrated circuits.

In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a back-end design method, the method comprising: generating an initial layout of a number of standard components, the number of standard components including a plurality of timing components, and the clock signal input end of each timing component is used to connect with the clock signal output end of a clock source; determining the target positions corresponding to each timing component, the length difference between the first clock paths of any two target positions is less than a preset threshold, and the first clock path of the target position is the clock path between the clock source and the target position; adjusting each timing element to the corresponding target position; and performing clock tree synthesis processing on the adjusted initial layout.

Optionally, determining the target positions corresponding to each timing element includes: determining a common point, one end of the common point is used to connect to a clock source, and the other end of the common point is used to connect to a clock signal input end of each timing element; based on the common point, determining a plurality of first candidate position sets, the first candidate position sets include candidate positions corresponding to each timing element, and the length difference between the second clock paths of any two candidate positions included in the first candidate position set is less than a preset threshold, and the second clock path of the candidate position is the clock path between the common point and the candidate position; selecting a target position set that meets the requirements from the plurality of first candidate position sets; and using the candidate positions of each timing element in the target position set as the target positions of each timing element.

Optionally, the lengths of the second clock paths of the candidate positions included in the first candidate position set are all the same.

Optionally, selecting a target position set that meets the requirements from a number of first candidate position sets includes: determining the total clock path length of each first candidate position set respectively; and taking the first candidate position set with the shortest total clock path length as the target position set.

Optionally, the plurality of standard elements further include a plurality of voting logic elements, and selecting a target position set that meets the requirements from a plurality of first candidate position sets includes: for each first candidate position set, based on each candidate position included in the first candidate position set, determining a limited area corresponding to the first candidate position set; selecting at least one second candidate position set whose limited area meets preset layout conditions from the plurality of first candidate position sets, and the preset layout conditions include: the limited area can accommodate a plurality of voting logic elements; and selecting a target position set from at least one second candidate position set.

Optionally, the limited area of the first candidate position set is the minimum circumscribed rectangular area corresponding to each candidate position included in the first candidate position set; and/or, selecting the target position set from at least one second candidate position set includes any one of the following methods: taking the second candidate position set with the shortest total clock path length as the target position set; taking the second candidate position set with the smallest area of the limited area as the target position set; determining the target position set from at least one second candidate position set by comprehensively considering the total clock path lengths corresponding to each second candidate position set and the area of the limited area.

Optionally, a clock buffer is arranged at the common point. After each timing element is adjusted to a corresponding target position and before the adjusted initial layout is subjected to clock tree synthesis processing, the method further includes: replacing the clock buffer at the common point with a first clock inverter; and inserting a second clock inverter on the clock path from the common point to each timing element.

Optionally, the lengths of clock paths between the first clock inverter and each second clock inverter are the same, and the lengths of clock paths between each second clock inverter and the corresponding sequential element are the same.

Optionally, determining the common point includes: determining a first element and a second element among a plurality of sequential elements; taking a point on a midline determined based on an initial position of the first element and an initial position of the second element as the common point; and/or, after adjusting each sequential element to a corresponding target position, and before performing clock tree synthesis processing on the adjusted initial layout, the method further includes: performing preset constraint processing on elements and connections on a clock path from the common point to each sequential element so that the elements and connections are not optimized.

Optionally, the plurality of standard components further include a plurality of voting logic components. After each sequential component is adjusted to a corresponding target position and before clock tree synthesis processing is performed on the adjusted initial layout, the method further includes: adjusting the plurality of voting logic components to a limited area of the plurality of sequential components, the limited area being determined based on the target position of each sequential component; and/or, the plurality of standard components are a plurality of circuit elements included in a triple-module redundant circuit, and the number of the plurality of sequential components is 3.

In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a back-end design device, which includes: an initial layout module, used to generate an initial layout of a number of standard components, the number of standard components include a plurality of timing components, and the clock signal input end of each timing component is used to connect with the clock signal output end of the clock source; a determination module, used to determine the target positions corresponding to each timing component, the length difference between the first clock paths of any two target positions is less than a preset threshold, and the first clock path of the target position is the clock path between the clock source and the target position; an adjustment module, used to adjust each timing element to the corresponding target position; a clock tree synthesis module, used to perform clock tree synthesis processing on the adjusted initial layout.

To solve the above technical problems, another technical solution adopted in this application is: to provide an electronic device, including a memory and a processor coupled to each other, the memory storing program instructions; the processor is used to execute the program instructions stored in the memory to implement the above back-end design method.

In order to solve the above technical problems, another technical solution adopted in the present application is: providing a computer-readable storage medium, which is used to store program instructions, and the program instructions can be executed by a processor to implement the above back-end design method.

In the above scheme, after the initial layout of several standard components, each sequential component in the several standard components is first adjusted to the corresponding target position, and then the adjusted initial layout is subjected to clock tree synthesis processing. Since the length difference between the first clock paths of any two target positions is less than the preset threshold, after adjusting each sequential component to the corresponding target position, the length difference of the first clock path of each sequential component can be reduced to reduce the time difference of the clock signal transmitted to each sequential component, thereby accelerating timing convergence and shortening the development cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of an embodiment of a backend design method provided by the present application;

FIG2 is a schematic diagram of the circuit structure of a triple-module redundant circuit provided by the present application;

FIG3 is a flow chart of another embodiment of the back-end design method provided by the present application;

FIG4 is a schematic diagram of an initial layout of several standard cells provided in the present application;

FIG5 is a schematic diagram of an adjusted initial layout of several standard cells provided in the present application;

FIG6 is a flow chart of an embodiment of a back-end design method for a triple-module redundant circuit provided by the present application;

FIG7a is a schematic diagram of a first layout of a triple-module redundant circuit provided by the present application;

FIG7 b is a schematic diagram of a second layout of a triple-module redundant circuit provided by the present application;

FIG7c is a schematic diagram of a third layout of a triple-module redundant circuit provided by the present application;

FIG7 d is a schematic diagram of a fourth layout of a triple-module redundant circuit provided by the present application;

FIG7e is a schematic diagram of a fifth layout of a triple-module redundant circuit provided by the present application;

FIG8 is a schematic diagram of a framework of an embodiment of a back-end design device provided by the present application;

FIG9 is a schematic diagram of a framework of an electronic device according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a framework of an embodiment of a computer-readable storage medium provided in the present application.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail below with reference to the accompanying drawings and examples.

In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

The term "and/or" in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The term "plurality" in this article means two or more than two; the term "several" means at least one; the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

Please refer to FIG. 1, which is a flow chart of an embodiment of a back-end design method provided by the present application. The method can be applied to a computer device that can run a design tool, such as an EDA (Electronic Design Automation) tool, to implement the back-end design method of the present application. It should be noted that if there is substantially the same result, the method of the present application is not limited to the flow sequence shown in FIG. 1.

As shown in FIG1 , the method comprises the following steps:

S11: Generate an initial layout of several standard components.

Among them, several standard components are several circuit components included in the submodule. The chip to be designed for the backend may include several submodules, each of which includes several standard components. The several standard components of each submodule include multiple timing components, and the clock signal input end of each timing component is used to connect to the clock signal output end of the clock source. Exemplarily, each timing element is a trigger, such as a DFF (D-type trigger). The several standard components of each submodule also include multiple voting logic components, and the multiple voting logic components constitute the voter of the submodule.

Taking the submodule as a triple mode redundancy (TMR) circuit as an example, FIG2 is a schematic diagram of the circuit structure of the triple mode redundancy circuit provided by the present application. As shown in FIG2, the triple mode redundancy circuit includes three DFFs 21 and a voter 22 (Voter), and the voter 22 is composed of four voting logic elements. The clock signal input end of each DFF 21 is connected to a clock pad, and the clock pad is used to connect to a clock source.

It should be noted that this embodiment only exemplifies the sub-module as a triple-module redundant circuit. In other embodiments, the sub-module may also be a quad-module redundant (QMR) circuit, a five-module redundant (FMR) circuit, or other circuits or devices that require a clock signal, and this embodiment does not specifically limit this.

In step S11, the plurality of standard components may be arranged according to the default arrangement rule to obtain an initial layout of the plurality of standard components. Exemplarily, the default arrangement rule is to arrange the timing components in the plurality of standard components in different rows, and the spacing between the rows is greater than or equal to the spacing threshold, and the voting logic components in the plurality of standard components may be arranged arbitrarily.

S12: Determine the target position corresponding to each sequential component in a plurality of standard components.

The length difference between the first clock paths of any two target locations is less than a preset threshold, and the first clock path of the target location is a clock path between a clock source and the target location. The preset threshold is a preset smaller value.

Exemplarily, the triple-mode redundant circuit includes three sequential elements, the target positions of the three sequential elements are A, B and C respectively, the lengths of the first clock paths of the three sequential elements are L1, L2 and L3 respectively, and the length difference ΔL1 between L1 and L2, the length difference ΔL2 between L1 and L3, and the length difference ΔL3 between L2 and L3 are all less than a preset threshold ΔL. For example, ΔL1, ΔL2 and ΔL3 are all 0, that is, L1, L2 and L3 are all equal.

S13: Adjust each sequential element to a corresponding target position.

After each sequential element is adjusted to a corresponding target position, the length difference between the first clock paths of any two sequential elements is less than a preset threshold.

S14: Perform clock tree synthesis processing on the adjusted initial layout.

In this embodiment, after the initial layout of several standard components, each sequential component in the several standard components is first adjusted to the corresponding target position, and then the adjusted initial layout is subjected to clock tree synthesis processing. Since the length difference between the first clock paths of any two target positions is less than the preset threshold, after each sequential component is adjusted to the corresponding target position, the length difference of the first clock path of each sequential component can be reduced to reduce the time difference of the clock signal transmitted to each sequential component, thereby accelerating the timing convergence and shortening the development cycle.

Please refer to Figure 3, which is a flow chart of another embodiment of the backend design method provided by the present application. The method can be applied to the aforementioned computer device, as shown in Figure 3, and the method includes the following steps:

S31: Generate an initial layout of several standard components.

The plurality of standard components include a plurality of timing components and a plurality of voting logic components. Specifically, the plurality of standard components may be placed according to the default placement rule to obtain an initial layout of the plurality of standard components. Exemplarily, the default placement rule is to place the timing components in the plurality of standard components in different rows, and the spacing between the rows is greater than or equal to the spacing threshold, and the voting logic components in the plurality of standard components may be placed arbitrarily.

S32: Determine a common point.

In order to facilitate the adjustment of the position of each sequential element in the standard element, a common point can be determined first, and then the target position of each sequential element can be determined based on the common point. One end of the common point is used to connect to the clock source, and the other end of the common point is used to connect to the clock signal input end of each sequential element.

In one embodiment, the common point may be any point.

In another embodiment, the position of the common point can be determined based on the positions of multiple sequential elements in the initial layout. Specifically, determining the common point includes the following sub-steps:

Sub-step 1: determining a first component and a second component among a plurality of sequential components.

Specifically, the first element and the second element may be any two sequential elements among the plurality of sequential elements. Alternatively, the first element is the sequential element placed in the first row among the plurality of sequential elements, and the second element is the sequential element placed in the last row among the plurality of sequential elements.

Sub-step two: taking a point on the midline determined based on the initial position of the first element and the initial position of the second element as a common point.

Specifically, based on the initial position of the first element and the initial position of the second element in the initial layout, the midline of the first element and the second element can be determined, and any point on the midline is used as a common point, wherein the midline is parallel to the row where the first element is located and the row where the second element is located.

S33: Determine a plurality of first candidate position sets based on the common point.

Furthermore, after determining the common point, several first candidate position sets can be determined based on the common point, each first candidate position set includes candidate positions corresponding to each timing element, and the candidate positions of each timing element included in different first candidate position sets are different. Then, a target position set that meets the requirements is selected from the several first candidate position sets, and the candidate positions of each timing element in the target position set are respectively used as the target positions of each timing element.

In order to reduce the time difference of the clock signal being transmitted to each sequential element, the length difference between the second clock paths of any two candidate positions included in each first candidate position set is less than a preset threshold. The second clock path of the candidate position is the clock path between the common point and the candidate position. It should be noted that for each first candidate position set, since the clock path between the clock source and the common point is a clock path common to each candidate position, when the length difference between the second clock paths of each candidate position is less than the preset threshold, the length difference between the first clock paths from the clock source to each candidate position is also less than the preset threshold. In order to further reduce the time difference of the clock signal being transmitted to each sequential element, the length of the second clock path of each candidate position included in the first candidate position set can be made the same.

Each candidate position in the first candidate position set still complies with the aforementioned default placement rule, that is, each candidate position in the first candidate position set is located in a different row, and the spacing between the rows is greater than or equal to the spacing threshold.

In order to minimize the difference between the initial layout after adjustment and the initial layout before adjustment, among the candidate positions of the sequential elements included in each first candidate position set, there is at least one candidate position of the sequential element whose row is the same as the row of the at least one sequential element in the initial layout. The rows of the candidate positions of different first candidate position sets may be the same or different.

The following is an exemplary description using a triple-module redundant circuit as an example, wherein the triple-module redundant circuit includes sequential element 1, sequential element 2, and sequential element 3, and in the initial layout, sequential element 1, sequential element 2, and sequential element 3 are located in row a, row b, and row e, respectively, and the determined first candidate position sets include first candidate position set 1, first candidate position set 2, first candidate position set 3, and first candidate position set 4.

For example, the rows where sequential element 1, sequential element 2 and sequential element 3 in first candidate position set 1, first candidate position set 2, first candidate position set 3 and first candidate position set 4 are located are the same as those in the initial layout, that is, they are still located in row a, row b and row e respectively.

For another example, the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in first candidate position set 1, first candidate position set 2, first candidate position set 3 and first candidate position set 4 are respectively located in row a, row c and row e.

For another example, the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 1 are located in the a-th row, the b-th row and the e-th row respectively; the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 2 are located in the a-th row, the c-th row and the e-th row respectively; the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 3 are located in the a-th row, the b-th row and the c-th row respectively; the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 4 are located in the b-th row, the c-th row and the d-th row respectively.

For another example, the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 1 and the first candidate position set 2 are respectively located in the a-th row, the b-th row and the e-th row; the candidate positions of sequential element 1, sequential element 2 and sequential element 3 in the first candidate position set 3 and the first candidate position set 4 are respectively located in the a-th row, the c-th row and the e-th row.

S34: Selecting a target position set that meets the requirements from a plurality of first candidate position sets.

In one embodiment, only the placement of multiple timing elements among several standard elements is considered, and the placement of multiple voting logic elements among several standard elements is not considered. Then, selecting a target position set that meets the requirements from several first candidate position sets includes: determining the total clock path length of each first candidate position set respectively; and taking the first candidate position set with the shortest total clock path length as the target position set.

Specifically, for each first candidate position set, the length of the second clock path of each candidate position in the first candidate position set is determined, and the length of the second clock path of each candidate position is summed to obtain the total clock path length corresponding to the first candidate position set. Then, the first candidate position set with the shortest total clock path length among the first candidate position sets is selected as the target position set.

In this implementation, by using the first candidate position set with the shortest total clock path length as the target position set of multiple sequential elements, the clock tree net can be made shortest, thereby saving wiring resources.

In another embodiment, considering the placement of multiple sequential elements and the placement of multiple voting logic elements in the multiple standard elements at the same time, selecting a target position set that meets the requirements from the multiple first candidate position sets may include the following sub-steps:

Sub-step 1: for each first candidate position set, based on each candidate position included in the first candidate position set, determine a limited area corresponding to the first candidate position set.

The limited area of the first candidate position set is the minimum circumscribed rectangular area corresponding to each candidate position included in the first candidate position set.

Sub-step 2: selecting at least one second candidate position set whose limited area meets preset layout conditions from the plurality of first candidate position sets, wherein the preset layout conditions include: the limited area can accommodate a plurality of voting logic elements.

Among the first candidate position sets, there may be first candidate position sets whose limited areas do not meet the preset layout conditions. Therefore, the first candidate position sets whose limited areas do not meet the preset layout conditions need to be eliminated.

Sub-step three: selecting a target location set from at least one second candidate location set.

In this implementation, at least one second candidate position set whose limited area meets the preset layout conditions is selected from a number of first candidate position sets, and then a target position set of multiple sequential elements is selected from at least one second candidate position set. Since the difference in the length of the second clock path of the candidate position of each sequential element in each first candidate position set is less than the preset threshold, and the limited area is determined based on the candidate position of each sequential element in the first candidate position set, each candidate position in the target position set is used as the target position of multiple sequential elements. On the one hand, the difference in the length of the clock path of each sequential element can be reduced, thereby accelerating the timing convergence; on the other hand, compared with the scattered placement of multiple voting logic elements, limiting the multiple voting logic elements in the limited area of the multiple timing elements can make the multiple voting logic elements closer to the multiple timing elements, that is, the distance distribution between the multiple voting logic elements and each sequential element can be more uniform, and the delay is closer, thereby further accelerating the timing convergence.

In one example, any second candidate position set may be used as a target position set.

In another example, the total clock path length of each second candidate position set is determined respectively; and the second candidate position set with the shortest total clock path length is used as the target position set. For the relevant content of determining the total clock path length of the second candidate position set, please refer to the above-mentioned determination of the total clock path length of the first candidate position set, which will not be repeated here. This example can reduce the length difference of the clock path of each timing element, and place multiple voting logic elements within the limited area of multiple timing elements, while further making the clock tree net the shortest and saving winding resources.

In another example, the area of the limited area corresponding to each second candidate position set is determined respectively; and the second candidate position set with the smallest area of the limited area is used as the target position set. This example can reduce the length difference of the clock path of each sequential element, and place multiple voting logic elements within the limited area of multiple sequential elements, while further reducing the occupied area of multiple voting logic elements.

In another example, the total clock path lengths and the areas of the limited areas corresponding to the second candidate position sets are combined to determine the target position set from at least one second candidate position set. This example can reduce the length differences of the clock paths of the sequential elements, and place the multiple voting logic elements within the limited areas of the multiple sequential elements while selecting a better target position set by combining the total clock path lengths and the areas of the limited areas.

Specifically, for each second candidate position set, a first score is determined based on the total clock path length of the second candidate position set, a second score is determined based on the area of a limited region of the second candidate position set, and the first score and the second score of the second candidate position set are combined to obtain a total score for the second candidate position set; and a second candidate position set with the highest total score is selected from at least one second candidate position set as the target position set.

Exemplarily, the first score of each set of second candidate positions may be determined based on the mapping relationship between the total clock path length and the first score. For example, the longer the total clock path length, the lower the corresponding first score; the shorter the total clock path length, the higher the corresponding first score. The second score of each set of candidate positions may be determined based on the mapping relationship between the area of the defined region and the second score. For example, the smaller the area of the defined region, the higher the corresponding second score; the larger the area of the defined region, the lower the corresponding second score.

Exemplarily, combining the first score and the second score of the second candidate location set to obtain the total score of the second candidate location set includes: taking the average of the first score and the second score of the second candidate location set as the total score of the second candidate location set; or taking the weighted value of the first score and the second score of the second candidate location set as the total score of the second candidate location set. The weighting coefficient of the first score and the weighting coefficient of the second score can be determined according to actual needs.

In this implementation, the area of the chip can be reduced by saving clock tree routing resources and reducing the occupied area of multiple voting logic elements; accelerating the timing convergence of the chip means that the frequency of the chip can be higher in theory, or the power consumption of the chip is lower at the same frequency. Therefore, the use of this implementation is conducive to improving the PPA of the chip, that is, the Performance, Power and Area of the chip.

S35: taking the candidate positions of each sequential component in the target position set as the target positions of each sequential component.

S36: Adjust each sequential element to a corresponding target position.

Furthermore, after adjusting each sequential element to a corresponding target position, the method further includes: adjusting a plurality of voting logic elements to a limited area of the plurality of sequential elements, wherein the limited area is determined based on the target position of each sequential element.

Furthermore, a clock buffer (ckbuf) is arranged at the common point, and after each timing element is adjusted to the corresponding target position, it also includes: replacing the clock buffer at the common point with a first clock inverter, and inserting a second clock inverter on the clock path from the common point to each timing element.

In one example, for each sequential element, a second clock inverter may be inserted at any position on the clock path from the common point to the sequential element.

In another example, to further reduce the delay difference of clock signal transmission on each second clock path, the clock path lengths between the inserted first clock inverter and each second clock inverter are the same, and the clock path lengths between each second clock inverter and the corresponding timing element are the same.

Furthermore, after adjusting each sequential element to the corresponding target position, it also includes: performing preset constraint processing on the elements and connections on the clock path from the common point to each sequential element, so that the elements and connections on the clock path from the common point to each sequential element are not optimized. The preset constraint processing is a dont_touch processing. For example, the first clock inverter at the common point, the connection between the first clock inverter and each second clock inverter, each second clock inverter, and the connection between each second clock inverter and the corresponding sequential element are all subjected to preset constraint processing.

Please refer to Figure 4, which is a schematic diagram of the initial layout of several standard cells provided by the present application. As shown in Figure 4, in the initial layout of several standard cells, each sequential element (DFF1, DFF2 and DFF3 in Figure 4) is located in different rows, the clock path lengths from the clock inverter (ckinv) at the common point to each sequential element are quite different, and each voting logic element is dispersed far away.

Figure 5 is a schematic diagram of the initial layout of several standard cells after adjustment provided by the present application. As shown in Figure 5, in the initial layout of several standard cells after adjustment, each sequential element is still located in a different row, but the clock path length from the clock inverter at the common point to each sequential element is equal (with a small difference), and each voting logic element is confined to the limited area corresponding to the dotted box.

S37: Perform clock tree synthesis processing on the adjusted initial layout.

In this embodiment, after the initial layout of a number of standard components, a number of first candidate position sets are first determined based on common points, and then a number of target position sets of sequential components are selected from the first candidate position sets. Since the length difference between the second clock paths of any two candidate positions included in each first candidate position set is less than a preset threshold, after adjusting each sequential component to a corresponding target position in the target position set, the length difference of the second clock path of each sequential component can be reduced to reduce the time difference of the clock signal transmitted to each sequential component, thereby accelerating timing convergence and shortening the development cycle.

In a specific application scenario, the design is performed for the three-mode redundant circuit in the chip. The standard unit placement and clock tree synthesis of the three-mode redundant circuit need to meet the mandatory functional safety requirements, which include requirements 1 and 2. Among them, requirement 1 includes: the three DFFs of the three-mode redundant circuit are placed in different rows, and a certain distance is left between the rows; requirement 2 includes: each DFF of the three-mode redundant circuit is driven by a separate ckinv.

Considering that the focus of the above approach at the beginning of development was only on meeting the mandatory requirements of functional safety, and on the basis of meeting the mandatory requirements of functional safety, other issues (mainly static timing analysis and routing) were not considered enough, resulting in more problems encountered in the actual process and too many timing convergence iterations, and even requiring a larger area to realize the back-end design of the three-mode redundant circuit. For this reason, this application adds additional requirements on the basis of the above-mentioned mandatory requirements of functional safety, and the additional requirements include requirements 3 and 4. Among them, requirement 3 includes: the clock path lengths of the three DFFs of the three-mode redundant circuit are as equal as possible, and the wiring resources are occupied as little as possible; requirement 4 includes: each voting logic element of the three-mode redundant circuit must be placed close to the three DFFs.

Please refer to Figure 6, which is a flow chart of an embodiment of a back-end design method for a triple-module redundant circuit provided by the present application. As shown in Figure 6, the method includes the following steps:

S61: automatically placing a plurality of standard units of a triple-module redundant circuit according to a default placement rule, wherein the plurality of standard units of the triple-module redundant circuit include three DFFs and four voting logic elements.

After automatically placing several standard units of the triple-module redundant circuit according to the default placement rules, the first layout of the triple-module redundant circuit can be obtained. Figure 7a is a schematic diagram of the first layout of the triple-module redundant circuit provided by the present application. As shown in Figure 7a, after being placed according to the default placement rules, the three DFFs are respectively located in different rows and there is a certain distance between different rows, that is, the placement of the three DFFs meets the aforementioned requirement 1, and the four voting logic elements are dispersed far away.

S62: Determine a common point according to the positions of the three placed DFFs, and insert a common clock buffer at the common point.

After inserting a common clock buffer at the common point, a second layout of the three-module redundant circuit can be obtained. Figure 7b is a schematic diagram of the second layout of the three-module redundant circuit provided by the present application. A point on the midline of DFF1 located in the first row and DFF3 located in the last row is taken as a common point. The midline is parallel to the row where DFF1 is located and the row where DFF3 is located. A common clock buffer is inserted at the determined common point. The position of the common clock buffer can be shown in Figure 7b.

S63: Based on the position of the common point, determine the target positions corresponding to the three DFFs respectively.

The relevant contents of determining the common point in step S62 can refer to the aforementioned step S32, and the relevant contents of determining the target positions of the three DFFs in step S63 can refer to the aforementioned steps S33 to S35, which will not be repeated here.

S64: Adjust the three DFFs to corresponding target positions respectively.

After adjusting the three DFFs to the corresponding target positions respectively, the third layout of the three-module redundant circuit can be obtained. Figure 7c is a schematic diagram of the third layout of the three-module redundant circuit provided in the present application. The target positions of the three DFFs determined can be shown in Figure 7c respectively. The lengths of the clock paths from the clock buffer at the common point to DFF1, DFF2 and DFF3 in Figure 7c are the same, that is, the placement of the three DFFs meets the aforementioned requirement 3.

S65: Determine a limited area based on the adjusted positions of the three DFFs.

The limited area is the minimum circumscribed rectangular area of the three DFFs.

S66: Adjust the four voting logic elements to within the limited area.

After adjusting the four voting logic elements into the limited area, the fourth layout of the three-module redundant circuit can be obtained. FIG7d is a schematic diagram of the fourth layout of the three-module redundant circuit provided in the present application. The limited area can be shown as the dotted box in FIG7d. After adjusting the four voting logic elements of the three-module redundant circuit into the limited area, the four voting logic elements of the three-module redundant circuit meet the aforementioned requirement 4.

S67: Replace the clock buffer at the common point with a first clock inverter, and insert a second clock inverter into each clock path between the common point and each DFF.

After inserting the first clock inverter and each second clock inverter, the fifth layout of the triple-module redundant circuit can be obtained. FIG7e is a schematic diagram of the fifth layout of the triple-module redundant circuit provided by the present application. The first clock inverter at the common point and the second clock inverter on the clock path of each DFF can be shown in FIG7e. After inserting the second clock inverter on the clock path of each DFF, each DFF can be driven by an independent second clock inverter, that is, the aforementioned requirement 2 is met.

S68: Preset constraint processing is performed on the first clock inverter at the common point, the connection between the first clock inverter and each second clock inverter, each second clock inverter, and the connection between each second clock inverter and the corresponding timing element.

The preset processing is the dont_touch processing. Further, the layout of the triple-module redundant circuit after the preset constraint processing can be subjected to clock tree synthesis processing.

Please refer to Fig. 8, which is a schematic diagram of a framework of an embodiment of a backend design device provided by the present application. In this embodiment, the backend design device 80 includes: an initial layout module 81, a determination module 82, an adjustment module 83 and a clock tree synthesis module 84.

Among them, the initial layout module 81 is used to generate an initial layout of several standard components, which include multiple timing components, and the clock signal input end of each timing component is used to connect to the clock signal output end of the clock source. The determination module 82 is used to determine the target positions corresponding to each timing component, the length difference between the first clock paths of any two target positions is less than a preset threshold, and the first clock path of the target position is the clock path between the clock source and the target position. The adjustment module 83 is used to adjust each timing component to the corresponding target position. The clock tree synthesis module 84 is used to perform clock tree synthesis processing on the adjusted initial layout.

Optionally, the determination module 82 is used to determine a common point, one end of the common point is used to connect to the clock source, and the other end of the common point is used to connect to the clock signal input end of each timing element; based on the common point, a number of first candidate position sets are determined, the first candidate position sets include candidate positions corresponding to each timing element, and the length difference between the second clock paths of any two candidate positions included in the first candidate position set is less than a preset threshold, and the second clock path of the candidate position is the clock path between the common point and the candidate position; a target position set that meets the requirements is selected from the number of first candidate position sets; and the candidate positions of each timing element in the target position set are respectively used as the target positions of each timing element.

Optionally, the lengths of the second clock paths of the candidate positions included in the first candidate position set are all the same.

Optionally, the determination module 82 is used to respectively determine the total clock path length of each first candidate position set; and take the first candidate position set with the shortest total clock path length as the target position set.

Optionally, the plurality of standard elements also include a plurality of voting logic elements, and the determination module 82 is used to determine, for each first candidate position set, a limited area corresponding to the first candidate position set based on each candidate position included in the first candidate position set; select at least one second candidate position set whose limited area meets preset layout conditions from the plurality of first candidate position sets, and the preset layout conditions include: the limited area can accommodate a plurality of voting logic elements; and select a target position set from at least one second candidate position set.

Optionally, the limited area of the first candidate position set is the minimum circumscribed rectangular area corresponding to each candidate position included in the first candidate position set;

And/or, the determination module 82 is used to select a target position set from at least one second candidate position set in any one of the following ways: taking the second candidate position set with the shortest total clock path length as the target position set; taking the second candidate position set with the smallest area of the limited area as the target position set; and determining the target position set from at least one second candidate position set by comprehensively considering the total clock path lengths and the areas of the limited areas corresponding to each second candidate position set.

Optionally, a clock buffer is arranged at the common point, and the back-end design device 80 further includes an inverter insertion module 85. After the adjustment module 83 adjusts each sequential element to a corresponding target position, and before the clock tree synthesis module 84 performs clock tree synthesis processing on the adjusted initial layout, the inverter insertion module 85 is used to replace the clock buffer at the common point with a first clock inverter, and to insert a second clock inverter on the clock path from the common point to each sequential element.

Optionally, the lengths of clock paths between the first clock inverter and each second clock inverter are the same, and the lengths of clock paths between each second clock inverter and the corresponding sequential element are the same.

Optionally, the determination module 82 is used to determine the first element and the second element among the plurality of sequential elements; and a point on the midline determined based on the initial position of the first element and the initial position of the second element is used as a common point. And/or, the back-end design device 80 further includes a preset constraint processing module 86, which is used to perform preset constraint processing on the elements and wires on the clock path from the common point to each sequential element after the adjustment module 83 adjusts each sequential element to the corresponding target position, and before the clock tree synthesis module 84 performs clock tree synthesis processing on the adjusted initial layout, so that the elements and wires are not optimized.

Optionally, the plurality of standard components further include a plurality of voting logic components, and the adjustment module 83 is further used to adjust the plurality of voting logic components to within a limited area of the plurality of timing components, wherein the limited area is determined based on a target position of each timing component; and/or, the plurality of standard components are a plurality of circuit elements included in a triple-mode redundant circuit, and the number of the plurality of timing components is 3.

It should be noted that the device of this embodiment can execute the steps in the above method. For detailed description of the relevant content, please refer to the above method part, which will not be repeated here.

Please refer to FIG9 , which is a schematic diagram of a framework of an electronic device according to an embodiment of the present application. In this embodiment, the electronic device 90 includes a memory 91 and a processor 92 .

The processor 92 may also be referred to as a CPU (Central Processing Unit). The processor 92 may be an integrated circuit chip having signal processing capabilities. The processor 92 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. A general-purpose processor may be a microprocessor or the processor 92 may also be any conventional processor 92, etc.

The memory 91 in the electronic device 90 is used to store program instructions required for the processor 92 to run.

The processor 92 is used to execute program instructions to implement the back-end design method in this application.

Please refer to Figure 10, which is a schematic diagram of the framework of an embodiment of a computer-readable storage medium provided by the present application. The computer-readable storage medium 100 of the embodiment of the present application stores a program instruction 101, and the program instruction 101 implements the back-end design method provided by the present application when it is executed. Among them, the program instruction 101 can form a program file and be stored in the above-mentioned computer-readable storage medium 100 in the form of a software product, so that a computer device (which can be a personal computer, a server, or a network device, etc.) executes all or part of the steps of each implementation method of the present application. The aforementioned computer-readable storage medium 100 includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, or a terminal device such as a computer, a server, a mobile phone, and a tablet.

In the above scheme, after the initial layout of several standard components, each sequential component in the several standard components is first adjusted to the corresponding target position, and then the adjusted initial layout is subjected to clock tree synthesis processing. Since the length difference between the first clock paths of any two target positions is less than the preset threshold, after adjusting each sequential component to the corresponding target position, the length difference of the first clock path of each sequential component can be reduced to reduce the time difference of the clock signal transmitted to each sequential component, thereby accelerating timing convergence and shortening the development cycle.

In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims (13)

1. A back-end design method, the method comprising:

generating an initial layout of a plurality of standard elements, wherein the standard elements comprise a plurality of time sequence elements, and the clock signal input end of each time sequence element is used for being connected with the clock signal output end of a clock source;

determining target positions corresponding to the time sequence elements respectively, wherein the length difference between first clock paths of any two target positions is smaller than a preset threshold value, and the first clock paths of the target positions are clock paths between the clock source and the target positions;

Respectively adjusting each time sequence element to the corresponding target position;

and carrying out clock tree comprehensive processing on the adjusted initial layout.

2. The method of claim 1, wherein determining the respective target locations for each of the timing elements comprises:

Determining a common point, wherein one end of the common point is used for being connected with the clock source, and the other end of the common point is respectively used for being connected with the clock signal input end of each time sequence element;

determining a plurality of first candidate position sets based on the common point, wherein the first candidate position sets comprise candidate positions respectively corresponding to the time sequence elements, the length difference between second clock paths of any two candidate positions included in the first candidate position sets is smaller than the preset threshold, and the second clock paths of the candidate positions are clock paths between the common point and the candidate positions;

selecting a target position set meeting the requirements from the plurality of first candidate position sets;

And taking the candidate positions of the time sequence elements in the target position set as the target positions of the time sequence elements respectively.

3. The method of claim 2, wherein the second clock path length for each of the candidate locations included in the first set of candidate locations is the same.

4. The method of claim 2, wherein said selecting a satisfactory set of target locations from said first plurality of candidate locations comprises:

Determining a total clock path length of each first candidate position set respectively;

And taking the first candidate position set with the shortest total clock path length as the target position set.

5. The method of claim 2, wherein the plurality of standard elements further comprises a plurality of voting logic elements, and wherein selecting a satisfactory set of target locations from the plurality of first candidate location sets comprises:

Determining a limited area corresponding to the first candidate position set based on the candidate positions included in the first candidate position set for each first candidate position set;

selecting at least one second candidate position set of which the limited area meets preset layout conditions from the plurality of first candidate position sets, wherein the preset layout conditions comprise: the defined area is capable of housing the plurality of voting logic elements;

The set of target locations is selected from the at least one second set of candidate locations.

6. The method of claim 5, wherein the step of determining the position of the probe is performed,

The limited area of the first candidate position set is a minimum circumscribed rectangular area corresponding to each candidate position included in the first candidate position set;

and/or said selecting said set of target locations from said at least one second set of candidate locations comprises any one of:

taking the second candidate position set with the shortest total clock path length as the target position set;

Taking the second candidate position set with the minimum area of the limiting area as the target position set;

and integrating the total clock path length corresponding to each second candidate position set and the area of the limiting area, and determining the target position set from the at least one second candidate position set.

7. The method of claim 2, wherein a clock buffer is disposed at the common point, the method further comprising, after the adjusting each of the sequential elements to the corresponding target position, respectively, and before the clock tree synthesis processing of the adjusted initial layout:

Replacing the clock buffer at the common point with a first clock inverter; and inserting a second clock inverter on the clock path from the common point to each time sequence element.

8. The method of claim 7, wherein the clock path lengths between the first clock inverter and each of the second clock inverters are the same, and the clock path lengths between each of the second clock inverters and the corresponding ones of the sequential elements are the same.

9. The method of claim 2, wherein the step of determining the position of the substrate comprises,

The determining the common point includes:

determining a first element and a second element of the plurality of timing elements;

Taking a point on a midline determined based on the initial position of the first element and the initial position of the second element as the common point;

and/or after each time sequence element is respectively adjusted to the corresponding target position and before the clock tree synthesis processing is performed on the adjusted initial layout, the method further comprises:

And performing preset constraint processing on the elements and the connecting lines on the clock paths from the common point to each time sequence element, so that the elements and the connecting lines are not optimized.

10. The method of claim 1, wherein the plurality of standard elements further comprises a plurality of voting logic elements, and wherein after each of the sequential elements is adjusted to the corresponding target position, and before the clock tree synthesis process is performed on the adjusted initial layout, the method further comprises:

Adjusting the plurality of voting logic elements into a defined area of the plurality of timing elements, the defined area being determined based on the target location of each of the timing elements;

and/or the standard elements are circuit elements included in the triple modular redundancy circuit, and the number of the time sequence elements is 3.

11. A back end design device, the device comprising:

the initial layout module is used for generating initial layouts of a plurality of standard elements, wherein the standard elements comprise a plurality of time sequence elements, and the clock signal input end of each time sequence element is used for being connected with the clock signal output end of a clock source;

The determining module is used for determining target positions corresponding to the time sequence elements respectively, wherein the length difference between first clock paths of any two target positions is smaller than a preset threshold value, and the first clock paths of the target positions are clock paths between the clock source and the target positions;

The adjusting module is used for respectively adjusting each time sequence element to the corresponding target position;

And the clock tree synthesis module is used for carrying out clock tree synthesis processing on the adjusted initial layout.

12. An electronic device comprising a memory and a processor coupled to each other,

The memory stores program instructions;

The processor is configured to execute program instructions stored in the memory to implement the method of any one of claims 1-10.

13. A computer readable storage medium for storing program instructions executable by a processor to implement the method of any one of claims 1-10.