CN118612010A - A CAN bus controller system capable of dynamically managing filter SRAM - Google Patents

Abstract

A CAN bus controller system capable of dynamically managing filter SRAM relates to the technical field of CAN bus, which mainly comprises the following components: the interface management module is used for initializing the CAN bus controller through the CAN bus controller initializing module, initializing the acceptance filter through the acceptance filter controlling module, controlling the distribution of the SRAM of the acceptance filter, and comparing the data of the SRAM of the acceptance filter with the received ID and IDE, RTR, EDL, FDF content to determine whether to receive the message; the acceptance filter SRAM is used for storing an externally configured ID for filtering, namely a filtering reference value and a filtering mask; the CAN bus controller initialization module is connected with the CAN bus controller and is used for completing the initialization of the CAN bus controller according to external configuration. The invention CAN realize the dynamic management and distribution of the SRAM of the acceptance filter to a plurality of CAN bus controllers, and CAN distribute the SRAM space according to the requirement.

Description

A CAN bus controller system capable of dynamically managing filter SRAM

Technical Field

The present invention relates to the technical field of CAN bus, and in particular to a CAN bus controller system capable of dynamically managing a filter SRAM.

Background Art

CAN (Controller Area Network) is currently an ISO internationally standardized serial communication protocol and one of the most widely used open fieldbuses in the world. It was originally designed by Bosch of Germany and used for automobile monitoring and control. Later, as a variety of serial communication buses, CAN bus has played an increasingly important role in the fields of computers, communication networks, intelligent sensor technology, and industrial control due to its advantages such as low cost, high reliability, and remote request. At present, the development is mainly aimed at the CAN2.0 protocol, but with the demand for the communication rate of the CAN bus, the development of FDCAN has also received more and more attention. FDCAN (CAN with Flexible Data rate) is an upgraded version of the CAN bus. It inherits the main characteristics of CAN and makes up for the limitations of CAN data length and bandwidth.

There are many existing technologies related to the CAN bus, such as "Dual Redundant CAN Bus Controller and Message Processing Method Thereof" with Patent No. 20081010106353.4, "CAN Bus HUB Board" with Patent No. 201620798479.2, and "CAN Bus Network Control Method and CAN Bus Network" with Patent No. 201710586911.0. These have all studied two or more CAN bus controllers, but these controllers are all CAN2.0 bus controllers, not FDCAN bus controllers, and the acceptance filters are all default built-in registers, and do not involve improvements to the shared acceptance filter SRAM.

As shown in Figure 1, the acceptance filters of conventional CAN bus controllers are all default built-in registers. The ID and mask are configured externally through the configuration register. Only limited specific messages can be filtered and received each time. When you want to receive other messages, you need to reconfigure. In a redundant CAN bus controller system, each CAN bus controller uses its own acceptance filter to implement message filtering. Figure 8 shows the communication process of a conventional CAN bus controller system. Its filter initialization includes configuring the ID filter mode register, and writing a set of ID reference values and masks into the corresponding registers. During the communication process, only this set of IDs and masks and their corresponding modes can be used for filtering.

In the actual application scenario of redundant CAN bus controllers, several CAN bus controllers may expect to filter the same messages. In this case, sharing the filter SRAM can save more resources than using the filter registers exclusively for the CAN bus controllers. It is also possible that different CAN bus controllers expect different numbers of IDs to be filtered, or some CANs do not work, so there is no need to configure filters. If each CAN bus controller is allocated a fixed capacity, it will cause problems such as waste of resources and inconvenience in application.

Summary of the invention

Based on the above problems, the purpose of the present invention is to realize dynamic management of acceptance filter SRAM and allocate it to multiple CAN bus controllers. SRAM space can be allocated according to demand, thereby fully utilizing the SRAM space, reducing system area and power consumption, and avoiding resource waste.

The technical solution adopted by the present invention to achieve its invention object is a CAN bus controller system capable of dynamically managing filter SRAM, comprising an interface management module, an acceptance filter control module, an acceptance filter SRAM, a bus controller initialization module and n CAN bus controllers, wherein:

The interface management module is used to initialize the CAN bus controller through the CAN bus controller initialization module, and to initialize the acceptance filter through the acceptance filter control module, and to configure the internal register according to the corresponding address, data, and control signal by controlling the external input signal;

The acceptance filter control module is used to control the allocation of the acceptance filter SRAM according to the external configuration, and compare the data of the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL, and FDF to determine whether to receive the message; the acceptance filter control module is also connected to the CAN bus controller;

The acceptance filter SRAM is used to store the externally configured ID for filtering, i.e., the filtering reference value and the filtering mask;

The CAN bus controller initialization module is connected to the CAN bus controller and is used to complete the initialization of the CAN bus controller according to the external configuration;

The CAN bus controller is a standard CAN bus controller or an FDCAN bus controller, and the maximum value of n is 32.

Further, the CAN bus controller includes a transmit buffer, a receive FIFO, a bit stream processor, and a bit timing logic, wherein:

The sending buffer is used to store externally written frame messages to be sent;

The receiving FIFO is used to store messages received from the CAN bus and passed the acceptance filter;

The bit stream processor is used to control the data flow between the sending buffer, the receiving FIFO and the CAN bus; when the CAN bus controller is in the sending mode, when the sending request is set, the frame message in the sending buffer is sent according to the frame format of the CAN standard; when the CAN bus controller is in the receiving mode, the message is received from the CAN bus, and the frame ID is sent to the acceptance filter controller, and when the acceptance filter indicates that the filter has passed, the received message is sent to the receiving FIFO for storage;

The bit timing logic is used to monitor the CAN bus and process the bit timing related to the CAN bus.

Furthermore, the acceptance filter control module includes a filter starting group register, a filter mode register, and a filter processing unit, wherein:

The filter start group register is used to realize the allocation of the acceptance filter SRAM according to the start filter group of each CAN bus controller configured externally;

The filter mode register is 32 bits, and each bit controls the filter mode of each group of filters, which is divided into ID complete match filter mode or ID mask filter mode according to the external configuration mode;

The filtering processing unit is used to compare the data in the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL and FDF to determine whether to receive the message.

As a further preferred solution, the filter start group register can be configured externally to have the same value or different values for the start addresses of different CAN bus controllers according to requirements;

If different CAN bus controllers expect to filter the same message, they are configured with the same value to achieve SRAM data sharing;

If different CAN bus controllers are expected to filter different messages, they are configured with different values to achieve dynamic allocation of SRAM.

As another preferred solution, when the filtering processing unit works in the ID complete match filtering mode, after receiving the received message ID transmitted by the bit stream processor, if the message is a standard frame, the 11-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message are compared with the filtering reference value read out of the SRAM; if the message is an extended frame, the 29-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message need to be compared with the filtering reference value read out of the SRAM; if it is a complete match, the filtering is passed, and the match flag is pulled high and transmitted to the CAN bus controller, indicating that the message is stored in the receive FIFO; otherwise, the message does not pass the filtering, and the match flag remains low, indicating that the message does not need to be stored in the receive FIFO;

When the filtering processing unit works in the ID mask filtering mode, after receiving the received message ID transmitted by the bit stream processor, the filtering reference value and filtering mask of the SRAM are read out; the filtering mask indicates whether the ID and IDE, RTR, EDL, and FDF of the received message need to be matched with the filtering reference value; a filtering mask of 1 indicates that the bit must be consistent with the content in the filtering reference value to pass the filtering, and a filtering mask of 0 indicates that the bit is not compared; if the message is a standard frame, even if the corresponding bits of the EXID of the filtering mask and the filtering reference value are both 1, since the standard frame ID does not have an EXID, the filtering mask and the EXID of the filtering reference value do not participate in the filtering. In this mode, the mask control is used to select whether to pay attention to the IDE, RTR, EDL, and FDF of the received message; if the filtering is passed, the matching flag is pulled high and transmitted to the CAN bus controller, indicating that the message is stored in the receiving FIFO; otherwise, the message does not pass the filtering, and the matching flag remains low, indicating that the message does not need to be stored in the receiving FIFO.

Furthermore, the acceptance filter SRAM is divided into SRAM0 and SRAM1. The two SRAMs have the same size of 32x32bit, totaling 128Byte. The filter data of the same depth are grouped together, totaling 32 groups. In the ID mask filtering mode, SRAM0 and SRAM1 store 32-bit filtering reference values and 32-bit filtering masks respectively. In the ID complete match filtering mode, SRAM0 and SRAM1 both store 32-bit filtering reference values.

The beneficial effects of the present invention are:

A dynamically managed acceptance filter SRAM shared by multiple CAN or FDCAN bus controllers is provided. When in use, the starting address of the filter SRAM space of each CAN or FDCAN bus controller is used for division, so that the acceptance filter SRAM filter data can be shared and dynamically allocated, so as to make full use of SRAM resources, reduce system area and power consumption, and avoid resource waste.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a conventional CAN bus controller system;

FIG2 is a schematic diagram of a CAN bus controller system according to an embodiment of the present invention;

FIG3 is a schematic diagram of a CAN bus controller according to an embodiment of the present invention;

FIG4 is a schematic diagram of an acceptance filter control module according to an embodiment of the present invention;

5 is a schematic diagram of SRAM sharing and dynamic allocation of acceptance filters according to an embodiment of the present invention;

6 is a data mapping diagram of the SRAM perfect matching filter mode of the acceptance filter according to an embodiment of the present invention;

7 is a data mapping diagram of the SRAM mask filtering mode of the acceptance filter according to an embodiment of the present invention;

FIG8 is a schematic diagram of a conventional CAN bus controller system communication flow;

FIG. 9 is a schematic diagram of the communication flow of the CAN bus controller system according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

2 to 7 and 9 show a specific implementation of the CAN bus controller system capable of dynamically managing the filter SRAM of the present invention: comprising an interface management module, an acceptance filter control module, an acceptance filter SRAM, a bus controller initialization module and n CAN bus controllers, wherein:

The interface management module is used to initialize the CAN bus controller through the CAN bus controller initialization module, and to initialize the acceptance filter through the acceptance filter control module, and to configure the internal register according to the corresponding address, data, and control signal by controlling the external input signal;

The acceptance filter control module is used to control the allocation of the acceptance filter SRAM according to the external configuration, and compare the data of the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL, and FDF to determine whether to receive the message;

The acceptance filter SRAM is used to store the externally configured ID for filtering, i.e., the filtering reference value and the filtering mask;

The CAN bus controller initialization module is connected to the CAN bus controller and is used to complete the initialization of the CAN bus controller according to the external configuration;

The CAN bus controller is a standard CAN bus controller or a FDCAN bus controller, and n is 32.

In this embodiment, the CAN bus controller includes a sending buffer, a receiving FIFO, a bit stream processor, and a bit timing logic, wherein:

The sending buffer is used to store externally written frame messages to be sent;

The receiving FIFO is used to store messages received from the CAN bus and passed the acceptance filter;

The bit stream processor is used to control the data flow between the sending buffer, the receiving FIFO and the CAN bus; when the CAN bus controller is in the sending mode, when the sending request is set, the sending buffer frame message is sent according to the frame format of the CAN standard; when the CAN bus controller is in the receiving mode, the message is received from the CAN bus, and the frame ID is sent to the acceptance filter controller, and when the acceptance filter indicates that the filter has passed, the received message is sent to the receiving FIFO for storage;

The bit timing logic is used to monitor the CAN bus and process the bit timing related to the CAN bus.

In this embodiment, the acceptance filter control module includes a filter starting group register, a filter mode register, and a filter processing unit, wherein:

The filter start group register is used to realize the allocation of the acceptance filter SRAM according to the start filter group of each CAN bus controller configured externally;

The filter start group register can be configured externally to have the same value or different values for the start addresses of different CAN bus controllers according to requirements;

If different CAN bus controllers expect to filter the same message, they are configured with the same value to achieve SRAM data sharing;

If different CAN bus controllers are expected to filter different messages, they are configured with different values to achieve dynamic allocation of SRAM.

As shown in FIG5 , CAN2 and CAN3 controllers share SRAM data, and other controllers exclusively use SRAM data to implement dynamic SRAM allocation. Other shared data and dynamically allocated SRAM data can configure the corresponding filter start group registers to appropriate values according to requirements.

The filter mode register is 32 bits, and each bit controls the filter mode of each group of filters, which is divided into ID complete match filter mode or ID mask filter mode according to the external configuration mode;

The filter processing unit is used to compare the data in the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL and FDF to determine whether to receive the message. The filter processing unit is connected to the bit stream processor in the CAN bus controller.

When the filtering processing unit works in the ID complete match filtering mode, after receiving the received message ID transmitted by the bit stream processor, if the message is a standard frame, the 11-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message are compared with the filtering reference value read out of the SRAM; if the message is an extended frame, the 29-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message need to be compared with the filtering reference value read out of the SRAM; if it is completely matched, it passes the filtering, pulls up the match flag and transmits it to the CAN bus controller, indicating that the message is stored in the receiving FIFO; otherwise, the message does not pass the filtering, and the match flag remains low, indicating that the message does not need to be stored in the receiving FIFO;

When the filtering processing unit works in the ID mask filtering mode, after receiving the received message ID transmitted by the bit stream processor, the filtering reference value and filtering mask of the SRAM are read out; the filtering mask indicates whether the ID and IDE, RTR, EDL, and FDF of the received message need to be matched with the filtering reference value; the filtering mask is 1, indicating that the bit must be consistent with the content in the filtering reference value to pass the filtering, and the filtering mask is 0, indicating that the bit is not compared; if the message is a standard frame, even if the corresponding bits of the EXID of the filtering mask and the filtering reference value are both 1, since the standard frame ID does not have EXID, the filtering mask and the EXID of the filtering reference value do not participate in the filtering. In this mode, the mask control is used to select whether to pay attention to the IDE, RTR, EDL, and FDF of the received message; if the filtering is passed, the matching flag is pulled high and transmitted to the CAN bus controller, indicating that the message is stored in the receiving FIFO; otherwise, the message does not pass the filtering, and the matching flag remains low, indicating that the message does not need to be stored in the receiving FIFO.

In this embodiment, the acceptance filter SRAM is divided into SRAM0 and SRAM1. The two SRAMs have the same size of 32x32bit, totaling 128Byte. The filter data of the same depth are grouped together, totaling 32 groups. In the ID mask filtering mode, SRAM0 and SRAM1 store 32-bit filtering reference values and 32-bit filtering masks respectively. In the ID complete match filtering mode, SRAM0 and SRAM1 both store 32-bit filtering reference values.

FIG9 shows the CAN bus controller communication process of this embodiment, wherein the main process of filter initialization is as follows:

1) Configure the current CAN bus controller system filter start group register;

2) Configure the filter mode register, each bit controls the data filtering mode of each group of filters, which is divided into ID complete match filtering mode or ID mask filtering mode;

3) Initialize SRAM0 and SRAM1.

The above embodiments of the present invention are merely examples for illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes and modifications can be made based on the above description. It is impossible to list all the embodiments here. Any obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims (6)

1. A CAN bus controller system capable of dynamically managing filter SRAM, characterized in that it comprises an interface management module, an acceptance filter control module, an acceptance filter SRAM, a bus controller initialization module and n CAN bus controllers, wherein: The interface management module is used to initialize the CAN bus controller through the CAN bus controller initialization module, and to initialize the acceptance filter through the acceptance filter control module, and to configure the internal register according to the corresponding address, data, and control signal by controlling the external input signal; The acceptance filter control module is used to control the allocation of the acceptance filter SRAM according to the external configuration, and compare the data of the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL, and FDF to determine whether to receive the message; The acceptance filter SRAM is used to store the externally configured ID for filtering, i.e., the filtering reference value and the filtering mask; The CAN bus controller initialization module is connected to the CAN bus controller and is used to complete the initialization of the CAN bus controller according to the external configuration; The CAN bus controller is a standard CAN bus controller or an FDCAN bus controller, and the maximum value of n is 32. 2. A CAN bus controller system capable of dynamically managing filter SRAM according to claim 1, characterized in that the CAN bus controller comprises a sending buffer, a receiving FIFO, a bit stream processor, and a bit timing logic, wherein: The sending buffer is used to store externally written frame messages to be sent; The receiving FIFO is used to store messages received from the CAN bus and passed the acceptance filter; The bit stream processor is used to control the data flow between the sending buffer, the receiving FIFO and the CAN bus; when the CAN bus controller is in the sending mode, when the sending request is set, the sending buffer frame message is sent according to the frame format of the CAN standard; when the CAN bus controller is in the receiving mode, the message is received from the CAN bus, and the frame ID is sent to the acceptance filter controller, and when the acceptance filter indicates that the filter has passed, the received message is sent to the receiving FIFO for storage; The bit timing logic is used to monitor the CAN bus and process the bit timing related to the CAN bus. 3. A CAN bus controller system capable of dynamically managing filter SRAM according to claim 2, characterized in that the acceptance filter control module comprises a filter start group register, a filter mode register, and a filter processing unit, wherein: The filter start group register is used to realize the allocation of the acceptance filter SRAM according to the start filter group of each CAN bus controller configured externally; The filter mode register is 32 bits, and each bit controls the filter mode of each group of filters, which is divided into ID complete match filter mode or ID mask filter mode according to the external configuration mode; The filtering processing unit is used to compare the data in the acceptance filter SRAM with the received ID and the contents of IDE, RTR, EDL and FDF to determine whether to receive the message. 4. A CAN bus controller system capable of dynamically managing filter SRAM according to claim 3, characterized in that: the filter start group register can be configured by an external device to have the same value or different values for the start addresses of different CAN bus controllers according to requirements; If different CAN bus controllers expect to filter the same message, they are configured with the same value to achieve SRAM data sharing; If different CAN bus controllers are expected to filter different messages, they are configured with different values to achieve dynamic allocation of SRAM. 5. A CAN bus controller system capable of dynamically managing filter SRAM according to claim 3, characterized in that: When the filtering processing unit works in the ID complete match filtering mode, after receiving the received message ID transmitted by the bit stream processor, if the message is a standard frame, the 11-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message are compared with the filtering reference value read out of the SRAM; if the message is an extended frame, the 29-bit ID and the contents of IDE, RTR, EDL, and FDF of the received message need to be compared with the filtering reference value read out of the SRAM; if it is completely matched, it passes the filtering, pulls up the matching flag and transmits it to the CAN bus controller, indicating that the message is stored in the receiving FIFO; otherwise, the message does not pass the filtering, and the matching flag remains low, indicating that the message does not need to be stored in the receiving FIFO; When the filtering processing unit works in the ID mask filtering mode, after receiving the received message ID transmitted by the bit stream processor, the filtering reference value and filtering mask of the SRAM are read out; the filtering mask indicates whether the ID and IDE, RTR, EDL, and FDF of the received message need to be matched with the filtering reference value; the filtering mask is 1, indicating that the bit must be consistent with the content in the filtering reference value to pass the filtering, and the filtering mask is 0, indicating that the bit is not compared; if the message is a standard frame, even if the corresponding bits of the EXID of the filtering mask and the filtering reference value are both 1, since the standard frame ID does not have EXID, the filtering mask and the EXID of the filtering reference value do not participate in the filtering. In this mode, the mask control is used to select whether to pay attention to the IDE, RTR, EDL, and FDF of the received message; if the filtering is passed, the matching flag is pulled high and transmitted to the CAN bus controller, indicating that the message is stored in the receiving FIFO; otherwise, the message does not pass the filtering, and the matching flag remains low, indicating that the message does not need to be stored in the receiving FIFO. 6. A CAN bus controller system capable of dynamically managing filter SRAM according to claim 1, characterized in that: the acceptance filter SRAM is divided into SRAM0 and SRAM1, the two SRAMs have the same size of 32x32bit, totaling 128Byte, filter data of the same depth are grouped together, totaling 32 groups, in ID mask filtering mode SRAM0 and SRAM1 store 32-bit filtering reference value and 32-bit filtering mask respectively, in ID complete match filtering mode, SRAM0 and SRAM1 both store 32-bit filtering reference value.