CN118611791B - Calibration circuit, chip and parameter calibration method - Google Patents

Abstract

The present application discloses a calibration circuit, a chip and a parameter calibration method, which belongs to the field of circuits. The calibration circuit provided by the present application includes a DFE circuit, a calibration control module and a data comparison module; the calibration control module is connected to the control end of the DFE circuit and is used to provide control information to the DFE circuit, and the control information is used to determine the feedback parameter of the DFE circuit; the data output end of the DFE circuit is connected to the first input end of the data comparison module, and the DFE circuit is used to process the first data input by the data input end based on the feedback parameter to obtain the second data, and output the second data to the first input end through the data output end; the data comparison module is used to determine the appropriate configuration value of the feedback parameter by comparing the second data with the random data received by the second input end; the random data is obtained based on the first data.

Description

A calibration circuit, a chip and a parameter calibration method

Technical Field

The present application belongs to the field of circuits, and specifically relates to a calibration circuit, a chip, and a parameter calibration method.

Background Art

Decision Feedback Equalizer (DFE) is often used in the receiving module (Receive, RX) in the input/output (I/O) interface. It can eliminate inter-symbol interference and effectively improve the receiving performance of the receiving module.

In order to minimize the impact of inter-symbol interference, the related art generally requires calibrating the feedback parameters of the DFE circuit to test stable and usable configuration values of the feedback parameters.

However, the feedback parameters are uncertain during the calibration process, and the feedback parameters may switch between multiple configuration parameters as the output data changes. Since multiple configuration parameters influence each other, the related technology generally needs to calibrate the configuration values of multiple configuration parameters of the DFE circuit at the same time, and there is a problem of low calibration efficiency of the feedback parameters of the DFE circuit. For example, as shown in Figure 1, for a first-order DFE circuit, the feedback parameter Y may switch between two configuration parameters (Y0, Y1) as the output data changes. During the calibration of the feedback parameter Y, it is necessary to test the stable and available configuration values of the two configuration parameters (Y0, Y1). Since the configuration parameters influence each other during the calibration process, the related technology needs to traverse multiple permutations and combinations of the configuration values of the configuration parameters (Y0, Y1) to test the available configuration values of the feedback parameters. It is difficult to quickly find the stable and available configuration values of the feedback parameters, and the calibration efficiency is low.

Summary of the invention

The embodiments of the present application provide a calibration circuit, a chip, and a parameter calibration method, which can solve the problem of low calibration efficiency of feedback parameters of a DFE circuit in the related art.

In a first aspect, an embodiment of the present application provides a calibration circuit, including: a DFE circuit, a calibration control module, and a data comparison module; the DFE circuit has a data input terminal, a control terminal, and a data output terminal, and the data comparison module has a first input terminal and a second input terminal;

The calibration control module is connected to the control terminal of the DFE circuit and is used to provide control information to the DFE circuit, where the control information is used to determine feedback parameters of the DFE circuit;

The data output terminal of the DFE circuit is connected to the first input terminal of the data comparison module, and the DFE circuit is used to process the first data inputted from the data input terminal based on the feedback parameter to obtain the second data, and output the second data to the first input terminal through the data output terminal;

The data comparison module is used to determine the appropriate configuration value of the feedback parameter by comparing the second data with the random data received at the second input terminal; the random data is obtained based on the first data.

In a second aspect, an embodiment of the present application provides a chip, which includes the calibration circuit described in the first aspect.

In a third aspect, an embodiment of the present application provides a parameter calibration method, the method comprising:

Acquire control information, and determine feedback parameters of the DFE circuit based on the control information;

Processing first data inputted from a data input terminal of the DFE circuit based on the feedback parameter to obtain second data;

By comparing the second data with random data, a suitable configuration value of the feedback parameter is determined; the random data is obtained based on the first data.

In an embodiment of the present application, the calibration circuit includes a DFE circuit, a calibration control module and a data comparison module; the DFE circuit has a data input terminal, a control terminal and a data output terminal, and the data comparison module has a first input terminal and a second input terminal; the calibration control module is connected to the control terminal of the DFE circuit and is used to provide control information to the DFE circuit, and the control information is used to determine the feedback parameter of the DFE circuit; the data output terminal of the DFE circuit is connected to the first input terminal of the data comparison module, and the DFE circuit is used to process the first data input by the data input terminal based on the feedback parameter to obtain the second data, and output the second data to the first input terminal through the data output terminal; the data comparison module is used to determine the appropriate configuration value of the feedback parameter by comparing the second data with the random data received by the second input terminal; the random data is obtained based on the first data. In this way, in the process of the calibration circuit calibrating the feedback parameter of the DFE circuit, the feedback parameter of the DFE circuit is determined by the control information provided by the calibration control module. Compared with the related art, it can avoid the feedback parameter from switching between multiple configuration parameters as the output second data changes, thereby avoiding the mutual influence between multiple configuration parameters during the calibration process, thereby quickly determining the appropriate configuration value of the feedback parameter, and improving the calibration efficiency of the feedback parameter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a first-order DFE circuit provided in the related art;

FIG2 is a schematic structural diagram of a calibration circuit provided in an embodiment of the present application;

FIG3 is a schematic structural diagram of another calibration circuit provided in an embodiment of the present application;

FIG4 is a schematic structural diagram of another calibration circuit provided in an embodiment of the present application;

FIG5 is a schematic structural diagram of another calibration circuit provided in an embodiment of the present application;

FIG6 is a schematic structural diagram of a chip provided in an embodiment of the present application;

FIG7 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG8 is a schematic flow chart of a parameter calibration method provided in an embodiment of the present application;

FIG9 is a schematic flow chart of another parameter calibration method provided in an embodiment of the present application;

FIG10 is a schematic flow chart of another parameter calibration method provided in an embodiment of the present application;

FIG. 11 is a schematic flowchart of yet another parameter calibration method provided in an embodiment of the present application.

Description of reference numerals:

10-calibration circuit; 100-DFE circuit; 110-analog circuit; 120-D flip-flop; 130-selector; 200-calibration control module; 300-data comparison module; 310-target D flip-flop; 400-data alignment module; 600-chip; 700-electronic device; Input-external input data; Y-feedback parameter; Y0-configuration parameter; Y1-configuration parameter; Y2n ^- 1-configuration parameter; d0-digital signal; golden_data-first data; golden_rx-random data; golden_rx_d-third data; d1-second data; {dn,…,d2,d1}-sampling data; Clock-clock signal; f-feedback data; m-control information; training_mode-control instruction.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and/or" in the specification and claims represents at least one of the connected objects, and the character "/" generally indicates that the objects associated with each other are in an "or" relationship.

DFE is commonly used in the receiving module of the I/O interface. It can eliminate inter-symbol interference and effectively improve the receiving performance of the receiving module. Among them, inter-symbol interference refers to the tailing phenomenon of the time domain response of the signal transmission channel, which will affect the next code element. In the time domain, DFE can eliminate all subsequent effects of the current code element in turn according to the judgment result of the current code element, thereby minimizing the inter-symbol interference effect of the current code element or even completely eliminating it. In circuit implementation, DFE can be implemented through a digital high-frequency filter. For example, for continuous input data, the input data sampled after a T-period delay is added with a weight, and then added to the current input data and output, thereby reducing or completely eliminating the inter-symbol interference of the input data.

For example, as shown in FIG. 1 , the working principle of the DFE circuit 100 may be: the analog circuit 110 converts the external input data Input into a digital signal d0 ; and the D flip-flop 120 samples the digital signal d0 and outputs the sampled data d1 .

At the same time, the control end of the selector 130 can receive the feedback data f, and the sampled data d1 can be used as the feedback data f to adjust the feedback parameter Y of the previous analog circuit 110. Specifically, when the sampled data d1 is 0, the feedback data f=d1=0, and the selector 130 can select the configuration parameter Y0 as the feedback parameter Y according to the feedback data f being 0. When the sampled data d1 is 1, the feedback data f=d1=1, and the selector 130 can select the configuration parameter Y1 as the feedback parameter Y according to the feedback data f being 1.

The current sampling data d1 can be understood as the digital signal d0 of the previous clock, and the feedback parameter Y can include but is not limited to at least one of a voltage feedback parameter and a delay feedback parameter. The feedback parameter Y can be used to convert the input data Input to obtain the digital signal d0.

In order to minimize the impact of inter-symbol interference on input data, the configuration parameters of the DFE circuit may be calibrated in the related art. Specifically, stable, available or optimal configuration values of two configuration parameters Y0 and Y1 need to be found through testing.

It should be pointed out that after modifying the configuration value of Y0 or Y1, the correctness of the next input data d0 is directly affected. For multiple consecutive input data, since the configuration parameters (such as Y0, Y1) affect each other during the calibration process, it is impossible to know whether one configuration parameter in the current configuration {Y0, Y1} is incorrectly configured or all configuration parameters are incorrectly configured. If the configuration value of Y0 or Y1 is modified separately, it is not easy to find the appropriate configuration value of {Y0, Y1}. For example: only modify the configuration value of Y0, d1=0 at the current moment, if the configuration value of Y0 is wrong, the correctness of the d0 data will be uncertain; in the next clock, d0 is saved as d1 (d1<= d0), the correctness of d1 is uncertain, the feedback parameter Y fed back by d1 is uncertain, and the subsequent output d0 is uncertain.

Based on this, since the configuration parameters (such as Y0, Y1) affect each other during the calibration process, the related technology generally needs to test the configuration values of multiple configuration parameters (such as Y0 and Y1) at the same time. For example, Y0 has 10 candidate configuration values and Y1 has 10 candidate configuration values. The related technology needs to traverse 10*10 permutations and combinations of (Y0, Y1) to find the available configuration values of the configuration parameters (Y0, Y1). It is difficult to quickly find stable and available configuration values of the configuration parameters, and the calibration efficiency is low.

In order to solve the problem of low calibration efficiency of feedback parameters of the DFE circuit in the related art, an embodiment of the present application provides a calibration circuit, which determines the feedback parameters of the DFE circuit through control information output by a calibration control module. Compared with the related art, it can avoid the feedback parameters from switching between multiple configuration parameters as the output second data changes, thereby avoiding the mutual influence between multiple configuration parameters during the calibration process, thereby quickly determining the appropriate configuration value of the feedback parameter, and improving the calibration efficiency.

For example, in the embodiment of the present application, the selector of the DFE circuit can be controlled by the calibration control module to select a target configuration parameter from multiple configuration parameters as a feedback parameter of the DFE circuit. One target configuration parameter can be calibrated separately to obtain a suitable configuration value of the target configuration parameter, thereby avoiding the influence of other configuration parameters during the calibration process of the target configuration parameter. Then, suitable configuration values of each configuration parameter can be determined separately, thereby quickly determining suitable configuration values of multiple configuration parameters and improving the calibration efficiency of the feedback parameters.

The calibration circuit and parameter calibration method provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

As shown in FIG. 2 , the calibration circuit 10 provided in the embodiment of the present application may include:

DFE circuit 100, calibration control module 200 and data comparison module 300;

The DFE circuit 100 has a data input terminal, a control terminal and a data output terminal, and the data comparison module 300 has a first input terminal and a second input terminal;

The calibration control module 200 is connected to the control terminal of the DFE circuit 100 and is used to provide control information to the DFE circuit 100, where the control information is used to determine feedback parameters of the DFE circuit;

The data output terminal of the DFE circuit 100 is connected to the first input terminal of the data comparison module 300, and the DFE circuit 100 is used to process the first data inputted from the data input terminal of the DFE circuit 100 based on the feedback parameter to obtain the second data, and output the second data to the first input terminal of the data comparison module 300 through the data output terminal of the DFE circuit 100;

The data comparison module 300 is used to determine a suitable configuration value of the feedback parameter by comparing the second data with the random data received at the second input terminal; wherein the random data is obtained based on the first data.

Referring to FIG. 1 , it should be noted that in the normal working mode of the DFE circuit 100 , the value of the second data output by the DFE circuit 100 is not fixed. For example, if the second data d1 is 0 at the current moment, the feedback data f is 0, and the feedback parameter Y is Y0; if the second data d1 is 1 at the next clock, the feedback data f is 1, and the feedback parameter Y is Y1. It can be seen that in the normal working mode, the feedback parameter Y is not fixed, and the feedback parameter Y can switch between Y0 and Y1 as the second data d1 changes. Based on this, when the configuration value of Y0 is calibrated separately in the normal working mode in the related art, the accuracy of the calibrated configuration value of Y0 may be affected by the configuration value of Y1. Alternatively, when the configuration value of Y1 is calibrated separately in the normal working mode in the related art, the accuracy of the calibrated configuration value of Y1 may be affected by the configuration value of Y0. In other words, in the normal working mode of the DFE circuit 100 , if the calibration of a certain configuration parameter is affected by other configuration parameters in the related art, it is difficult to test the appropriate configuration value. If the configuration values of Y0 and Y1 are calibrated simultaneously in the normal working mode in the related technology, although the appropriate configuration value of (Y0, Y1) can be tested, many permutations and combinations of (Y0, Y1) need to be traversed during the calibration process, and the required calibration time is longer than calibrating each configuration parameter separately, and the calibration efficiency is low.

In the calibration circuit 10 provided in the embodiment of the present application, the feedback parameter Y may not change with the change of the second data outputted from the data output terminal of the DFE circuit 100, but may be determined by the control information m provided by the calibration control module 200. For example, in the calibration mode of the DFE circuit 100, the feedback data f may be determined by the control information m outputted by the calibration control module 200, and the feedback data f=m. In the calibration mode of the DFE circuit 100, although the value of the second data is still not fixed, in this calibration mode, the feedback data f is not determined by the second data, but may be determined by the control information m outputted by the calibration control module 200. Thus, in the calibration mode, the feedback parameter Y may always be equal to the target configuration parameter Ym, and may not change with the change of the second data.

Furthermore, in the embodiment of the present application, during the calibration process of the feedback parameters, the feedback parameters of the DFE circuit are determined by the control information provided by the calibration control module. Compared with the related art, it is possible to avoid the feedback parameters from switching between multiple configuration parameters as the output second data changes, thereby avoiding the mutual influence between multiple configuration parameters during the calibration process, thereby quickly determining the appropriate configuration value of the feedback parameter and improving the calibration efficiency of the feedback parameter.

It should be noted that the feedback parameter of the DFE circuit can be selected from multiple configuration parameters of the DFE circuit, and therefore, determining the appropriate configuration value of the feedback parameter includes determining appropriate configuration values of the multiple configuration parameters respectively. The following is an example of the specific working principle of the DFE circuit.

As shown in FIG3 , in the calibration circuit 10 provided in the embodiment of the present application, the DFE circuit 100 may include an analog circuit 110, a D flip-flop 120 and a selector 130; the analog circuit 110 is connected to the D flip-flop 120, the D flip-flop 120 is connected to the first input terminal of the data comparison module 300, and the output terminal of the selector 130 is connected to the analog circuit 110; the control terminal of the selector 130 is connected to the calibration control module 200;

The selector 130 is used to receive the control information output by the calibration control module 200, select a target configuration parameter from a plurality of configuration parameters based on the control information, and use the target configuration parameter as the feedback parameter.

Among them, the selector 130 has multiple input terminals, a control terminal and an output terminal. The multiple input terminals of the selector 130 are used to receive multiple candidate configuration values of multiple configuration parameters, the control terminal of the selector 130 is used to receive control information output by the calibration control module 200, and the output terminal of the selector 130 is used to output the target configuration parameters as feedback parameters.

The feedback parameter may be used as a working parameter of the analog circuit 110 to reduce inter-symbol interference of the first data.

The control end of the DFE circuit 100 may specifically be a control end of the selector 130, and the control information is used to control the selector 130 to select a target configuration parameter from a plurality of configuration parameters, and use the target configuration parameter as a feedback parameter;

The analog circuit 110 is used to process the first data based on the feedback parameter to obtain a digital signal;

The D flip-flop 120 is used to sample the digital signal output by the analog circuit 110 to obtain sampled data, and use the sampled data as the second data.

In practical applications, for DFE circuits of different orders, the sampled data output by a D flip-flop 120 connected to the analog circuit 110 may be used as the second data.

For example, as shown in FIG. 3 , in a first-order DFE circuit, a D flip-flop 120 is connected to an analog circuit 110 , and the sampled data d1 outputted by the D flip-flop 120 is used as the second data.

For another example, as shown in FIG5 , in an n-stage DFE circuit, the sampling data output by the n D flip-flops 120 are {dn,…,d2,d1}, and the first D flip-flop 120 is connected to the analog circuit 110 , and the sampling data d1 output by the first D flip-flop 120 can be used as the second data.

The first data may be a string of known random data. For example, in practical applications, the DFE circuit 100 may be located at the receiving end, and the first data may be a string of known random data sent by the transmitting end to the DFE circuit of the receiving end.

In the embodiment of the present application, the calibration control module 200 can be used to control the selector 130 to select the target configuration parameter from multiple configuration parameters as the feedback parameter, so as to calibrate the target configuration parameter separately and avoid the influence of other configuration parameters on the target configuration parameter.

For example, the feedback parameter may be recorded as Y, and the target configuration parameter may be recorded as Ym; the calibration control module 200 may control the selector 130 to select Ym from a plurality of configuration parameters such that Y=Ym.

Here, 0≤m≤2 ⁿ −1, and n may be determined by the order of the DFE circuit 100 .

It should be noted that the calibration control module 200 can control the selector 130 to select the target configuration parameter Ym from multiple configuration parameters, determine the target configuration parameter Ym as the feedback parameter Y, and calibrate the target configuration parameter Ym alone to avoid the influence of other configuration parameters on the target configuration parameter Ym.

In the embodiment of the present application, when the feedback parameter Y is the target configuration parameter Ym, the data comparison module 300 is used to test multiple candidate configuration values of the target configuration parameter Ym to obtain a suitable configuration value of the target configuration parameter.

For example, when the feedback parameter is the target configuration parameter, when the target configuration parameter Ym is the first candidate configuration value, if the data comparison module 300 compares the second data and the random data and finds that they are the same, the first candidate configuration value can be determined as the appropriate configuration value of the target configuration parameter. The appropriate configuration value can be understood as a stable and available configuration value that can work normally. In the case where the feedback parameter is the target configuration parameter, when the target configuration parameter Ym is the second candidate configuration value, if the data comparison module 300 compares the second data and the random data and finds that they are different, then the second candidate configuration value is not the appropriate configuration value of the target configuration parameter.

In this way, through multiple calibrations, multiple candidate configuration values of the target configuration parameter are tested respectively to obtain appropriate configuration values of the target configuration parameter.

Furthermore, the target configuration parameter may be any one of multiple configuration parameters in the DFE circuit, and then each configuration parameter may be calibrated separately through multiple calibrations to obtain a suitable configuration value of each target configuration parameter, that is, a suitable configuration value of the feedback parameter.

In the embodiment of the present application, the working principle of the selector 130 is: if the feedback data f=m received by the selector 130, the selector 130 selects the target configuration parameter Ym corresponding to the feedback data as the feedback parameter Y from multiple configuration parameters.

As shown in FIG. 1 , in the normal working mode of the DFE circuit 100 , the feedback data f may be determined by the sampled data d1 output by the D flip-flop 120 of the DFE circuit 100 , and the feedback data f=d1 .

It should be pointed out that in the normal working mode, the value of the sampling data d1 is not fixed. For example, if the current sampling data d1 is 0, the feedback data f is 0, and the feedback parameter Y is Y0; if the next clock sampling data d1 is 1, the feedback data f is 1, and the feedback parameter Y is Y1. It can be seen that in the normal working mode, the feedback parameter Y is also not fixed, and the feedback parameter Y can be switched between Y0 and Y1. Based on this, when the configuration value of Y0 is calibrated separately in the normal working mode in the related art, the accuracy of the calibrated configuration value of Y0 may be affected by the configuration value of Y1. In other words, in the normal working mode of the DFE circuit, if the calibration of a certain configuration parameter is affected by other configuration parameters in the related art, it is difficult to test the appropriate configuration value. If the configuration values of Y0 and Y1 are calibrated at the same time in the normal working mode in the related art, although the appropriate configuration value of (Y0, Y1) can be tested, more permutations and combinations of (Y0, Y1) need to be traversed during the calibration process, and the required calibration time is longer than that of calibrating each configuration parameter separately, and the calibration efficiency is low.

It can be understood that in the calibration circuit 10 provided in the embodiment of the present application, as shown in FIG2 , in the calibration mode of the DFE circuit 100, although the value of the sampled data is still not fixed, in the calibration mode, the feedback data f is not determined by the sampled data, but can be determined by the control information m output by the calibration control module 200, and the feedback data f does not change with the change of the sampled data. Furthermore, in the calibration mode, the feedback parameter Y can always be equal to the target configuration parameter Ym, and will not change with the change of the sampled data. Based on this, the embodiment of the present application can calibrate the configuration value of the target configuration parameter Ym alone in the calibration mode, and the accuracy of the determined appropriate configuration value of Ym will not be affected by other configuration parameters.

In this way, in the calibration process of the feedback parameters in the embodiment of the present application, the calibration control module controls the selector to select the target configuration parameter as the feedback parameter from multiple configuration parameters, and the target configuration parameter is calibrated separately to obtain the appropriate configuration value of the target configuration parameter, thereby avoiding the influence of other feedback parameters during the calibration process of the target configuration parameter, and then the appropriate configuration value of each configuration parameter can be determined separately, thereby quickly determining the appropriate configuration values of multiple configuration parameters, thereby improving the calibration efficiency.

For example, in the related art, it is generally necessary to test the configuration values of multiple configuration parameters (such as Y0 and Y1) at the same time. For example, Y0 has 10 candidate values and Y1 has 10 candidate values. The related art needs to traverse 10*10 permutations and combinations of (Y0, Y1) to find the available configuration values of the configuration parameters (Y0, Y1). In the embodiment of the present application, during the calibration process of the configuration parameters, the calibration control module controls the selector to select Y0 as the feedback parameter, and calibrates Y0 10 times alone to obtain the appropriate configuration value of Y0; similarly, the calibration control module controls the selector to select Y1 as the feedback parameter, and calibrates Y1 10 times alone to obtain the appropriate configuration value of Y1. A total of 20 calibrations can be performed to obtain the appropriate configuration value of (Y0, Y1). Obviously, compared with the 100 tests required in the related art, the time required for 20 tests in the embodiment of the present application is significantly reduced, and the appropriate configuration value of the configuration parameter (Y0, Y1) can be quickly determined, thereby improving the calibration efficiency.

In actual applications, in the normal working mode of the DFE circuit 100, the feedback parameter Y of the analog circuit 110 at the current moment is determined by the sampled data d1 outputted by the D flip-flop 120 at the previous clock. For example, if the feedback parameter Y at the current moment is Ym, it means that the sampled data d1 of the previous clock is m, and m is used as the feedback data f, and Ym is selected as the feedback parameter Y accordingly.

Based on this, in the process of calibrating the target configuration parameter Ym alone in the embodiment of the present application, the random data and the sampled data at the current moment can be compared to see if they are the same when the random data input at the previous clock is the same as the control information m, without having to compare all the random data and sampled data input at all moments, so that the target configuration parameter Ym can be calibrated in a targeted manner, thereby improving the accuracy and efficiency of the configuration value of the target configuration parameter Ym. An example is given below.

In a specific embodiment, in order to improve the accuracy of the configuration value of the target configuration parameter Ym, as shown in FIG3 , the data comparison module 300 may include a target D flip-flop 310, the input end of the target D flip-flop 310 is connected to the second input end of the data comparison module 300 to receive the random data golden_rx, and the target D flip-flop 310 is used to sample the random data golden_rx and output the third data golden_rx_d;

The random data golden_rx can be understood as random data at the current moment, and the third data golden_rx_d can be understood as random data at the previous clock.

The data comparison module 300 can be used to determine a suitable configuration value of the feedback parameter Y by comparing the second data (ie, the sampled data d1 ) output by the D flip-flop 120 with the random data golden_rx received by the target D flip-flop 310 when the third data golden_rx_d is the same as the control information m.

Specifically, when the third data golden_rx_d is the same as the control information m, the data comparison module 300 can determine the appropriate configuration value of the target configuration parameter Ym by comparing whether the sampled data d1 output by the D flip-flop 120 is the same as the random data golden_rx received by the target D flip-flop 310 .

In an embodiment of the present application, the calibration process of the target configuration parameter Ym may include: the calibration control module 200 controls the selector 130 to select the target configuration parameter Ym as the feedback parameter Y from the configuration parameters Y0 and Y1, and Ym may be Y0 or Y1; the analog circuit 110 converts the first data golden_data based on the feedback parameter Y to obtain the digital signal d0; the D flip-flop 120 samples the digital signal d0 output by the analog circuit 110 to obtain the sampled data d1; the data comparison module 300 determines the appropriate configuration value of the target configuration parameter Ym by comparing whether the sampled data d1 output by the D flip-flop 120 is the same as the random data golden_rx received by the target D flip-flop 310 when the feedback parameter Y is the target configuration parameter Ym and when the third data golden_rx_d is the same as the control information m.

The clock signal Clock of the D flip-flop 120 and the clock signal Clock of the target D flip-flop 310 have the same frequency, and can be understood as the same clock signal.

In this way, during the process of calibrating the target configuration parameter Ym alone in the embodiment of the present application, the data comparison module 300 can compare whether the random data golden_rx and the second data (i.e., the sampling data d1) are the same when the third data golden_rx_d is the same as the control information m, without having to compare all the random data and sampling data input at all times, so that the target configuration parameter Ym can be calibrated in a targeted manner, thereby improving the accuracy and efficiency of the configuration value of the target configuration parameter Ym.

In practical applications, in order to accurately compare the random data golden_rx input to the data comparison module 300 with the second data d1 output to the data comparison module 300 by the D flip-flop 120, the phases of the random data golden_rx input to the data comparison module 300 and the second data d1 output to the data comparison module 300 by the D flip-flop 120 can be aligned.

In a specific embodiment, the first data golden_data input to the data input terminal of the DFE circuit 100 and the random data golden_rx input to the second input terminal of the data comparison module 300 may come from the same string of random data, and the random data golden_rx input to the second input terminal of the data comparison module 300 may be phase-aligned with the second data d1 output from the data output terminal of the DFE circuit.

Alternatively, in another specific embodiment, when the phases of the random data input to the second input end of the data comparison module 300 and the second data d1 output from the data output end of the DFE circuit are not aligned, the present application may perform phase adjustment processing on the first data golden_data to obtain the phase-adjusted random data golden_rx, so that the phases of the phase-adjusted random data golden_rx are aligned with the second data d1.

In a specific embodiment, as shown in FIG. 4 or FIG. 5 , the calibration circuit provided in the embodiment of the present application may further include a data alignment module 400; the data alignment module 400 is connected to the second input end of the data comparison module 300; the data alignment module 400 is used to perform phase adjustment on the first data golden_data to obtain random data golden_rx, so that the phase of the random data golden_rx is aligned with the second data d1 outputted from the data output end of the DFE circuit.

For example, as shown in FIG. 4 , when the DFE circuit 100 is a first-order DFE circuit, the data alignment module 400 performs phase adjustment on the first data golden_data to obtain random data golden_rx, so that the phase of the random data golden_rx is aligned with the sampling data d1 outputted from the data output terminal of the DFE circuit.

For another example, as shown in FIG5 , when the DFE circuit 100 is an n-order DFE circuit, the data alignment module 400 performs phase adjustment on the random data golden_data to obtain the random data golden_rx, so that the phase of the random data golden_rx is aligned with the second data output from the data output end of the DFE circuit (i.e., the sampling data d1 output by the first D flip-flop 120).

The data alignment module 400 may include a device with a data alignment function such as a delay circuit or a D flip-flop, and the present application does not limit the specific structure of the data alignment module.

In this way, the data alignment module 400 aligns the phase of the random data golden_rx with the second data d1 output by the D flip-flop 120 to the data comparison module 300, so that the random data golden_rx and the second data d1 can be accurately compared, which is suitable for the case where a deviation occurs during data transmission.

In this way, in an application scenario where an offset occurs during data transmission, the present application can use a data alignment module to phase-align the random data received by the data comparison module with the sampled data collected by the DFE circuit. Then, the data comparison module can use the random data after phase alignment to compare the data with the sampled data collected by the DFE circuit, thereby preventing the accuracy of the data comparison module from being affected by the offset phenomenon during data transmission, thereby ensuring the accuracy of the data comparison performed by the data comparison module.

In practical applications, the number of configuration parameters of the DFE circuit 100 is different for different orders of the DFE circuit 100. The DFE circuit 100 may include an n-order DFE circuit, where n is a positive integer; in the n-order DFE circuit, the number of D flip-flops 120 may be n, and the first D flip-flop 120 is connected to the analog circuit 110; when n is greater than 1, the n D flip-flops 120 are connected in series in sequence; the number of configuration parameters of the DFE circuit 100 is ²ⁿ .

For example, as shown in FIGS. 3 and 4 , when n is equal to 1, the DFE circuit 100 is a first-order DFE circuit, and the sampled data output by the DFE circuit 100 is d1, where d1 is a binary number and d1 can be 0 or 1. Correspondingly, the configuration parameters of the DFE circuit 100 include two: Y0 and Y1.

For another example, as shown in FIG5 , when n is greater than 1, the DFE circuit 100 is an n-order DFE circuit, and the sampled data output by the DFE circuit 100 is {dn, …, d2, d1}, {dn, …, d2, d1} is an n-bit binary number, d1 is the lowest bit of the sampled data {dn, …, d2, d1}, and each of the n bits can be 0 or 1, and the corresponding {dn, …, d2, d1} can be 0, 1, 2, …, 2 ⁿ -1. Correspondingly, the configuration parameters of the DFE circuit 100 include 2 ⁿ : Y0, Y1, Y2, …, Y2 ⁿ -1.

Furthermore, for different DFE circuits 100, the embodiment of the present application can calibrate the configuration parameters of different DFE circuits 100. For an n-th order DFE circuit, the calibration control module 200 can be used to control the selector 130 to select the target configuration parameter Ym as the feedback parameter Y from ²ⁿ configuration parameters.

For example, as shown in FIG. 3 , the DFE circuit 100 includes a first-order DFE circuit, in which the number of D flip-flops 120 is one and the number of configuration parameters is two; the calibration control module 200 may be used to control the selector 130 to select a target configuration parameter from the two configuration parameters as a feedback parameter.

For example, when the DFE circuit 100 is a first-order DFE circuit, the calibration control module 200 may output control information m as feedback data f, 0≤m≤1; the configuration parameters of the first-order DFE circuit may include Y0 and Y1, and the calibration control module 200 may control the selector 130 to select the target configuration parameter from Y0 and Y1, so as to calibrate the target configuration parameter Y0 alone to avoid the influence of the configuration parameter Y1 on the target configuration parameter Y0, or to calibrate the target configuration parameter Y1 alone to avoid the influence of the configuration parameter Y0 on the target configuration parameter Y1.

For another example, as shown in FIG5 , the DFE circuit 100 includes an n-stage DFE circuit, where n is an integer greater than 1; in the n-stage DFE circuit, the number of D flip-flops 120 is n, the first D flip-flop 120 is connected to the analog circuit 110, and the n D flip-flops 120 are connected in series in sequence;

The second data is the sampled data output by the first D flip-flop 120 , and the calibration control module 200 can be used to control the selector 130 to select the target configuration parameter Ym as the feedback parameter Y from the 2 ⁿ configuration parameters.

Among them, the sampled data {dn,…,d2,d1} output by n D flip-flops is an n-bit binary number;

The sampling data d1 output by the first D flip-flop may be used as the second data.

For example, when the DFE circuit 100 is an n-order (n is greater than 1)-order DFE circuit, the calibration control module 200 may output control information m as feedback data f, 0≤m≤2n ^- 1; the configuration parameters of the n-order DFE circuit may include Y0, Y1, Y2, ..., Y2n ^- 1, and the calibration control module 200 may control the selector 130 to select the target configuration parameter Ym from Y0, Y1, Y2, ..., ^Y2n -1 to calibrate the target configuration parameter Ym alone, thereby avoiding the influence of other configuration parameters on the target configuration parameter Ym.

As shown in FIG5 , when the DFE circuit 100 is an n-stage DFE circuit, the data comparison module 300 may include n target D flip-flops 310 ; when n is greater than 1, the n target D flip-flops 310 are connected in sequence; the input end of the first target D flip-flop 310 is used for the random data golden_rx; the n target D flip-flops 310 are used to output the third data golden_PRE;

The third data golden_PRE is an n-bit binary number, which can be expressed as {golden_rx_dn, ..., golden_rx_d2, golden_rx_d1};

The data comparison module 300 may be used to determine a suitable configuration value of the target configuration parameter Ym by comparing whether the second data d1 output by the first D flip-flop 120 is the same as the random data golden_rx when the third data golden_PRE is the same as the control information m.

In this way, in the process of calibrating the target configuration parameter Ym of the n-order DFE circuit alone in the embodiment of the present application, the random data golden_rx and the second data d1 can be compared to see whether they are the same when the third data golden_PRE is the same as the control information m, without having to compare all the random data and sampling data input at all times, so that the target configuration parameter Ym can be calibrated in a targeted manner to improve the accuracy of the configuration value of the target configuration parameter Ym.

In the embodiment of the present application, as shown in FIG. 3 or FIG. 5 , the data output end of the DFE circuit 100 is also connected to the calibration control module 200. The calibration control module 200 can also be used to control the data output end of the DFE circuit 100 to be connected to the control end of the DFE circuit 100 after determining a suitable configuration value of the feedback parameter, so that the DFE circuit enters a normal working mode.

Specifically, the DFE circuit 100 may include multiple configuration parameters. The calibration control module 200 may be used to control the data output end of the DFE circuit 100 to be connected with the control end of the DFE circuit 100 after determining appropriate configuration values of the multiple configuration parameters, so that the DFE circuit enters a normal working mode.

For example, as shown in FIG3 , in a first-order DFE circuit, the data output end of the DFE circuit 100 is the output end of the D flip-flop 120, and the control end of the DFE circuit 100 is the control end of the selector 130; the output end of the D flip-flop 120 is connected to the calibration control module 200, and the calibration control module 200 can also be used to control the output end of the D flip-flop 120 to be connected to the control end of the selector 130 after determining the appropriate configuration value of the configuration parameter (Y0, Y1), so that the DFE circuit enters a normal operating mode; in the normal operating mode, the feedback data f is equal to the sampled data d1 of the output of the D flip-flop 120, so as to ensure that the feedback mechanism of the DFE circuit 100 operates normally.

For another example, as shown in FIG5 , in an n-order DFE circuit, the data output end of the DFE circuit 100 is the output end of n D flip-flops 120, and the control end of the DFE circuit 100 is the control end of the selector 130; the output ends of the n D flip-flops 120 are connected to the calibration control module 200, and the calibration control module 200 can also be used to control the output end of the D flip-flop 120 to be connected to the control end of the selector 130 after determining the appropriate configuration value of the configuration parameter (Y0, Y1, …, Y2 ⁿ -1), so that the DFE circuit enters the normal working mode; in the normal working mode, the feedback data f is equal to the sampled data {dn, …, d2, d1} of the output of the D flip-flop 120.

Based on the concept similar to the calibration circuit provided in any of the above embodiments, the present application embodiment further provides a chip. As shown in FIG6 , the chip 600 may include the calibration circuit 10 provided in any of the above embodiments, and is used to implement all the functions of the calibration circuit provided in any of the above embodiments, which will not be described here to avoid repetition.

Based on a concept similar to the calibration circuit provided in any of the above embodiments, an embodiment of the present application further provides an electronic device, as shown in FIG7 . The electronic device 700 may include the calibration circuit 10 provided in any of the above embodiments, and is used to implement all the functions of the calibration circuit provided in any of the above embodiments. To avoid repetition, it will not be described here.

Based on a concept similar to the calibration circuit provided in any of the above embodiments, an embodiment of the present application further provides a parameter calibration method for calibrating feedback parameters of a DFE circuit. The parameter calibration method can be applied to the calibration circuit provided in any of the above embodiments.

As shown in FIG8 , an embodiment of the present application provides a parameter calibration method, which may include:

Step 810: Acquire control information, and determine feedback parameters of the DFE circuit based on the control information;

Step 820: Process the first data input from the data input terminal of the DFE circuit based on the feedback parameter to obtain second data;

Step 830: Determine a suitable configuration value of the feedback parameter by comparing the second data with the random data; the random data is obtained based on the first data.

The parameter calibration method is used to calibrate the feedback parameter Y of the DFE circuit 100 .

In step 810, the present application may obtain a control instruction, which may be recorded as training_mode, and parse the control instruction to obtain control information, which may be recorded as m.

The control information m may be used to determine a feedback parameter Y of the DFE circuit.

For example, based on the control information m, a target configuration parameter Ym is selected from a plurality of configuration parameters of the DFE circuit, and the target configuration parameter Ym is used as the feedback parameter Y of the DFE circuit.

The control instruction may be an instruction pre-acquired and stored by the calibration control module, or may be an instruction received by the calibration control module from other control modules, and this application does not impose any specific limitation thereto.

In step 820 , the present application may control the selector 130 to select a target configuration parameter Ym as the feedback parameter Y of the analog circuit 110 from a plurality of configuration parameters based on the control information m obtained by the control instruction training_mode.

In step 830 , when the feedback parameter Y of the analog circuit 110 is the target configuration parameter Ym, the present application can determine a suitable configuration value of the target configuration parameter Ym by comparing whether the second data d1 is the same as the random data golden_rx.

In the calibration mode of the DFE circuit, the embodiment of the present application can determine that the feedback data f is m based on the control information m obtained by the control instruction training_mode, and then control the selector to select the target configuration parameter Ym corresponding to the control information m as the feedback parameter Y from multiple configuration parameters.

It can be understood that, in the calibration mode, although the value of the second data output by the DFE circuit is not fixed, compared with the normal working mode, the feedback data f is not determined by the second data, but can be determined by the control information m indicated by the control instruction training_mode, and the feedback data f does not change with the change of the second data. Furthermore, when the target configuration parameter Ym is calibrated in this calibration mode, the feedback parameter Y can be fixed to the target configuration parameter Ym, and will not change with the change of the sampled data. Based on this, the embodiment of the present application can calibrate the configuration value of the target configuration parameter Ym alone in the calibration mode, determine the appropriate configuration value of Ym, and the accuracy will not be affected by other configuration parameters.

According to the parameter calibration method provided by the embodiment of the present application, the feedback parameter of the DFE circuit is determined based on the control information by acquiring the control information; the first data is processed based on the feedback parameter to obtain the second data; the appropriate configuration value of the feedback parameter is determined by comparing the second data with the random data; the random data is obtained based on the first data. In this way, the target configuration parameter is selected from multiple configuration parameters as the feedback parameter through the control information, and the target configuration parameter can be calibrated separately to obtain the appropriate configuration value of the target configuration parameter, so as to avoid the influence of other feedback parameters during the calibration process of the target configuration parameter, and then the appropriate configuration value of each configuration parameter can be determined separately, so as to quickly determine the appropriate configuration value of the feedback parameter, and improve the calibration efficiency.

In another specific embodiment, in order to improve the accuracy of the appropriate configuration value of the target configuration parameter obtained by calibration, in the above step 830, determining the appropriate configuration value of the feedback parameter by comparing the second data with the random data may include:

Sampling the random data through a target D flip-flop to obtain third data;

In the case that the third data is identical to the control information, a suitable configuration value of the feedback parameter is determined by comparing the second data with random data.

The third data may be understood as random data input by the previous clock.

In this way, in the process of calibrating the target configuration parameter Ym alone in the embodiment of the present application, the random data at the current moment and the second data can be compared to see whether they are the same when the third data is the same as the control information m, without having to compare all the random data and sampling data input at all moments, so that the target configuration parameter Ym can be calibrated in a targeted manner, thereby improving the accuracy and efficiency of the configuration value of the target configuration parameter Ym.

In another specific embodiment, in order to accurately compare the random data with the sampled data, before step 830, the parameter calibration method may further include:

The first data is phase-adjusted to obtain random data, so that the phases of the random data and the second data are aligned.

In this way, before data comparison, the embodiment of the present application can more accurately compare the random data golden_rx with the second data d1 by aligning the phases of the random data golden_rx and the second data d1, thereby improving the accuracy of the configuration value of the target configuration parameter Ym.

In addition, there may be multiple suitable configuration values of the target configuration parameter Ym determined by the embodiment of the present application. In this case, after step 830, the embodiment of the present application can also determine the optimal configuration value of the target configuration parameter based on multiple suitable configuration values of the target configuration parameter. The optimal configuration value can be determined by averaging or median. In other words, the optimal configuration value can be the average or median of multiple suitable configuration values.

Furthermore, after step 830, the embodiment of the present application can also determine the optimal configuration value combination of multiple configuration parameters of the DFE circuit based on the optimal configuration value of each configuration parameter in the multiple configuration parameters after respectively determining the optimal configuration value of each configuration parameter in the multiple configuration parameters, thereby being able to calibrate the optimal configuration value of the feedback parameter. However, in the related art, what is obtained is a suitable configuration value combination of (Y0, Y1), and it is unclear whether Y0 and Y1 in the combination affect each other, and it is difficult to separate the optimal configuration values of Y0 and Y1 and calculate the optimal configuration value combination of Y0 and Y1.

In addition, in other embodiments, the embodiments of the present application may also obtain a switching control instruction after determining a suitable configuration value of each configuration parameter in the plurality of configuration parameters, and control the output end of the DFE circuit to be connected to the control end of the DFE circuit based on the switching information indicated by the switching control instruction, so that the DFE circuit enters a normal working mode. In the normal working mode, the feedback data f input to the control end of the selector of the DFE circuit is equal to the sampled data output by the D flip-flop of the DFE circuit.

In practical applications, the number of configuration parameters of the DFE circuits is different for different orders of the DFE circuits, and the calibration process of the corresponding feedback parameters is also different. The specific process of the parameter calibration method is described below with examples based on the specific situation of the DFE circuit.

For example, for the first-order DFE circuit shown in FIG. 3 , the parameter calibration method provided in the embodiment of the present application can calibrate the configuration parameters Y0 and Y1 respectively.

In the first-order DFE circuit, the value range of the feedback data f is equal to the value range of the sampled data d1 (0 or 1). The control instruction training_mode can provide the following three working modes according to the value range of d1:

When training_mode=0, the feedback data f is equal to the sampled data d1, and the first-order DFE circuit enters the normal working mode;

When training_mode=1, the feedback data f=m=0, and the first-order DFE circuit enters the calibration mode for the configuration parameter Y0;

When training_mode=2, the feedback data f=m=1, and the first-order DFE circuit enters the calibration mode for the configuration parameter Y1.

As shown in FIG. 9 , the embodiment of the present application provides a method for calibrating the configuration parameter Y0 of a first-order DFE circuit, and the specific process includes:

When starting the calibration test, set the control instruction training_mode=1; enter the calibration mode for the configuration parameter Y0; and perform calibration tests on multiple candidate configuration values of the configuration parameter Y0;

Set Y0 to the first candidate configuration value Y0_min;

After the transmitter is started, the DFE circuit starts to receive random data from the transmitter;

Determine whether the third data (i.e., the random data of the previous clock) golden_rx_d is 0;

If golden_rx_d is not 0, get the random data of the next clock;

If golden_rx_d is 0, then compare and determine whether the random data golden_rx of the current clock is equal to d1;

If golden_rx is not equal to d1, it is determined that the current candidate configuration value of Y0 is not a suitable configuration value;

If golden_rx is equal to d1, it is determined whether all random data has been received;

If the random data has not been completely received, the random data of the next clock is obtained;

If all random data has been received, determine that the current candidate configuration value of Y0 is a suitable configuration value;

Determine whether all candidate configuration values of Y0 have been traversed and tested;

If multiple candidate configuration values of Y0 have not been traversed completely, after the transmitter is reset, Y0 is replaced with the next candidate configuration value, and a calibration test is performed on the next candidate configuration value;

If all candidate configuration values of Y0 have been traversed, the calibration test is terminated and all suitable configuration values of Y0 are output.

Similarly, as shown in FIG10 , the embodiment of the present application provides a method for calibrating a configuration parameter Y1 of a first-order DFE circuit, and the specific process includes:

When starting the calibration test, set the control instruction training_mode=2; enter the calibration mode for the configuration parameter Y1; and perform calibration tests on multiple candidate configuration values of the configuration parameter Y1;

Set Y1 to the first candidate configuration value Y1_min;

After the sender starts, it starts receiving random data from the sender;

Determine whether the random data golden_rx_d of the previous clock is 1;

If golden_rx_d is not 1, get the random data of the next clock;

If golden_rx_d is 1, then compare and determine whether the random data golden_rx of the current clock is equal to d1;

If golden_rx is not equal to d1, it is determined that the current candidate configuration value of Y1 is not a suitable configuration value;

If golden_rx is equal to d1, it is determined whether all random data has been received;

If the random data has not been completely received, the random data of the next clock is obtained;

If all random data has been received, determine that the current candidate configuration value of Y1 is a suitable configuration value;

Determine whether all candidate configuration values of Y1 have been traversed and tested;

If multiple candidate configuration values of Y1 have not been traversed completely, after the transmitter is reset, Y1 is replaced with the next candidate configuration value, and a calibration test is performed on the next candidate configuration value;

If all candidate configuration values of Y1 have been traversed, the calibration test is terminated and all suitable configuration values of Y1 are output.

After obtaining all suitable configuration value sets of Y0 and Y1 in the embodiment of the present application, a set of the most suitable {Y0, Y1} configuration values can also be selected by averaging, median, etc. The configuration value is set to the first-order DFE circuit, and then training_mode is modified to 0, so that the first-order DFE circuit can work in normal mode, suppress the inter-symbol interference of the input signal, and output the restored sampled data.

In addition, the embodiment of the present application can also support fast calibration test of n-order DFE circuit. For the n-order DFE circuit shown in FIG5 , the parameter calibration method provided by the embodiment of the present application can calibrate the configuration parameters Y0, Y1, ..., Y2 ⁿ -1 respectively.

In an n-order DFE circuit, the value range of the feedback data f is determined by the value range (0, 1, 2, …, 2 ⁿ -1) of the sampled data {dn, …, d2, d1}. The control instruction training_mode can provide the following 2 ⁿ +1 working modes according to the value range of the sampled data {dn, …, d2, d1}:

When training_mode=0, the feedback data f is equal to the sampled data {dn,…,d2,d1}, and the n-order DFE circuit enters the normal working mode;

When training_mode=1, the feedback data f=m=0, and the n-order DFE circuit enters the calibration mode for the configuration parameter Y0;

When training_mode=2, the feedback data f=m=1, and the n-order DFE circuit enters the calibration mode for the configuration parameter Y1;

……;

When training_mode= ²ⁿ , the feedback data f=m= ²ⁿ -1, and the n-th order DFE circuit enters the calibration mode for the configuration parameter ^Y2n -1.

For the configuration parameter of feedback data f=m (0≤m≤2 ⁿ -1), the calibration test process refers to FIG11. As shown in FIG11, the embodiment of the present application provides a method for calibrating the configuration parameter Ym of an n-order DFE circuit, and the specific process includes:

When starting the calibration test, set the control instruction training_mode=m+1; enter the calibration mode for the configuration parameter Ym; and perform calibration tests on multiple candidate configuration values of the configuration parameter Ym;

Set Ym to the first candidate configuration value Ym_min;

After the sender starts, it starts receiving random data from the sender;

Determine whether the random data golden_PRE of the previous clock is m;

If golden_PRE is not m, get the random data of the next clock;

If golden_PRE is m, then compare and determine whether the random data golden_rx is equal to d1;

If golden_rx is not equal to d1, it is determined that the current candidate configuration value of Y1 is not a suitable configuration value;

If golden_rx is equal to d1, it is determined whether all random data has been received;

If the random data has not been completely received, the random data of the next clock is obtained;

If all random data has been received, determine that the current candidate configuration value of Ym is a suitable configuration value;

Determine whether all candidate configuration values of Ym have been traversed and tested;

If multiple candidate configuration values of Ym have not been traversed completely, after the transmitter is reset, Ym is replaced with the next candidate configuration value, and a calibration test is performed on the next candidate configuration value;

If all candidate configuration values of Ym have been traversed, the calibration test is terminated and all suitable configuration values of Ym are output.

After obtaining all suitable configuration value sets of {Y2n ^- 1, ..., Y1, Y0} in the embodiment of the present application, a set of most suitable configuration values of { ^Y2n -1, ..., Y1, Y0} can be selected by averaging, median, etc. The configuration value is set to the n-order DFE circuit, and then training_mode is modified to 0, so that the n-order DFE circuit can work in normal mode, suppress the inter-symbol interference of the input signal, and output the restored sampled data.

It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims (9)

1. A calibration circuit, comprising: the system comprises a decision feedback equalizer DFE circuit, a calibration control module and a data comparison module; the DFE circuit is provided with a data input end, a control end and a data output end, and the data comparison module is provided with a first input end and a second input end;

the calibration control module is connected with the control end of the DFE circuit and is used for providing control information for the DFE circuit, and the control information is used for determining feedback parameters of the DFE circuit;

The data output end of the DFE circuit is connected with the first input end of the data comparison module, and the DFE circuit is used for processing the first data input by the data input end based on the feedback parameter to obtain second data, and outputting the second data to the first input end through the data output end;

The data comparison module is used for determining a proper configuration value of the feedback parameter by comparing the second data with the random data received by the second input end; the random data is derived based on the first data;

the DFE circuit comprises an analog circuit, a D trigger and a selector; the analog circuit is connected with the D trigger, the D trigger is connected with the first input end of the data comparison module, the output end of the selector is connected with the analog circuit, and the control end of the selector is connected with the calibration control module;

The selector is configured to receive the control information output by the calibration control module, select a target configuration parameter from a plurality of configuration parameters based on the control information, and use the target configuration parameter as the feedback parameter.

2. The calibration circuit of claim 1, wherein the data comparison module comprises a target D flip-flop for receiving the random data, sampling the random data, and outputting third data;

the data comparison module is configured to determine an appropriate configuration value of the feedback parameter by comparing the second data with the random data received by the second input terminal when the third data is the same as the control information.

3. The calibration circuit of claim 1, wherein the DFE circuit comprises an n-order DFE circuit, n being a positive integer; in the n-order DFE circuit, the number of the D flip-flops is n, and the first D flip-flop is connected with the analog circuit; n is greater than 1, n D flip-flops are connected in series in turn; the number of the configuration parameters is 2 ⁿ;

the calibration control module is used for controlling the selector to select a target configuration parameter from 2 ⁿ configuration parameters as the feedback parameter.

4. A calibration circuit according to claim 3, wherein the data comparison module comprises n target D flip-flops; n is greater than 1, n target D flip-flops are sequentially connected in series; the input end of the first target D trigger is used for receiving the random data; n target D flip-flops are used for outputting third data;

the second data are sampling data output by the first D trigger; and the data comparison module is used for determining the proper configuration value of the target configuration parameter by comparing whether the sampling data output by the first D trigger is identical to the random data or not under the condition that the third data is identical to the control information.

5. The calibration circuit of any one of claims 1 to 4, further comprising a data alignment module;

The data alignment module is connected with the second input end of the data comparison module; the data alignment module is used for carrying out phase adjustment on the first data to obtain the random data, so that the random data are aligned with the second data in phase.

6. The calibration circuit of any one of claims 1 to 4,

The data output end of the DFE circuit is connected with the calibration control module, and the calibration control module is further used for controlling the data output end of the DFE circuit to be conducted with the control end of the DFE circuit after determining the proper configuration value of the feedback parameter so as to enable the DFE circuit to enter a normal working mode.

7. A chip comprising the calibration circuit of any one of claims 1-6.

8. A parameter calibration method applied to the calibration circuit of claim 1, comprising:

acquiring control information, and determining feedback parameters of a Decision Feedback Equalizer (DFE) circuit based on the control information;

processing the first data input by the data input end of the DFE circuit based on the feedback parameter to obtain second data;

determining a proper configuration value of the feedback parameter by comparing the second data with the random data; the random data is derived based on the first data.

9. The parameter calibration method of claim 8, comprising: the determining the appropriate configuration value of the feedback parameter by comparing the second data with random data includes:

sampling the random data through a target D trigger to obtain third data;

And under the condition that the third data is the same as the control information, determining the proper configuration value of the feedback parameter by comparing the second data with random data.