CN118610222B - Image sensor and preparation method thereof - Google Patents
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- CN118610222B CN118610222B CN202411045875.3A CN202411045875A CN118610222B CN 118610222 B CN118610222 B CN 118610222B CN 202411045875 A CN202411045875 A CN 202411045875A CN 118610222 B CN118610222 B CN 118610222B
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Abstract
The invention discloses an image sensor and a preparation method thereof, and belongs to the technical field of semiconductors. The image sensor at least comprises a substrate, a photoelectric sensing region, a charge storage region, a floating diffusion region, a drain electrode, a plurality of first grids, a second grid, a third grid and a plurality of global exposure transmission transistors, wherein the photoelectric sensing region is arranged in the substrate, the charge storage region is arranged in the substrate on one side of the photoelectric sensing region, the floating diffusion region and the charge storage region are arranged in the substrate on the same side of the photoelectric sensing region, the drain electrode is arranged in the substrate on one side of the photoelectric sensing region away from the charge storage region, the first grids are arranged on the substrate between the photoelectric sensing region and the charge storage region in parallel, the second grid is arranged on the substrate between the floating diffusion region and the charge storage region, the third grid is arranged on the substrate between the photoelectric sensing region and the drain electrode, and the global exposure transmission transistors comprise at least one first grid. The image sensor and the preparation method thereof can avoid the backflow of electrons to the photoelectric sensing area and improve the image residual shadow problem.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an image sensor and a preparation method thereof.
Background
The complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor has the advantages of low cost, low power consumption, good process compatibility and the like, and is widely applied to the fields of smart phones, machine vision, monitoring cameras and the like. Among CMOS image sensors, a global shutter sensor has a prominent advantage in terms of high-speed scene capturing. For global shutter sensors with smaller pixel sizes, the positive potential of the photo-sensing region needs to be particularly high to increase the full well capacity of the photo-sensing region, but due to the shape and size limitations of the charge storage region, the potential of the charge storage region may be less than the potential of the photo-sensing region. Therefore, at the time when the global exposure transfer transistor (GTX) is turned on to off, electrons under the GTX are easily reflowed to the photo sensing region, thereby causing an image sticking problem.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an image sensor and a method for manufacturing the same, which can avoid the backflow of electrons to the photo-sensing area, improve the image sticking problem, and improve the quality of the image sensor.
In order to solve the technical problems, the invention is realized by the following technical scheme.
The invention provides an image sensor, comprising at least:
A substrate;
the photoelectric sensing area is arranged in the substrate;
a charge storage region disposed within the substrate at one side of the photo-sensing region;
A floating diffusion region disposed within the substrate on the same side of the photo-sensing region as the charge storage region;
the drain electrode is arranged in the substrate at one side of the photoelectric sensing region far away from the charge storage region;
a plurality of first gates arranged in parallel on the substrate between the photoelectric sensing region and the charge storage region;
a second gate disposed on the substrate between the floating diffusion region and the charge storage region;
A third gate electrode disposed on the substrate between the photo-sensing region and the drain electrode, and
A plurality of global exposure pass transistors, each global exposure pass transistor including at least one of the first gates therein.
In an embodiment of the present invention, the plurality of first gates are disposed in parallel on the substrate between the photo sensing region and the charge storage region.
In an embodiment of the present invention, the first gates are two, and the two first gates are a first sub-gate and a second sub-gate, the first sub-gate is disposed on the substrate between the photo-sensing region and the charge storage region, and the second sub-gate is disposed on the substrate on a side of the first sub-gate away from the photo-sensing region.
In an embodiment of the present invention, the global exposure transfer transistor includes a first global exposure transfer transistor including a first sub-gate and a second global exposure transfer transistor including a second sub-gate.
In one embodiment of the present invention, the off time of the first global exposure pass transistor and the off time of the second global exposure pass transistor have a time difference.
In an embodiment of the present invention, the turn-on voltage of the first global exposure transfer transistor and the turn-on voltage of the second global exposure transfer transistor have a voltage difference.
In one embodiment of the present invention, the ratio of the widths of the first sub-gate and the second sub-gate is 1 (1-5).
In an embodiment of the present invention, the first sub-gate and the second sub-gate are spaced apart on the substrate, and a space between the first sub-gate and the second sub-gate is 100nm-300nm.
In an embodiment of the present invention, the image sensor further includes an isolation well region disposed within a portion of the substrate, and the isolation well region exposes a portion of the substrate between the photo-sensing region and the charge storage region, a portion of the substrate between the charge storage region and the floating diffusion region, and a portion of the substrate between the photo-sensing region and the drain.
The invention also provides a preparation method of the image sensor, which at least comprises the following steps:
Providing a substrate;
forming a photoelectric sensing region in the substrate;
forming a charge storage region in the substrate at one side of the photoelectric sensing region;
forming a floating diffusion region in the substrate at one side of the photoelectric sensing region, wherein the floating diffusion region and the charge storage region are arranged at the same side of the photoelectric sensing region;
forming a drain electrode in the substrate at one side of the photoelectric sensing region far away from the charge storage region;
A plurality of first grid electrodes are arranged on the substrate between the photoelectric sensing area and the charge storage area in parallel;
Forming a second gate on the substrate between the floating diffusion region and the charge storage region, and
A third gate is formed on the substrate between the photo-sensing region and the drain.
In summary, the present invention provides an image sensor and a method for manufacturing the same, which can prevent electrons from flowing back to a photo-sensing region, improve the image sticking problem, and improve the quality of the image sensor. In addition, the image sensor provided by the invention can accelerate the transmission of electrons, reduce the generation of image hysteresis, reduce the threshold voltage and improve the sensitivity and the response speed of the image sensor.
Of course, it is not necessary for any of the above described advantages to be achieved simultaneously in practicing any of the embodiments of the invention.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a top view of an image sensor according to an embodiment of the invention.
Fig. 2 is a schematic view of the formation of an oxide layer along section A-A of fig. 1.
Figure 3 is a schematic illustration of the formation of an isolation well region along section A-A of figure 1.
Fig. 4 is a schematic view of forming an isolation well region along the section B-B of fig. 1.
Fig. 5 is a schematic view of the formation of the photo-sensing region along section A-A of fig. 1.
FIG. 6 is a schematic illustration of the formation of a first pinning layer within the photo sensing region along section A-A of FIG. 1.
Fig. 7 is a schematic view of the formation of a charge storage region along section A-A of fig. 1.
Fig. 8 is a schematic view of the formation of a charge storage region along section B-B of fig. 1.
FIG. 9 is a schematic diagram of a portion of the isolation well region, the photo-sensing region and the charge storage region of FIG. 1.
FIG. 10 is a schematic illustration of the formation of a first pinning layer within the charge storage region along section A-A in FIG. 1.
FIG. 11 is a schematic illustration of the formation of a first pinning layer within the charge storage region along section B-B in FIG. 1.
Fig. 12 is a schematic view of a gate material layer formed along section A-A of fig. 1.
Fig. 13 is a schematic view of a gate material layer formed along section B-B of fig. 1.
Fig. 14 is a schematic view of the formation of the first gate and the third gate along section A-A of fig. 1.
Fig. 15 is a schematic view of a second sub-gate and a second gate formed along section B-B of fig. 1.
FIG. 16 is a schematic illustration of the formation of a second pinning layer along section A-A of FIG. 1.
FIG. 17 is a schematic illustration of the formation of a second pinning layer along section B-B of FIG. 1.
Fig. 18 is a schematic view of forming a floating diffusion region along the B-B section of fig. 1.
Fig. 19 is a schematic view of the formation of a drain along section A-A of fig. 1.
Description of the reference numerals:
10. The semiconductor device comprises a substrate, 11, an isolated well region, 12, a photoelectric sensing region, 121, a first region, 122, a second region, 13, a charge storage region, 131, a first subsection, 132, a second subsection, 14, a floating diffusion region, 15, a drain electrode, 16, a first grid, 161, a first sub-grid, 162, a second sub-grid, 17, a second grid, 18, a third grid, 19, an oxide layer, 20, a grid material layer, 21, a first pinning layer, 22 and a second pinning layer.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The technical solution of the present invention will be described in further detail below with reference to the embodiments and the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides an image sensor, which includes, for example, a substrate 10, a photo-sensing region 12, a charge storage region 13, and a first gate 16. The photo-sensing region 12 is disposed in the substrate 10, the charge storage region 13 is disposed in the substrate 10 at one side of the photo-sensing region 12, the first gate 16 is a plurality of first gates 16, for example, and the plurality of first gates 16 are disposed on the substrate 10 between the photo-sensing region 12 and the charge storage region 13 in parallel and cover a portion of the photo-sensing region 12 and a portion of the charge storage region 13. According to the image sensor provided by the invention, the plurality of first grid electrodes 16 are arranged to form the plurality of GTXs, so that electrons can be effectively prevented from flowing back to the photoelectric sensing area 12, the problem of image residual shadow is solved, and the imaging quality of the image sensor is improved. The present invention also provides a method for manufacturing an image sensor, and in this embodiment, the method for manufacturing an image sensor is described by taking a cross-sectional view taken along A-A section and B-B section in fig. 1 as an example.
Referring to fig. 2, in one embodiment of the present invention, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire, silicon wafer, or other III/V compound semiconductor materials, and the like, and also includes a stacked structure of these semiconductor materials, or is silicon on insulator, silicon germanium on insulator, and the like. The substrate 10 may be an intrinsic semiconductor, or an N-type semiconductor or a P-type semiconductor may be formed by implanting ions into the substrate 10. Moreover, the present invention is not limited to the thickness of the substrate 10. In this embodiment, a method of manufacturing an image sensor will be described, taking the P-type substrate 10 as an example, for example. The dopant ions In the P-type substrate 10 are, for example, boron (B) or indium (In), and the concentration of the dopant ions is low, for example, 1×10 15atmos/cm3-2×1015atmos/cm3.
Referring to fig. 2, in one embodiment of the present invention, an oxide layer 19 is formed on a substrate 10. The oxide layer 19 is formed, for example, by a thermal oxidation method, an in-situ vapor growth method, a chemical vapor deposition method, or the like, and the material of the oxide layer 19 is, for example, silicon oxide, silicon dioxide, silicon oxynitride, or the like, and the thickness of the oxide layer 19 is not limited, and may be specifically selected according to actual needs. By providing the oxide layer 19 as a buffer layer, the substrate 10 can be protected from damage when ions are subsequently implanted into the substrate 10.
Referring to fig. 1 and fig. 2 to fig. 4, in an embodiment of the present invention, after forming the oxide layer 19, first ions are implanted into the substrate 10 to form the isolation well region 11. The isolation well region 11 is disposed in a portion of the substrate 10, the kind and concentration of the first ions may be selected according to the actual situation, and specific parameters such as the depth and width of the isolation well region 11 may be set according to the actual situation. In this embodiment, the first ion is, for example, a P-type ion such as B or In, and the concentration of the first ion is, for example, greater than the concentration of the P-type ion doped In the P-type substrate 10. By arranging the isolation well region 11, the isolation well region can be used as isolation between adjacent components in the substrate 10, so that mutual interference between the adjacent components is avoided, and the performance of the image sensor is improved.
Referring to fig. 1 and 5, in an embodiment of the present invention, after forming an isolation well region 11, a second ion is implanted into a substrate 10 to form a photo-sensing region 12. Parameters such as the shape, width and depth of the photo-sensing region 12, and the type and concentration of the second ion may be selected according to practical situations. In this embodiment, the second ion and the first ion are different, for example, the second ion is an N-type ion such As phosphorus (P) or arsenic (As), the photo-sensing region 12 includes, for example, a first region 121 and a second region 122, the first region 121 is disposed in the substrate 10, the second region 122 is disposed on one side of the first region 121, and the width of the second region 122 is smaller than that of the first region 121, for example. By providing the photo-sensing region 12, the optical signal received by the image sensor can be converted into an electrical signal.
Referring to fig. 5 and 6, in an embodiment of the present invention, after the photo-sensing region 12 is formed, third ions are implanted into the photo-sensing region 12, and the first pinning layer 21 is formed in the photo-sensing region 12. Parameters such as the type and concentration of the third ion may be selected according to the actual situation, and specific parameters such as the depth and width of the first pinning layer 21 may be set according to the actual situation. In this embodiment, the type and concentration of the third ion are the same as those of the first ion, for example, and the third ion is a P-type ion such as B or In. By providing the first pinning layer 21, electron residue can be prevented, and dark current generated by defects in the surface layer of the photo-sensing region 12 can be isolated.
Referring to fig. 6 to 9, in an embodiment of the present invention, after forming the first pinning layer 21 in the photo-sensing region 12, fourth ions are implanted into the substrate 10 at one side of the photo-sensing region 12 to form the charge storage region 13. Parameters such as the shape, width and depth of the charge storage region 13, and the type and concentration of the fourth ion may be selected according to practical situations. In this embodiment, the type of the fourth ion is different from that of the first ion, for example, the fourth ion is an N-type ion such As P or As, the charge storage region 13 and the photo-sensing region 12 are disposed in the substrate 10 in parallel, and the depth ratio of the photo-sensing region 12 to the charge storage region 13 is (1-3): 1, for example. In this embodiment, the charge storage region 13 includes, for example, a first portion 131 and a second portion 132, the first portion 131 is disposed at a side of the first region 121 at intervals, the second portion 132 is disposed at a side of the second region 122 at intervals, the first portion 131 and the second portion 132 are disposed at the same side of the photo-sensing region 12, the side of the first portion 131 away from the second portion 132 is aligned with the first region 121, and the width of the first portion 131 is smaller than the width of the second portion 132, for example. Wherein the ratio of the widths of the second portion 132 and the first portion 131 is, for example, (1-3): 1, the ratio of the widths of the first region 121 and the second portion 132 is, for example, (2-4): 1, the distance between the first portion 131 and the first region 121 is, for example, 600nm to 700nm, and the distance between the second portion 132 and the second region 122 is, for example, 200nm to 400nm.
Referring to fig. 10 to 11, in an embodiment of the invention, after forming the charge storage region 13, fifth ions are implanted into the charge storage region 13, and the first pinning layer 21 is formed in the charge storage region 13. Parameters such as the type and concentration of the fifth ion may be selected according to the actual situation, and specific parameters such as the depth and width of the first pinned layer 21 in the charge storage region 13 may be set according to the actual situation. In the present embodiment, the species and concentration of the fifth ion are the same as those of the third ion, for example, and the fifth ion is a P-type ion such as B or In. By providing the first pinning layer 21, electron residue can be prevented, and dark current generated by defects on the surface layer of the charge storage region 13 can be isolated.
Referring to fig. 12 to 13, in an embodiment of the present invention, after forming the first pinning layer 21, a gate material layer 20 is formed on the oxide layer 19. The material of the gate material layer 20 is, for example, polysilicon, and the forming manner of the gate material layer 20 is, for example, chemical vapor deposition, physical vapor deposition, electroplating, atomic layer deposition, etc., and the thickness of the gate material layer 20 can be set according to practical situations.
Referring to fig. 1, 14 to 15, in an embodiment of the present invention, after forming a gate material layer 20, a patterned photoresist layer is formed on the gate material layer 20, and the patterned photoresist layer is used as a mask, and an oxide layer 19 is used as a stop layer to etch the gate material layer 20, so as to form a first gate 16, a second gate 17 and a third gate 18. The first gate 16 is, for example, a plurality of first gates 16, the first gates 16 are disposed on the substrate 10 between the photo-sensing region 12 and the charge storage region 13 in parallel to form a plurality of GTXs, the second gate 17 is disposed on the substrate 10 on a side of the second portion 132 away from the first portion 131 to form a transfer Transistor (TX), and the third gate 18 is disposed on the substrate 10 on a side of the photo-sensing region 12 away from the charge storage region 13 to form a charge discharging gate (OFG). In this embodiment, the second gate 17 covers a portion of the charge storage region 13, and the third gate 18 covers a portion of the photo-sensing region 12. By forming the first gate electrode 16, the second gate electrode 17, and the third gate electrode 18 on the substrate 10, electron transfer can be accelerated, and image lag can be reduced.
Referring to fig. 1 and fig. 14 to fig. 15, in an embodiment of the invention, the number of the first gates 16 is two, for example, the number of the first gates 16 is a first sub-gate 161 and a second sub-gate 162, respectively, the first sub-gate 161 is disposed on the substrate 10 between the photo-sensing region 12 and the charge storage region 13, the second sub-gate 162 is disposed on the substrate 10 on a side of the first sub-gate 161 away from the photo-sensing region 12, the first sub-gate 161 covers a portion of the first region 121 and a portion of the second sub-portion 132, and the second sub-gate 162 covers a portion of the first sub-portion 131 and a portion of the second sub-portion 132. Also, in the present embodiment, the first sub-gate 161 and the second sub-gate 162 are disposed in parallel and spaced apart on the substrate 10. The ratio of the widths of the first sub-gate 161 and the second sub-gate 162 is, for example, 1 (1-5), and the distance between the first sub-gate 161 and the second sub-gate 162 is, for example, 100nm-300nm. In the present embodiment, the number of first gates 16 is two to form two GTXs, i.e., GTX1 and GTX2. The first sub-gate 161 is included in the GTX1, the second sub-gate 162 is included in the GTX2, and the closing time of the GTX1 and the GTX2 has a time difference. In this embodiment, GTX2 is turned off late relative to GTX 1. By arranging the first sub-gate 161 and the second sub-gate 162 parallel to the photo-sensing region 12 to form two GTXs, and the closing time of the two GTXs is different, the GTX2 can effectively capture electrons approaching to the photo-sensing region 12, thereby preventing electrons from flowing back to the photo-sensing region 12 and improving the image sticking problem. In other embodiments of the present invention, not only the turn-off time of GTX1 and GTX2 has a time difference, but also the turn-on voltage of GTX1 and GTX2 may have a voltage difference, so as to further inhibit the electrons from flowing back to the photo-sensing region 12, and further improve the image sticking problem. The turn-on voltage of GTX2 is, for example, greater than the turn-on voltage of GTX 1.
Referring to fig. 16 to 17, in an embodiment of the present invention, after forming the first gate 16, the second gate 17 and the third gate 18, sixth ions are implanted into the isolation well region 11 and the photo-sensing region 12 exposed by the gates, so as to form the second pinning layer 22. Parameters such as the type and concentration of the sixth ion may be selected according to the actual situation, and specific parameters such as the depth and width of the second pinning layer 22 may be set according to the actual situation. In this embodiment, the second pinning layer 22 is disposed In the photo-sensing region 12 exposed by the gate and In the portion of the isolation well region 11 on the side of the charge storage region 13 away from the photo-sensing region 12, the species of the sixth ion is the same as that of the third ion, for example, the sixth ion is a P-type ion such as B or In, the thickness of the second pinning layer 22 is greater than that of the first pinning layer 21, and the energy of the sixth ion is greater than that of the third ion. Specifically, in the present embodiment, the implantation dose of the sixth ion is one order of magnitude higher than that of the third ion. By providing the second pinning layer 22, dark current and white pixels can be prevented.
Referring to fig. 18, after forming the second pinning layer 22, seventh ions are implanted into the substrate 10 and the isolation well region 11 at one side of the charge storage region 13 to form the floating diffusion region 14, and then the substrate 10 is annealed to eliminate lattice defects in an embodiment of the present invention. Wherein the floating diffusion region 14 and the charge storage region 13 are disposed on the same side of the photo-sensing region 12, during the annealing process, the isolation well region 11 and seventh ions within the isolation well region 11 may diffuse in the direction in which the photo-sensing region 12 is located, thereby causing a portion of the floating diffusion region 14 to be covered by the second gate 17. The present invention is not limited to the depth and width of the floating diffusion region 14, and the kind and concentration of the seventh ion, and may be selected according to the actual situation. In this embodiment, the seventh ion is different from the first ion in kind, for example, and the seventh ion is an N-type ion such As P or As.
Referring to fig. 18 to 19, in an embodiment of the present invention, after forming the floating diffusion region 14, eighth ions are continuously implanted into the substrate 10 and the isolation well region 11 on the side of the photo sensing region 12 away from the charge storage region 13 to form the drain electrode 15, and then annealing the substrate 10. During the annealing process, the isolation well 11 and the eighth ions in the isolation well 11 diffuse in the direction of the charge storage region 13, so that a portion of the drain 15 is covered by the third gate 18. The present invention is not limited to parameters such as the depth and width of the drain electrode 15, and the type and concentration of the eighth ion, and may be selected according to practical situations. In this embodiment, the eighth ion is different from the first ion in kind, for example, and is an N-type ion such As P or As.
Referring to fig. 1, 18 to 19, in an embodiment of the present invention, the isolation well region 11 is not provided on a portion of the substrate 10 between the drain electrode 15 and the photo sensing region 12, a portion of the substrate 10 between the floating diffusion region 14 and the charge storage region 13, and a portion of the substrate 10 between the photo sensing region 12 and the charge storage region 13. Due to the high doping concentration of ions in the isolation well region 11, electrons are prevented from being transferred between the photo-sensing region 12, the charge storage region 13, the floating diffusion region 14 and the drain electrode 15 if the isolation well region 11 completely covers the substrate 10 between the photo-sensing region 12 and the charge storage region 13, the substrate 10 between the charge storage region 13 and the floating diffusion region 14, and the substrate 10 between the photo-sensing region 12 and the drain electrode 15. Therefore, by providing the isolation well region 11 to expose a portion of the substrate 10 between the photo-sensing region 12 and the charge storage region 13, it is possible to ensure normal transfer of electrons between the photo-sensing region 12, the charge storage region 13, the floating diffusion region 14 and the drain electrode 15, and also to reduce the threshold voltage, and to improve the sensitivity and response speed of the image sensor.
Referring to fig. 1 and 19, in an embodiment of the present invention, after forming the drain electrode 15, subsequent metal silicide blocking layer, metal interconnection layer, filtering and microlens processes may be performed, which will not be described herein.
In summary, the present invention provides an image sensor and a method for manufacturing the same, in which a plurality of first gates are formed on a substrate, and the plurality of first gates are disposed parallel to a photo-sensing region and a charge storage region, so as to form a plurality of global exposure transmission transistors with different off-time or on-voltage, which can effectively prevent electrons from flowing back to the photo-sensing region, improve the image sticking problem, and improve the quality of the image sensor. In addition, the image sensor provided by the invention can accelerate the transmission of electrons and reduce the generation of image hysteresis by arranging the grid electrode on the substrate.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (9)
1. An image sensor, comprising at least:
A substrate;
the photoelectric sensing area is arranged in the substrate;
a charge storage region disposed within the substrate at one side of the photo-sensing region;
A floating diffusion region disposed within the substrate on the same side of the photo-sensing region as the charge storage region;
the drain electrode is arranged in the substrate at one side of the photoelectric sensing region far away from the charge storage region;
A plurality of first grids, which are arranged on the substrate between the photoelectric sensing area and the charge storage area in parallel, wherein the first grids comprise first sub-grids and second sub-grids, the first sub-grids are arranged on the substrate between the photoelectric sensing area and the charge storage area, and the second sub-grids are arranged on the substrate at one side of the first sub-grids far away from the photoelectric sensing area;
a second gate disposed on the substrate between the floating diffusion region and the charge storage region;
A third gate electrode disposed on the substrate between the photo-sensing region and the drain electrode, and
A plurality of global exposure pass transistors, each global exposure pass transistor including at least one of the first gates therein.
2. The image sensor of claim 1, wherein a plurality of the first gates are disposed in parallel on the substrate between the photo-sensing region and the charge storage region.
3. The image sensor of claim 1, wherein the global exposure pass transistor comprises a first global exposure pass transistor comprising a first sub-gate and a second global exposure pass transistor comprising a second sub-gate.
4. The image sensor of claim 3, wherein there is a time difference between the off time of the first global exposure pass transistor and the off time of the second global exposure pass transistor.
5. The image sensor of claim 3, wherein there is a voltage difference between an on voltage of the first global exposure pass transistor and an on voltage of the second global exposure pass transistor.
6. The image sensor of claim 1, wherein the ratio of the widths of the first sub-gate and the second gate is 1 (1-5).
7. The image sensor of claim 1, wherein the first and second sub-gates are spaced apart on the substrate with a spacing between the first and second sub-gates of 100nm-300nm.
8. The image sensor of claim 1, further comprising an isolation well region disposed within a portion of the substrate, and exposing a portion of the substrate between the photo-sensing region and the charge storage region, a portion of the substrate between the charge storage region and the floating diffusion region, and a portion of the substrate between the photo-sensing region and the drain.
9. A method for manufacturing an image sensor, comprising at least the steps of:
Providing a substrate;
forming a photoelectric sensing region in the substrate;
forming a charge storage region in the substrate at one side of the photoelectric sensing region;
forming a floating diffusion region in the substrate at one side of the photoelectric sensing region, wherein the floating diffusion region and the charge storage region are arranged at the same side of the photoelectric sensing region;
forming a drain electrode in the substrate at one side of the photoelectric sensing region far away from the charge storage region;
A plurality of first grids are arranged on the substrate between the photoelectric sensing area and the charge storage area in parallel, the first grids comprise first sub-grids and second sub-grids, the first sub-grids are arranged on the substrate between the photoelectric sensing area and the charge storage area, and the second sub-grids are arranged on the substrate at one side of the first sub-grids far away from the photoelectric sensing area;
Forming a second gate on the substrate between the floating diffusion region and the charge storage region, and
A third gate is formed on the substrate between the photo-sensing region and the drain.
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