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CN118607452B - Manufacturing method of satellite navigation three-dimensional chip - Google Patents

Manufacturing method of satellite navigation three-dimensional chip Download PDF

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CN118607452B
CN118607452B CN202410538210.XA CN202410538210A CN118607452B CN 118607452 B CN118607452 B CN 118607452B CN 202410538210 A CN202410538210 A CN 202410538210A CN 118607452 B CN118607452 B CN 118607452B
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袁永斌
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Zhicode Core Wuxi Communication Technology Co ltd
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Abstract

The invention provides a manufacturing method of a satellite navigation three-dimensional chip, and relates to the field of manufacturing of three-dimensional chips. The manufacturing method based on the satellite navigation three-dimensional chip comprises the following steps of S1, firstly, performing three-dimensional structural design by using professional design software, taking electrical performance, thermal management and optimization of physical dimensions into consideration, adopting a silicon perforation technology to realize vertical integration among all layers of the chip, ensuring rapid signal transmission and high-density integration, and simultaneously, preparing a high-heat-conductivity nano material by using graphene and carbon nano tube composite materials, and using the high-heat-conductivity nano material as a thermal interface material. Through using professional design software to carry out three-dimensional structural design to adopt the vertical integration between each layer of silicon perforation technique realization chip, this scheme can ensure quick transmission and the high density integration of signal, selects graphene and carbon nanotube combined material as thermal interface material, combines meticulous design's thermal diffusion layer overall arrangement and miniature cooling channel, has shown the thermal management efficiency who has promoted the chip.

Description

Manufacturing method of satellite navigation three-dimensional chip
Technical Field
The invention relates to the technical field of manufacturing of three-dimensional chips, in particular to a manufacturing method of a satellite navigation three-dimensional chip.
Background
The manufacturing method and the characteristics of the satellite navigation chip ZMX A2301 can be summarized in that the packaging process ZMX A adopts a packaging format of 7mmx7mmLGA-28 by using a single chip packaging process. The packaging mode is suitable for application of GPS/Beidou single chip, and provides compact size and good performance. The integrated design is that all necessary chips required by the GPS/Beidou receiver are integrated inside the chip, wherein the necessary chips comprise GPS/Beidou radio frequency and fundamental frequency, a 0.5ppm temperature compensation oscillator, a voltage stabilizer and passive devices. This integrated design simplifies the external hardware requirements and the user can start using it by simply connecting the antenna to the power supply. Temperature profile-during manufacturing, the chip is recommended to process using a specific temperature profile to ensure good performance and reliability. For lead-free and SnPb technologies, there are definite preheating, rising, reflow and cooling steps to ensure the quality of the chip during the production process.
Drawbacks or challenges are high integration, which, while reducing external component requirements, increases internal heat generation. If the thermal management is improperly designed, performance and lifetime of the chip may be affected. Packaging limitations-the use of a particular packaging format (e.g., 7mmx7 mmLGA-28) may limit the flexibility of chip design, especially when attempting to introduce new functionality or to retrofit existing functionality. Production process complexity-high precision temperature control and complex production process requirements can increase production costs and complexity, especially in large-scale production. Environmental flexibility-for applications where temperature compensation and stability requirements are high, the chip needs to maintain high performance under a wide range of environmental conditions, which can present additional challenges for design and testing.
Disclosure of Invention
(One) solving the technical problems
Aiming at the defects of the prior art, the invention provides a manufacturing method of a satellite navigation three-dimensional chip, which solves the problems that the temperature compensation and stability requirements are high and the flexibility of chip design can be limited by using a specific packaging format.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme that the manufacturing method of the satellite navigation three-dimensional chip comprises the following steps:
S1, performing three-dimensional structural design by using professional design software, considering optimization of electrical performance, thermal management and physical dimension, adopting a silicon perforation technology to realize vertical integration among layers of a chip, ensuring rapid transmission and high-density integration of signals, and simultaneously preparing a high-heat-conductivity nano material by using graphene and carbon nano tube composite materials, and using the high-heat-conductivity nano material as a thermal interface material to optimize a thermal conduction path and improve thermal management efficiency;
S2, particularly considering the layout of the heat diffusion layers in the design, ensuring that heat can be uniformly distributed and effectively conducted to the surface of a cooling channel or a chip, and avoiding hot spots;
S3, adopting a novel mixed material packaging technology, fusing a high-heat-conductivity nano material with a traditional packaging material, and simultaneously introducing a telescopic interconnection structure to adapt to different circuit designs and heat diffusion requirements;
S4, precisely manufacturing a micro cooling channel by using a laser direct writing lithography technology and an electrochemical deposition process, wherein the process comprises the steps of selecting a proper lithography mask, adjusting laser parameters and electrochemical deposition parameters to form a cooling channel with precise size and optimized layout;
S5, developing a power management strategy based on environment perception, collecting surrounding environment data by using environment sensors such as temperature, humidity and the like, and analyzing and determining an optimal power consumption state through a machine learning model by combining workload information in a chip;
S6, integrating a self-adaptive frequency adjustment technology, dynamically adjusting the working frequency of a processor according to the chip temperature and the load condition monitored in real time, and adopting a high-precision temperature sensor and a signal processing algorithm to ensure quick and accurate frequency adjustment response;
S7, utilizing a multilayer mixed signal integration technology, effectively isolating analog, digital and radio frequency modules through special isolation layer materials, reducing mutual interference, and particularly considering layout optimization of signal paths and isolation layers during design;
s8, integrating an intelligent material containing microcapsules in a key structure to realize a self-repairing mechanism, wherein a repairing agent contained in the microcapsules can be automatically released when microcracks appear in the material, damage is repaired through chemical reaction, the long-term reliability of a chip is enhanced, and detailed experiments are carried out to verify the distribution uniformity, the repairing efficiency and the influence on the performance of the chip of the microcapsules;
s9, implementing an environment-friendly production process, optimizing selection and use of chemical reagents, introducing an energy recovery and waste treatment system, ensuring environmental friendliness of the production process, identifying production bottlenecks and efficiency improvement opportunities by using a data driving method through monitoring data on a production line in real time, optimizing a production flow by using an artificial intelligent algorithm, improving production efficiency and reducing cost;
S10, designing and implementing a set of comprehensive performance and reliability test schemes including, but not limited to, environmental tests, mechanical tests and long-term stability tests, ensuring the performance and stability of the chip under various extreme conditions, analyzing root causes of problems found in the test process, and feeding back to the design and manufacturing process for optimization.
Preferably, the laser parameters include power, focal length and scanning speed, and the electrochemical deposition parameters are electrolyte concentration and current density.
Preferably, the isolation layer material is a high dielectric constant material, the environmental test is a high-low temperature test, a humidity test and a salt spray test, and the mechanical test is a vibration and impact test.
Preferably, the novel mixed material packaging technology comprises the step of combining the epoxy resin with the graphene sheets and the carbon nanotubes in a specific ratio of 2:3.
Preferably, the machine learning model is a deep neural network training model through training a data set, the data set training model comprises steps of feature selection, model parameter tuning, cross verification and the like, so that prediction accuracy and generalization capability are ensured, and the data set comprises historical data of temperature, humidity, workload and power consumption state.
Preferably, the high-precision temperature sensor adopts a high-precision temperature sensor based on a micro-electromechanical system technology, the signal processing algorithm comprises the steps of filtering, denoising, temperature compensation and the like, and a digital signal processor is used for realizing real-time data processing, so that the accuracy and the reliability of temperature data are ensured.
Preferably, the layout of the isolation layer is optimized by adopting a material with high dielectric constant and low loss, such as aluminum oxide or silicon nitride, so as to effectively isolate electromagnetic interference among different functional modules.
Preferably, the experimental verification of the microcapsule distribution uniformity, the repair efficiency and the chip performance influence comprises scanning electron microscope analysis, energy dispersion X-ray spectrum analysis and mechanical performance test, so as to verify the uniform distribution condition of the microcapsules in the intelligent material, the repair efficiency under different stress conditions and the influence of a self-repair mechanism on the chip electrical performance.
(III) beneficial effects
The invention provides a manufacturing method of a satellite navigation three-dimensional chip. The beneficial effects are as follows:
The three-dimensional structural design is carried out by using professional design software, vertical integration among all layers of the chip is realized by adopting a silicon perforation technology, the scheme can ensure rapid transmission and high-density integration of signals, graphene and carbon nano tube composite materials are selected as thermal interface materials, the well-designed thermal diffusion layer layout and micro cooling channels are combined, the thermal management efficiency of the chip is remarkably improved, a novel mixed material packaging technology is adopted, a high-heat-conductivity nano material and a traditional packaging material are combined, a telescopic interconnection structure is introduced, the thermal conductivity of the package is improved, the adaptability of circuit design and thermal diffusion requirements is increased, the overall packaging performance and reliability are improved, the integration of an environment-aware power management strategy and a self-adaptive frequency adjustment technology is improved, the chip can dynamically adjust power consumption and processor frequency according to real-time temperature and load conditions, the application of a multi-layer mixed signal integration technology and isolation layer materials effectively isolates interference among analog, digital and radio frequency modules, the signal path and isolation layer layout are optimized, the signal processing capacity and the overall performance of the chip are improved, and the microcapsule can automatically release a chemical repair agent to carry out a detailed repair reaction when microcrack appears, and the special experiment performance is positively verified by the verification of the chip.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a manufacturing method of a satellite navigation three-dimensional chip, which comprises the following steps of S1, firstly, performing three-dimensional structural design by using professional design software, taking electrical performance, thermal management and optimization of physical dimensions into consideration, adopting a silicon perforation technology to realize vertical integration among all layers of the chip, ensuring rapid signal transmission and high-density integration, and simultaneously, preparing a high-heat-conductivity nano material by using graphene and carbon nano tube composite materials, and using the high-heat-conductivity nano material as a thermal interface material so as to optimize a heat conduction path and improve thermal management efficiency.
S2, the layout of the heat diffusion layers is particularly considered in the design, so that the heat can be uniformly distributed and effectively conducted to the surface of the cooling channel or the chip, and hot spots are avoided.
S3, a novel mixed material packaging technology is adopted, a high-heat-conductivity nano material and a traditional packaging material are fused, and a telescopic interconnection structure is introduced to adapt to different circuit designs and thermal diffusion requirements, wherein the novel mixed material packaging technology comprises the steps of using epoxy resin, graphene sheets and carbon nanotubes to be combined in a specific ratio of 2:3.
S4, precisely manufacturing a micro cooling channel by using a laser direct-writing photoetching technology and an electrochemical deposition process, wherein the process comprises the steps of selecting a proper photoetching mask, adjusting laser parameters and electrochemical deposition parameters to form the cooling channel with accurate size and optimized layout, and the laser parameters comprise power, focal length and scanning speed, and the electrochemical deposition parameters comprise electrolyte concentration and current density.
S5, developing a power management strategy based on environment perception, collecting surrounding environment data by using environment sensors such as temperature and humidity, analyzing and determining an optimal power consumption state through a machine learning model by combining with workload information in a chip, wherein the data set training model comprises the steps of feature selection, model parameter tuning, cross verification and the like so as to ensure the accuracy and generalization capability of prediction, and the data set comprises historical data of the temperature, the humidity, the workload and the power consumption state.
S6, an integrated self-adaptive frequency adjustment technology dynamically adjusts the working frequency of the processor according to the chip temperature and the load condition monitored in real time, a high-precision temperature sensor and a signal processing algorithm are adopted, quick and accurate frequency adjustment response is guaranteed, the signal processing algorithm comprises the steps of filtering, denoising, temperature compensation and the like, real-time data processing is achieved through a digital signal processor, and accuracy and reliability of temperature data are guaranteed.
S7, utilizing a multilayer mixed signal integration technology, effectively isolating analog, digital and radio frequency modules through special isolation layer materials, reducing mutual interference, particularly considering layout optimization of signal paths and isolation layers in design, wherein the isolation layer materials are high dielectric constant materials, environment tests are high-low temperature tests, humidity tests and salt spray tests, mechanical tests are vibration and impact tests, and the layout optimization of the isolation layers adopts materials with high dielectric constants and low loss, such as aluminum oxide or silicon nitride, to effectively isolate electromagnetic interference among different functional modules.
S8, integrating an intelligent material containing microcapsules in a key structure to realize a self-repairing mechanism, wherein a repairing agent contained in the microcapsules can be automatically released when microcracks appear in the material, damage is repaired through chemical reaction, the long-term reliability of a chip is enhanced, detailed experiments are carried out to verify the distribution uniformity, the repairing efficiency and the influence on the chip performance of the microcapsules, and the experimental verification of the distribution uniformity, the repairing efficiency and the influence on the chip performance of the microcapsules comprises scanning electron microscope analysis, energy dispersion X-ray spectrum analysis and mechanical performance test so as to verify the uniform distribution condition of the microcapsules in the intelligent material, the repairing efficiency under different stress conditions and the influence of the self-repairing mechanism on the electrical performance of the chip.
S9, implementing an environment-friendly production process, optimizing selection and use of chemical reagents, introducing an energy recovery and waste treatment system, ensuring environmental friendliness of the production process, identifying production bottlenecks and efficiency improvement opportunities by using a data driving method through monitoring data on a production line in real time, optimizing a production flow by using an artificial intelligent algorithm, improving production efficiency and reducing cost.
S10, designing and implementing a set of comprehensive performance and reliability test schemes including, but not limited to, environmental tests, mechanical tests and long-term stability tests, ensuring the performance and stability of the chip under various extreme conditions, analyzing root causes of problems found in the test process, and feeding back to the design and manufacturing process for optimization.
TABLE I data comparison Table
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (7)

1.一种卫星导航三维芯片的制造方法，其特征在于，包括：1. A method for manufacturing a satellite navigation three-dimensional chip, characterized by comprising: S1、首先使用专业的设计软件进行三维结构设计，考虑电气性能、热管理和物理尺寸的最优化，采用硅穿孔技术实现芯片各层之间的垂直集成，确保信号的快速传递和高密度集成，同时，选用石墨烯和碳纳米管复合材料制备高导热纳米材料，用作热界面材料，以优化热传导路径，提高热管理效率；S1. First, use professional design software to design the three-dimensional structure, consider the optimization of electrical performance, thermal management and physical size, use silicon via technology to achieve vertical integration between chip layers, ensure fast signal transmission and high-density integration, and at the same time, use graphene and carbon nanotube composite materials to prepare high thermal conductivity nanomaterials, which are used as thermal interface materials to optimize the heat conduction path and improve thermal management efficiency; S2、设计中考虑热扩散层的布局，确保热量均匀分布并有效传导至冷却通道或芯片表面，避免热点产生；S2. Consider the layout of the heat diffusion layer in the design to ensure that the heat is evenly distributed and effectively conducted to the cooling channel or chip surface to avoid hot spots; S3、采用新型混合材料封装技术，融合了高导热纳米材料与传统封装材料，同时引入可伸缩互连结构以适应不同的电路设计和热扩散需求；S3, adopts new hybrid material packaging technology, combines high thermal conductivity nanomaterials with traditional packaging materials, and introduces scalable interconnection structure to adapt to different circuit designs and thermal diffusion requirements; S4、使用激光直写光刻技术和电化学沉积过程精密制造微型冷却通道，该过程包括选择适当的光刻掩模、调整激光参数以及电化学沉积参数，以形成尺寸精确、布局优化的冷却通道；S4, using laser direct writing lithography technology and electrochemical deposition process to precisely manufacture micro cooling channels, which process includes selecting appropriate lithography masks, adjusting laser parameters and electrochemical deposition parameters to form cooling channels with precise dimensions and optimized layout; S5、开发基于环境感知的电源管理策略，利用温度、湿度环境传感器收集周围环境数据，结合芯片内部的工作负载信息，通过机器学习模型分析确定最优的功耗状态；S5. Develop a power management strategy based on environmental perception, use temperature and humidity environmental sensors to collect ambient data, combine it with the workload information inside the chip, and determine the optimal power consumption state through machine learning model analysis; S6、集成自适应频率调整技术，根据实时监测到的芯片温度和负载条件动态调整处理器的工作频率，采用高精度温度传感器和信号处理算法，确保快速且精确的频率调节响应；S6, integrated adaptive frequency adjustment technology, dynamically adjusts the processor's operating frequency according to the real-time monitored chip temperature and load conditions, and uses high-precision temperature sensors and signal processing algorithms to ensure fast and accurate frequency adjustment response; S7、利用多层混合信号集成技术，通过特制的隔离层材料有效隔离模拟、数字和射频模块，减少相互之间的干扰，设计时考虑信号路径和隔离层的布局优化；S7. Use multi-layer mixed signal integration technology to effectively isolate analog, digital and RF modules through special isolation layer materials to reduce mutual interference. Consider the layout optimization of signal paths and isolation layers during design. S8、集成含有微胶囊的智能材料于关键结构中，以实现自我修复机制，微胶囊中含有的修复剂能在材料出现微裂纹时自动释放，通过化学反应修复损伤，增强芯片的长期可靠性，开展详细的实验验证微胶囊的分布均匀性、修复效率和对芯片性能的影响；S8. Integrate smart materials containing microcapsules into key structures to achieve a self-healing mechanism. The repair agent contained in the microcapsules can be automatically released when microcracks appear in the material, repair the damage through chemical reactions, and enhance the long-term reliability of the chip. Carry out detailed experiments to verify the distribution uniformity of the microcapsules, the repair efficiency, and the impact on chip performance; S9、实施环保生产工艺，优化化学试剂的选择和使用，引入能源回收和废物处理系统，确保生产过程的环境友好性，通过实时监测生产线上的数据，利用数据驱动方法识别生产瓶颈和效率提升机会，应用人工智能算法进行生产流程优化，提升生产效率和降低成本；S9. Implement environmentally friendly production processes, optimize the selection and use of chemical reagents, introduce energy recovery and waste treatment systems, ensure the environmental friendliness of the production process, monitor data on the production line in real time, use data-driven methods to identify production bottlenecks and efficiency improvement opportunities, and apply artificial intelligence algorithms to optimize production processes, improve production efficiency and reduce costs; S10、设计并实施一套全面的性能和可靠性测试方案，包括环境测试、机械测试和长期稳定性测试，确保芯片在各种极端条件下的性能和稳定性，对测试过程中发现的问题进行根本原因分析，并反馈至设计和制造过程中进行优化。S10. Design and implement a comprehensive performance and reliability test program, including environmental testing, mechanical testing, and long-term stability testing, to ensure the performance and stability of the chip under various extreme conditions, conduct root cause analysis on problems found during the test, and provide feedback to the design and manufacturing process for optimization. 2.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述激光参数包括功率、焦距和扫描速度，所述电化学沉积参数为电解液浓度和电流密度。2. A method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that the laser parameters include power, focal length and scanning speed, and the electrochemical deposition parameters are electrolyte concentration and current density. 3.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述隔离层材料为高介电常数材料，所述环境测试为高低温测试、湿度测试与盐雾测试、所述机械测试为振动、冲击测试。3. The manufacturing method of a satellite navigation three-dimensional chip according to claim 1 is characterized in that: the isolation layer material is a high dielectric constant material, the environmental test is a high and low temperature test, a humidity test and a salt spray test, and the mechanical test is a vibration and impact test. 4.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述机器学习模型为深度神经网络通过训练数据集训练模型，所述数据集训练模型包括特征选择、模型参数调优和交叉验证步骤，以确保预测的准确性和泛化能力，所述数据集包括温度、湿度、工作负载与功耗状态的历史数据。4. According to claim 1, a method for manufacturing a satellite navigation three-dimensional chip is characterized in that: the machine learning model is a deep neural network training model through a training data set, and the data set training model includes feature selection, model parameter tuning and cross-validation steps to ensure the accuracy and generalization ability of the prediction, and the data set includes historical data of temperature, humidity, workload and power consumption status. 5.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述高精度温度传感器采用基于微机电系统技术的高精度温度传感器，所述信号处理算法包括滤波、去噪和温度补偿步骤，使用数字信号处理器实现实时数据处理，确保温度数据的准确性和可靠性。5. According to claim 1, a method for manufacturing a satellite navigation three-dimensional chip is characterized in that: the high-precision temperature sensor adopts a high-precision temperature sensor based on micro-electromechanical system technology, the signal processing algorithm includes filtering, denoising and temperature compensation steps, and uses a digital signal processor to realize real-time data processing to ensure the accuracy and reliability of temperature data. 6.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述隔离层的布局优化采用具有高介电常数和低损耗的材料，氧化铝或氮化硅有效隔离不同功能模块间的电磁干扰。6. A method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: the layout of the isolation layer is optimized by using materials with high dielectric constant and low loss, such as aluminum oxide or silicon nitride to effectively isolate electromagnetic interference between different functional modules. 7.根据权利要求1所述的一种卫星导航三维芯片的制造方法，其特征在于：所述微胶囊分布均匀性、修复效率和芯片性能影响的实验验证包括扫描电子显微镜分析、能量色散X射线光谱分析和机械性能测试，以验证微胶囊在智能材料中的均匀分布情况、在不同应力条件下的修复效率，以及自我修复机制对芯片电气性能的影响。7. According to claim 1, a method for manufacturing a satellite navigation three-dimensional chip is characterized in that: the experimental verification of the uniformity of microcapsule distribution, repair efficiency and chip performance impact includes scanning electron microscopy analysis, energy dispersion X-ray spectroscopy analysis and mechanical properties testing to verify the uniform distribution of microcapsules in smart materials, the repair efficiency under different stress conditions, and the impact of the self-repair mechanism on the electrical performance of the chip.
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