CN118606193B - Automated connection verification method, device, terminal, medium and program product for chip interconnect manager - Google Patents
Automated connection verification method, device, terminal, medium and program product for chip interconnect manager Download PDFInfo
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Abstract
The application provides an automatic connection verification method, device, terminal, medium and program product for a chip interconnection manager, wherein the method comprises the steps of obtaining a design form of a chip design to be verified; the method comprises the steps of carrying out macro definition processing on a design table to generate a macro definition file for connection relation among all modules connected through an interconnection manager in a chip design to be verified, constructing a test case file according to acquired target chip design verification requirements and the macro definition file, writing HEX files obtained by compiling the macro definition file and the test case file into the chip design to be verified, and operating the HEX files so that the verification platform can carry out automatic connection verification based on the interconnection manager on the chip design to be verified. The application can automatically generate the corresponding macro definition file along with the update of the version of the chip design, thereby automatically connecting each module in the chip design in the verification process, and leading the verification process to be simple, efficient and visual.
Description
Technical Field
The present application relates to the field of integrated circuit design technologies, and in particular, to an automated connection verification method, apparatus, terminal, medium, and program product for a chip interconnection manager.
Background
When verifying a chip design, the modules within the chip often need to be interconnected to work together. In the verification scheme in the prior art, a mode of manually configuring and connecting the modules one by one is generally adopted to verify the connection state and the correctness of data receiving and transmitting. However, for the complex and tedious connection between the internal modules, and up to hundreds of chips with connection ports, the manual configuration and the one-by-one connection mode can generate huge workload when verification is performed, and it is difficult or impossible to cover the whole area, especially, the data is transmitted and received between a plurality of modules at the same time. And with the updating of the chip design version, the register configuration bit corresponding to different modules is changed to a new position or increased or decreased, each module needs to be checked and changed in sequence every time the new version is released, and then the test case and the test platform are manually changed, so that the verification work is complex, tedious, time-consuming and labor-consuming, poor in readability and easy to make mistakes.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide an automated connection verification method, apparatus, terminal, medium and program product for a chip interconnection manager, which are used for solving the problems of complex and tedious verification work, time and effort consuming, poor readability and error prone caused by a manual modification during chip verification in the prior art.
In order to achieve the above and other related objects, a first aspect of the present application provides an automated connection verification method for a chip interconnection manager, which includes obtaining a design table of a chip design to be verified, performing macro definition processing on the design table to generate a macro definition file for describing a connection relationship between modules connected through the interconnection manager inside the chip design to be verified, constructing a test case file according to an obtained target chip design verification requirement and the macro definition file, writing an HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified, and running the HEX file, so that a verification platform performs automated connection verification based on the interconnection manager on the chip design to be verified.
In some embodiments of the first aspect of the present application, macro definition processing is performed on the design table to generate a macro definition file for describing connection relationships between modules connected through an interconnection manager inside the chip design to be verified, where the process includes dividing each module connected through the interconnection manager inside the chip design to be verified in the design table by using a set separation identifier, determining a plurality of module input ports and a plurality of module output ports inside the chip design to be verified according to port information of each module, and generating a macro definition file for describing connection relationships between modules inside the chip design to be verified according to the determined plurality of module input ports and the determined plurality of module output ports by using an index value-based string automatic generation manner.
In some embodiments of the first aspect of the present application, according to the determined multiple module input ports and multiple module output ports, a macro definition file for describing the connection relationship of the internal module of the chip design to be verified is generated by an automatic generation mode based on the character string of the index value, where the process includes assigning a value to each module input port and each module output port according to the sequence of the ports in the design table, to obtain the port index value of each module input port and each module output port; and generating a plurality of macro definition character strings for describing the connection relation between the module ports according to the sequence of the port index values and the set character string structure, and further obtaining a macro definition file for describing the connection relation of the internal module of the chip design to be verified.
In some embodiments of the first aspect of the present application, the string structure includes a module input port name, a connection relationship identifier, and a module output port name.
In some embodiments of the first aspect of the present application, each macro definition string further carries corresponding register configuration information, where, when performing chip design verification, the corresponding port is connected according to the register configuration information carried by each macro definition string.
In some embodiments of the first aspect of the present application, the obtaining manner of the register configuration information corresponding to each macro definition string includes determining an access address of each macro definition string according to a port index value of a module output port in each macro definition string and a base address of a register, determining the port index value of a module input port in each macro definition string as the configuration information of each macro definition string, and outputting the access address and the configuration information of each macro definition string as the register configuration information corresponding to each macro definition string.
In order to achieve the above object and other related objects, a second aspect of the present application provides an automated connection verification device for a chip interconnection manager, which includes an obtaining module configured to obtain a design form of a chip design to be verified, a macro definition module connected to the obtaining module and configured to perform macro definition processing on the design form to generate a macro definition file for describing a connection relationship between modules connected through the interconnection manager inside the chip design to be verified, a test case construction module connected to the macro definition module and configured to construct a test case file according to an obtained target chip design verification requirement and the macro definition file, and a verification module connected to the test case construction module and configured to write an HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and operate the HEX file, so that the verification module performs automated connection verification based on the interconnection manager on the chip design to be verified.
To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the automated connection verification method for a chip interconnection manager.
To achieve the above and other related objects, a fourth aspect of the present application provides a computer program product, including computer program code, which when run on a computer causes the computer to implement the automated connection verification method for a chip interconnection manager.
To achieve the above and other related objects, a fifth aspect of the present application provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory, where the processor executes the computer program to implement the automated connection verification method for a chip interconnection manager.
As described above, the automated connection verification method, apparatus, terminal, medium and program product for a chip interconnection manager of the present application have the following beneficial effects:
The application can automatically generate the corresponding macro definition file along with the update of the version of the chip design, thereby automatically connecting each module in the chip design in the verification process, and leading the verification process to be simple, efficient and visual.
Drawings
Fig. 1 is a flowchart of an automated connection verification method facing a chip interconnection manager according to an embodiment of the application.
Fig. 2 is a schematic diagram of a connection structure of a chip design and verification platform according to an embodiment of the application.
Fig. 3 is a schematic structural diagram of an automated connection verification device facing a chip interconnection manager according to an embodiment of the application.
Fig. 4 is a schematic structural diagram of an electronic terminal according to an embodiment of the application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In embodiments of the present application, the words "first," "second," and the like are used to distinguish between identical or similar items that have substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the embodiments of the present application, words such as "exemplary" or "such as" denote examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or" describes an association of associated objects, meaning that there may be three relationships, e.g., A and/or B, and that there may be A alone, while A and B are present, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a, b or c) of a, b, c, a-b, a-c, b-c or a-b-c may be represented, wherein a, b, c may be single or plural.
The application provides an automatic connection verification method, device, terminal, medium and program product for a chip interconnection manager, wherein the method comprises the steps of obtaining a design form of a chip design to be verified; the method comprises the steps of carrying out macro definition processing on a design table to generate a macro definition file for connection relation among all modules connected through an interconnection manager in a chip design to be verified, constructing a test case file according to acquired target chip design verification requirements and the macro definition file, writing HEX files obtained by compiling the macro definition file and the test case file into the chip design to be verified, and operating the HEX files so that the verification platform can carry out automatic connection verification based on the interconnection manager on the chip design to be verified. The application can automatically generate the corresponding macro definition file along with the update of the version of the chip design, thereby automatically connecting each module in the chip design in the verification process, and leading the verification process to be simple, efficient and visual.
To facilitate an understanding of embodiments of the present application, a detailed description is first provided with reference to fig. 1. Fig. 1 shows a flowchart of an automated connection verification method for a chip interconnection manager in an embodiment of the present application. The automatic connection verification method for the chip interconnection manager in the embodiment mainly comprises the following steps:
step S101, a design table of a chip design to be verified is obtained.
It should be noted that the design table is used to describe each module and the connection relationship between each module in the chip design to be verified.
In one embodiment, the design table is in the format of csv.
And step S102, performing macro definition processing on the design table to generate a macro definition file for describing the connection relation between the modules connected through the interconnection manager inside the chip design to be verified.
It should be noted that the interconnection manager supports a plurality of inputs and a plurality of outputs, and these input/output ports may be assigned to modules connected to the interconnection manager for use as their inputs or outputs. On the product, the input and output signals of the modules can be mutually connected, so that the modules can be mutually matched for use. The interconnection manager may configure these connections.
In one embodiment, the macro definition processing is performed on the design table to generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager in the chip design to be verified, and the macro definition file for describing the connection relationship between the modules in the chip design to be verified is generated by using a set separation identifier to separate the modules connected through the interconnection manager in the chip design to be verified in the design table, determining a plurality of module input ports and a plurality of module output ports in the chip design to be verified according to port information of the modules, and automatically generating a character string based on index values according to the determined plurality of module input ports and the determined plurality of module output ports.
In an embodiment, according to the determined multiple module input ports and multiple module output ports, generating a macro definition file for describing the connection relation of the internal module of the chip design to be verified through an automatic generation mode of character strings based on index values, wherein the macro definition file comprises the steps of assigning values to each module input port and each module output port according to the sequence of ports in the design table to obtain the port index values of each module input port and each module output port; and generating a plurality of macro definition character strings for describing the connection relation between the module ports according to the sequence of the port index values and the set character string structure, and further obtaining a macro definition file for describing the connection relation of the internal module of the chip design to be verified.
In one embodiment, the macro definition file is a file in the.h format.
In one embodiment, the character string structure comprises a module input port name, a connection relationship identifier, and a module output port name.
The process of generating the macro definition string will be explained in detail as follows:
In the design table, each module inside the chip design is partitioned by a set partition mark (the partition mark may be comma, pause sign, etc., and is not limited here).
Further, the design form after the separation process (format is. Csv) is input into python. And determining a plurality of module input ports and a plurality of module output ports according to the port information of each module by using the python language.
Further, the determined plurality of module input ports and the determined plurality of module output ports are divided (spilt) into two queues, queue1 (queue 1) and queue2 (queue 2), respectively, using split functions in python.
Note that the split () function is a built-in method of Python character strings for dividing one character string into a plurality of sub-character strings by a specified separation Fu Cafen and storing the sub-character strings in a list. The basic syntax is str.split (", num = string. Count (str)) [ n ]. Where str is a separator, default to all empty characters, including space, line feed (\n), tab (\t), etc. num is the number of divisions, if there is a parameter num, it is divided into only num+1 substrings, and each substring can be assigned a new variable. Defaulting to-1, i.e., separating all. [ n ] represents selecting the nth fragment.
Queue-in multi-threaded programming, when multiple threads need to access shared data, race conditions are likely to occur, i.e., multiple threads attempt to access and modify the same data at the same time, resulting in inconsistent or lost data. A queue is a data structure used to solve this problem that provides a thread-safe way to manage data, ensuring that multiple threads can safely access and modify it.
Further, according to the sequence of the ports in the design table, each module input port and each module output port are assigned to obtain the port index value of each module input port and each module output port.
The port index values of the ports have an order, and the order of the index values reflects the connection order of the ports.
Further, according to the order of the port index values, a plurality of macro definition strings for describing the connection relations between the ports of the modules are generated according to the character string structures of the port names of the input ports of the modules, the connection relation identification symbols and the port names of the output ports of the modules.
For example, if the connection identifier is "__", and the input port a1 of the module a and the output port B2 of the module B have a connection relationship, the corresponding macro definition string is "a1__ B2".
It should be noted that, the connection relationship identifier is not limited in the present invention, and those skilled in the art may set the connection relationship identifier according to actual needs.
Further, the write () function in the python language is used to write the macro definition character strings generated in the above steps into a blank h file and save the blank h file, so as to obtain a macro definition file for describing the connection relation of the internal module of the chip design to be verified.
It should be noted that, when a file is opened in the write mode, data may be written into the file using the write () function. The parameters of the write () function are the data to be written to the file and the data type may be a string or a byte stream.
In an embodiment, each macro definition string further carries corresponding register configuration information.
In an embodiment, the method for acquiring the register configuration information corresponding to each macro definition string includes determining an access address of each macro definition string according to a port index value of a module output port in each macro definition string and a base address of a register, determining the port index value of a module input port in each macro definition string as the configuration information of each macro definition string, and outputting the access address and the configuration information of each macro definition string as the register configuration information corresponding to each macro definition string.
In one embodiment, the access address for each macro definition string is calculated by the following equation:
access address of macro definition string = base address of general register +4 x port index value of module output port in macro definition string;
the port index value of the output port in the module in the 4 x macro definition character string is the offset address of the register corresponding to the macro definition character string.
And step S103, constructing a test case file according to the acquired target chip design verification requirement and the macro definition file.
In a specific embodiment, the test case is used to verify the function of the internal module of the chip design to be verified. In the constructed test case file, the connection relation of the internal modules of the chip design to be verified is defined by adopting a macro definition character string in the macro definition file.
In one embodiment, the test case file is a c-format file.
And step S104, writing HEX files obtained by compiling the macro definition files and the test case files into the chip design to be verified and running the HEX files so that the verification platform can perform automatic connection verification based on an interconnection manager on the chip design to be verified.
It should be noted that the HEX file is a hexadecimal (Hexadecimal) encoded file format, and is mainly used for storing and transmitting binary data. Files of this format are very common in the field of electronics and computer engineering, particularly in firmware programming and embedded system development.
In one embodiment, as shown in fig. 2, the obtained HEX file is written into the RAM of the chip design to run the HEX file through the RAM, and the automation connection between the ports of each module in the chip design is performed by using the chip interconnection manager through the file running of the HEX.
In one embodiment, the automated connection between the ports of each module in the chip design by the file running of the HEX using the chip interconnection manager includes:
and for each macro definition character string in the HEX file, accessing a corresponding register according to the access address in the register configuration information carried by the macro definition character string. And configuring configuration information in the register configuration information carried by the macro definition character string to the register to complete the connection between the module input port and the module output port corresponding to the macro definition character string. Wherein this is done by the interconnection manager.
For example, a string is defined for a macro of "a1__ b 2". The process of connecting the input port a1 of the module A and the output port B2 of the module B specifically comprises accessing the corresponding register through the access address in the register address information carried by the macro definition character string of "a1__ B2". And configuring configuration information in the register address information carried by the macro definition character string to the register to complete connection between an input port a1 and an output port b2 corresponding to the macro definition character string of 'a 1__ b 2'.
It should be noted that, in the embodiment of the present invention, since the connection configuration in the test case is replaced with the macro definition string, with the update of the version, the test case can be automatically updated to the latest connection configuration without manually changing the configuration when the chip design verification is performed.
In one embodiment, the interconnection manager may employ an S32K3XX trigger MUX module. It should be noted that the present invention is not limited to the type of the interconnection manager, and those skilled in the art may select according to actual requirements.
In one embodiment, as shown in FIG. 2, the verification platform is built in verilog or system verilog. Verifying the chip design through a Driver (Driver) and a Monitor (Monitor) in a verification platform;
the Driver is a testing component for simulating an external signal or stimulus to test the hardware design. On the ports of the modules, the Driver is responsible for providing input signals, which may be fixed values, periodically varying signals, or complex waveforms dynamically generated according to the test requirements. The Driver may be simple, providing only a few predefined values, or complex, capable of simulating various characteristics of the real world signal. In Verilog Driver can be implemented by using initial or analysis blocks to generate test vectors. The input signal is dynamically changed using a parameterized or programmed method. The # delay operator is used in combination to control the timing of the signal changes.
Monitor is a test component that observes and records the behavior and response of a hardware design during testing. Monitor is typically connected to the output port of the design, capturing the variation of the output signal and comparing it to the expected result to verify the correctness of the design. In Verilog, monitor can be implemented by using an initial or an analysis block to observe the output signal. Recording changes in the signal may involve writing the data to a file or displaying it in a simulated environment. Whether the signal meets expectations, such as using a $display or $monitor system task, is checked by asserting (Assertions).
In verification of chip designs, drivers and monitors are often used together to create a complete test environment. Driver provides input signals, monitor observes the output response and verifies that the behavior of the design is expected.
In one embodiment, errors and alarms in chip design can be quickly located through macro definition strings.
Fig. 3 is a schematic block diagram of an automated connection verification device for a chip interconnection manager provided in an embodiment of the present application.
As shown in fig. 3, the automated connection verification device for a chip interconnection manager includes:
an obtaining module 31, configured to obtain a design table of a chip design to be verified;
The macro definition module 32 is connected with the acquisition module 31 and is used for performing macro definition processing on the design form to generate a macro definition file for describing the connection relation between the modules connected through the interconnection manager inside the chip design to be verified;
The test case construction module 33 is connected with the macro definition module 32 and is used for constructing a test case file according to the acquired target chip design verification requirement and the macro definition file;
And the verification module 34 is connected with the test case construction module 33, and is used for writing the HEX file obtained by compiling the macro definition file and the test case file into the chip design to be verified and running the HEX file, so that the verification platform can perform automatic connection verification based on an interconnection manager on the chip design to be verified.
It should be understood that the specific process of each module to perform the corresponding steps is described in detail in the above method embodiments, and is not described herein for brevity.
It should also be understood that the division of the modules in the embodiment of the present application is merely a logic function division, and other division manners may be actually implemented. In addition, each functional module in the embodiments of the present application may be integrated in one processor, or may exist alone physically, or two or more modules may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules.
In one embodiment, the macro definition processing is performed on the design table to generate a macro definition file for describing the connection relationship between the modules connected through the interconnection manager in the chip design to be verified, and the macro definition file for describing the connection relationship between the modules in the chip design to be verified is generated by using a set separation identifier to separate the modules connected through the interconnection manager in the chip design to be verified in the design table, determining a plurality of module input ports and a plurality of module output ports in the chip design to be verified according to port information of the modules, and automatically generating a character string based on index values according to the determined plurality of module input ports and the determined plurality of module output ports.
In an embodiment, according to the determined multiple module input ports and multiple module output ports, generating a macro definition file for describing the connection relation of the internal module of the chip design to be verified through an automatic generation mode of character strings based on index values, wherein the macro definition file comprises the steps of assigning values to each module input port and each module output port according to the sequence of ports in the design table to obtain the port index values of each module input port and each module output port; and generating a plurality of macro definition character strings for describing the connection relation between the module ports according to the sequence of the port index values and the set character string structure, and further obtaining a macro definition file for describing the connection relation of the internal module of the chip design to be verified.
In one embodiment, the character string structure comprises a module input port name, a connection relationship identifier, and a module output port name.
In one embodiment, each macro definition string further carries corresponding register configuration information, wherein when chip design verification is performed, the corresponding ports are connected according to the register configuration information carried by each macro definition string.
In an embodiment, the method for acquiring the register configuration information corresponding to each macro definition string includes determining an access address of each macro definition string according to a port index value of a module output port in each macro definition string and a base address of a register, determining the port index value of a module input port in each macro definition string as the configuration information of each macro definition string, and outputting the access address and the configuration information of each macro definition string as the register configuration information corresponding to each macro definition string.
Fig. 4 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. As shown in fig. 4, the electronic terminal comprises at least one processor 401, a memory 402, at least one network interface 403 and a user interface 405. The various components in the device are coupled together by a bus system 404. It is to be appreciated that bus system 404 is employed to facilitate connected communications between these components. The bus system 404 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 4.
The user interface 405 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 402 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 402 in the embodiment of the present invention is used to store various kinds of data to support the operation of the electronic terminal 400. Examples of such data include any executable programs for operation on the electronic terminal 400, such as an operating system 4021 and application programs 4022, and the operating system 4021 contains various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application programs 4022 may include various application programs such as a media player (MEDIA PLAYER), a Browser (Browser), and the like for implementing various application services. The method for verifying the automated connection of the chip interconnection manager provided by the embodiment of the invention can be contained in the application 4022.
The automatic connection verification method for the chip interconnection manager disclosed in the embodiment of the invention can be applied to the processor 401 or realized by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 401 or by instructions in the form of software. The Processor 401 may be a general purpose Processor, a digital signal Processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. Processor 401 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. The general purpose processor 401 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex programmable logic devices (CPLDs, complex Programmable Logic Device) for performing the aforementioned methods.
According to the method provided by the embodiment of the application, the application further provides a computer program product, which comprises computer program code for enabling a computer to execute the automatic connection verification facing the chip interconnection manager in the embodiment shown in fig. 1 when the computer program code runs on the computer.
According to the method provided by the embodiment of the application, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores program code, and when the program code runs on a computer, the computer is caused to execute the automatic connection verification facing to the chip interconnection manager in the embodiment shown in fig. 1.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between 2 or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the above-described embodiments, the functions of the respective functional units may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, magnetic tape), optical media (e.g., high density digital video discs (digital video disc, DVD), or semiconductor media (e.g., solid State Drives (SSDs)), etc.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
In summary, the application provides an automatic connection verification method, device, terminal, medium and program product for a chip interconnection manager, which comprises the steps of obtaining a design form of a chip design to be verified, performing macro definition processing on the design form to generate a macro definition file for connection relation among modules connected through the interconnection manager in the chip design to be verified, constructing a test case file according to obtained target chip design verification requirements and the macro definition file, writing HEX files obtained by compiling the macro definition file and the test case file into the chip design to be verified, and running the HEX files for the verification platform to perform automatic connection verification based on the interconnection manager on the chip design to be verified. The application can automatically generate the corresponding macro definition file along with the update of the version of the chip design, thereby automatically connecting each module in the chip design in the verification process, and leading the verification process to be simple, efficient and visual.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
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| CN116050315A (en) * | 2022-06-15 | 2023-05-02 | 北京爱芯科技有限公司 | Verification method and device and electronic equipment |
| CN117725869A (en) * | 2023-12-22 | 2024-03-19 | 山东云海国创云计算装备产业创新中心有限公司 | Assertion development method, chip verification method, device, equipment and medium |
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| CN110347542A (en) * | 2019-05-31 | 2019-10-18 | 北京华捷艾米科技有限公司 | A kind of port connection method, system and medium improving verification environment reusability |
| CN112631852B (en) * | 2020-12-22 | 2023-04-28 | 海光信息技术股份有限公司 | Macro checking method, macro checking device, electronic equipment and computer readable storage medium |
| CN115618777A (en) * | 2022-10-26 | 2023-01-17 | 北京物芯科技有限责任公司 | File generation method, device, equipment and storage medium |
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| CN116050315A (en) * | 2022-06-15 | 2023-05-02 | 北京爱芯科技有限公司 | Verification method and device and electronic equipment |
| CN117725869A (en) * | 2023-12-22 | 2024-03-19 | 山东云海国创云计算装备产业创新中心有限公司 | Assertion development method, chip verification method, device, equipment and medium |
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