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CN118604424B - Current detection circuit, power chip and electronic equipment - Google Patents

Current detection circuit, power chip and electronic equipment Download PDF

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Publication number
CN118604424B
CN118604424B CN202410264018.6A CN202410264018A CN118604424B CN 118604424 B CN118604424 B CN 118604424B CN 202410264018 A CN202410264018 A CN 202410264018A CN 118604424 B CN118604424 B CN 118604424B
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Prior art keywords
current
field effect
source
effect transistor
tube
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CN118604424A (en
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杨国顺
曹智博
郑耿
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Shenzhen Jingkong Integrated Semiconductor Co ltd
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Shenzhen Jingkong Integrated Semiconductor Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

A current detection circuit, a power chip and electronic equipment belong to the technical field of inductance current detection, and the current of a first PMOS tube is reduced through a fifth field effect tube to generate detection current, a common gate amplifier of the first field effect tube and a second field effect tube is used as a feed-forward path of a feedback system, a third field effect tube is used as a feedback link of a negative feedback loop, so that the first PMOS tube and the fifth field effect tube have similar source-drain voltages, the accuracy of current detection is improved, meanwhile, if the inductance current is negative, the first PMOS tube generates negative voltage drop, namely, the source voltage of a fourth field effect tube is higher than the voltage of a first power supply, and the source voltage of the second field effect tube is still lower than the voltage of the first power supply, and the other input voltage of a common gate amplifier is similar, so that the fifth field effect tube still works and generates accurate negative detection current, and the positive inductance current and the negative inductance current are detected simultaneously.

Description

Current detection circuit, power chip and electronic equipment
Technical Field
The application belongs to the technical field of inductance current detection, and particularly relates to a current detection circuit, a power chip and electronic equipment.
Background
In current-mode dc-dc converters, inductor current is required as a feedback signal control loop to dynamically adjust the duty cycle of the control signal, and therefore such converters require inductor current detection techniques. The inductor current detection technology can be divided into on-chip inductor current detection and off-chip inductor current detection according to the position of the power tube. Conventional on-chip inductor current detection techniques are based on detecting the tube current. The technology has the advantages of high efficiency and easy integration, but has the main problem that only positive inductor current can be detected.
For example, as shown in fig. 1, a related current detection circuit is shown in fig. 1, a circuit in a dashed box corresponding to reference numeral 10 is a current detection circuit, a circuit in a dashed box corresponding to reference numeral 20 is a current mirror, U1 is a comparator, a signal corresponding to reference numeral 90 is a slope compensation current, and bias currents I1 and I2 provide the same pull-down currents for two identical PNP transistors Q1 and Q2. M1 is a power tube of the dc-dc converter. M2 is defined as a reference power transistor, so that PMOS transistors M1 and M2 are scaled such that the aspect ratio of the transistors on the output side of the circuit is much greater than the aspect ratio of the transistors on the detection side of the circuit. Therefore, the current on the detection side is not only much smaller than the current on the output side, but also proportional thereto.
The output current is the difference between the current flowing through M1 (with a larger aspect ratio) and the current flowing through the other small current source I1. The sense current flowing through the internal sense resistor R is the difference between the current flowing through M2 (having a smaller aspect ratio) and the current flowing through the other small current source I2. Thus, the current flowing through the sense resistor is substantially proportional to and much less than the current flowing through the load.
However, the current detection circuit can only detect the positive current flowing through the inductor L but cannot detect the negative current thereof. When negative current flows through the inductor, the voltage at node D will be higher than the supply voltage VCC, while Q1 and Q2 cannot regulate the voltage at node A to be as high as the voltage at node B. Thus, the current sense amplifier will be in an open loop state and the sense current will no longer be proportional to the load current in the negative direction.
The associated current sensing circuit cannot sense the negative current of the inductor.
Disclosure of Invention
The application aims to provide a current detection circuit, a power chip and electronic equipment, and aims to solve the problem that the related current detection circuit cannot detect negative current of an inductor.
The embodiment of the application provides a current detection circuit which is connected with a direct current-direct current converter, wherein the direct current-direct current converter comprises a first PMOS tube and a first NMOS tube, and the current detection circuit comprises a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a first current, a second current source, a third current source and a fourth current source;
The source electrode of the fourth field effect tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the fourth field effect tube is connected with the source electrode of the second field effect tube and the positive electrode of the first current source, the source electrode of the fifth field effect tube and the source electrode of the first PMOS tube are connected with a first power supply, the drain electrode of the fifth field effect tube is connected with the source electrode of the first field effect tube and the source electrode of the third field effect tube, the grid electrode of the second field effect tube is connected with the grid electrode of the first field effect tube, the drain electrode of the first field effect tube and the positive electrode of the third current source, and the drain electrode of the second field effect tube is connected with the grid electrode of the third field effect tube and the positive electrode of the fourth current source together serve as an output current output end of the current detection circuit so as to output current;
The source electrode of the first NMOS tube, the cathode of the first current source, the cathode of the second current source, the cathode of the third current source and the cathode of the fourth current source are commonly connected to the power ground.
In one embodiment, the circuit further comprises a first switch, a second switch, a sixth field effect transistor and a fifth current source;
The first end of the first switch is connected with the drain electrode of the fourth field effect transistor and the positive electrode of the first current source, and the second end of the first switch is connected with the source electrode of the second field effect transistor and the second end of the second switch;
The source electrode of the sixth field effect transistor is connected with the first power supply, the drain electrode of the sixth field effect transistor is connected with the positive electrode of the fifth current source and the first end of the second switch, and the negative electrode of the fifth current source is connected with the power supply ground.
In one embodiment, the current I 5 of the fifth current source is derived from the following formula (I) 5+I2)RM6＝(I4+I3)RM5
Wherein I 2 is the current of the second current source, R M6 is the equivalent on-resistance of the sixth field effect transistor, I 4 is the current of the fourth current source, I 3 is the current of the third current source, and R M5 is the equivalent on-resistance of the fifth field effect transistor.
In one embodiment, at most one of the first switch SW1 and the second switch SW2 is closed at the same time.
In one embodiment, a third switch is further included;
The first end of the third switch is connected with the drain electrode of the fifth field effect transistor, and the second end of the third switch is connected with the source electrode of the first field effect transistor and the source electrode of the third field effect transistor.
In one embodiment, the current I 4 of the fourth current source I4 is derived from the following formula I mpRmp+(I1+I2)RM4＝IM5RM5
Wherein I M5 is the source-drain current of the fifth fet M5, R mp is the equivalent on-resistance of the first PMOS MP, I 1 is the current of the first current source, I 2 is the current of the second current source, R M4 is the equivalent on-resistance of the fourth fet, and R M5 is the equivalent on-resistance of the fifth fet.
In one embodiment, the output current I out satisfies the following calculation formula:
Wherein, R mp is the equivalent on-resistance of the first PMOS tube, and I mp is the source leakage current of the first PMOS tube.
In one embodiment, the first PMOS transistor is a power up transistor.
The embodiment of the invention also provides a power chip, which comprises the current detection circuit.
The embodiment of the invention also provides electronic equipment, which comprises a first PMOS tube, a first NMOS tube, an inductor, a capacitor, a load resistor and the current detection circuit;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the first end of the inductor, and the second end of the inductor is connected with the anode of the capacitor and the anode of the load resistor;
the negative electrode of the capacitor and the negative electrode of the load resistor are commonly connected to the power ground.
Compared with the prior art, the embodiment of the invention has the advantages that the fifth field effect transistor is used for reducing the current of the first PMOS transistor to generate detection current, the common gate amplifier comprising the first field effect transistor and the second field effect transistor is used as a feed-forward path of a feedback system, the third field effect transistor is used as a feedback link of a negative feedback loop, so that the first PMOS transistor and the fifth field effect transistor have similar source-drain voltages, the accuracy of current detection is improved, meanwhile, if the inductance current is negative, the first PMOS transistor generates negative voltage drop, namely, the source voltage of the fourth field effect transistor is higher than the voltage of the first power supply, and the source voltage of the second field effect transistor is still lower than the voltage of the first power supply and is similar to the other input voltage of the common gate amplifier, so that the fifth field effect transistor still works and generates accurate negative detection current under the condition, and the positive inductance current and the negative inductance current are detected simultaneously.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of an exemplary circuit of an associated current sense circuit;
FIG. 2 is a schematic diagram of an exemplary current detection circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another exemplary current detection circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another exemplary current detection circuit according to an embodiment of the present application;
fig. 5 is a schematic circuit diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 2 is a schematic diagram of a current detection circuit according to a preferred embodiment of the present application, and for convenience of explanation, only the portions related to the present embodiment are shown, and the details are as follows:
The current detection circuit is connected with a direct current-direct current converter, wherein the direct current-direct current converter comprises a first P-channel metal-oxide-semiconductor (PMOS) tube MP and a first N-type metal-oxide-semiconductor (NMOS) tube MN, and the current detection circuit comprises a first field effect tube M1, a second field effect tube M2, a third field effect tube M3, a fourth field effect tube M4, a fifth field effect tube M5, a first current source I1, a second current source I2, a third current source I3 and a fourth current source I4;
The source electrode of the fourth field effect tube M4 is connected with the drain electrode of the first PMOS tube MP and the drain electrode of the first NMOS tube MN, the drain electrode of the fourth field effect tube M4 is connected with the source electrode of the second field effect tube M2 and the positive electrode of the first current source I1, the source electrode of the fifth field effect tube M5 and the source electrode of the first PMOS tube MP are commonly connected with the first power supply VDD, the drain electrode of the fifth field effect tube M5 is connected with the source electrode of the first field effect tube M1 and the source electrode of the third field effect tube M3, the grid electrode of the second field effect tube M2 is connected with the grid electrode of the first field effect tube M1, the drain electrode of the first field effect tube M1 and the positive electrode of the third current source I3, the drain electrode of the second field effect tube M2 is connected with the grid electrode of the third field effect tube M3 and the positive electrode of the second current source I2, and the positive electrode of the fourth current source I4 are commonly used as the output current output end of the current detection circuit to output current Iout.
The source of the first NMOS transistor MN, the cathode of the first current source I1, the cathode of the second current source I2, the cathode of the third current source I3 and the cathode of the fourth current source I4 are commonly connected to the power ground.
It should be noted that the first PMOS transistor MP and the first NMOS transistor MN are power transistors of the dc-dc converter.
The drain electrode of the fourth field effect transistor M4, the drain electrode of the first PMOS transistor MP and the drain electrode of the first NMOS transistor MN are commonly connected to the node LX, the voltage at the common junction of the drain electrode of the fifth field effect transistor M5, the source electrode of the first field effect transistor M1 and the source electrode of the third field effect transistor M3 is V1, and the voltage at the common junction of the drain electrode of the fourth field effect transistor M4, the source electrode of the second field effect transistor M2 and the positive electrode of the first current source I1 is V2.
Because the fifth field effect transistor M5 is configured to reduce the current of the first PMOS transistor to generate the detection current, the common gate amplifier including the first field effect transistor M1 and the second field effect transistor M2 is used as a feed-forward path of the feedback system, and the third field effect transistor M3 is used as a feedback link of the negative feedback loop, so that the first PMOS transistor MP and the fifth field effect transistor M5 have similar source-drain voltages, thereby improving accuracy of current detection. Meanwhile, if the inductor current is negative, the first PMOS MP will generate a negative voltage drop, i.e. the source voltage of the fourth fet M4 will be higher than the voltage Vdd of the first power supply. The fourth fet M4 makes the source voltage of the second fet M2 still lower than the voltage Vdd of the first power supply and similar to the other input voltage of the common-gate amplifier, so that the fifth fet M5 still works and generates an accurate negative sense current Iout in this case, thereby realizing the simultaneous detection of the positive and negative inductor currents. The second current source I2 and the third current source I3 are used to provide a current load for the common gate amplifying circuit.
In one embodiment, the first fet M1, the second fet M2, the third fet M3, the fourth fet M4, and the fifth fet M5 are P-type fets.
The five field effect transistors are realized by adopting the field effect transistors of the same type, and the process is simplified.
When the first PMOS tube MP is conducted, the first PMOS tube MP works as a switch, the source-drain voltage is lower, and the self equivalent on-resistance R mp is inversely proportional to the width-to-length ratio. Therefore, the drain-source voltage can be expressed as I mpRmp,Imp being the source-drain current of the first PMOS MP. Since V1 and V2 are similar, it can be obtained that:
ImpRmp+(I1+I2)RM4＝IM5RM5 (1)
Wherein I M5 is the source-drain current of the fifth fet M5, R mp is the equivalent on-resistance of the first PMOS MP, R M4 is the equivalent on-resistance of the fourth fet M4, and R M5 is the equivalent on-resistance of the fifth fet M5. Therefore, the width-to-length ratio of the fifth FET M5 is set Setting to a smaller value allows I M5 to maintain a lower value than I mp, thereby saving power consumption. But if itToo small may result in a large mismatch and thus affect the accuracy of the detected current. In addition, considering that the temperature of the first PMOS MP increases during operation, the fifth fet M5 needs to be placed adjacent to the first PMOS MP so that the temperatures of the first PMOS MP and the fifth PMOS MP are the same.
Because the first PMOS transistor MP and the fifth fet M5 have mismatch before, and the common gate amplifier has offset voltage, I out may have a certain error. In order to improve the detection accuracy, a trimming circuit is required to provide trimming bias current. When the first PMOS transistor MP is turned on, the node LX is at a high level, the load current is set to 0, and the current I 4 of the fourth current source I4 is trimmed to make Iout be 0. The modified I 4 can be obtained from the following calculation formula:
ImpRmp+(I1+I2)RM4＝IM5RM5 (2)
Furthermore, it is possible from fig. 2 that:
I4+I3+Iout＝IM5 (3)
thus, in combination of (1) (2) (3), after trimming I 4, the calculation formula of the detected current I out is:
as shown in fig. 3, the current detection circuit further includes a first switch SW1, a second switch SW2, a sixth fet M6 and a fifth current source I5.
The first end of the first switch SW1 is connected with the drain electrode of the fourth field effect transistor M4 and the positive electrode of the first current source I1, the second end of the first switch SW1 is connected with the source electrode of the second field effect transistor M2 and the second end of the second switch SW2, the source electrode of the sixth field effect transistor M6 is connected with the first power supply VDD, the drain electrode of the sixth field effect transistor M6 is connected with the positive electrode of the fifth current source I5 and the first end of the second switch SW2, and the negative electrode of the fifth current source I5 is connected with the power supply ground.
At the same time, at most one of the first switch SW1 and the second switch SW2 is closed.
It should be noted that, a main branch and a sub-branch are respectively set for the on and off states of the first PMOS MP. The main branch comprises a fourth field effect transistor M4, a first switch SW1 and a second field effect transistor M2, and the auxiliary branch comprises a sixth field effect transistor M6, a second switch SW2 and a second field effect transistor M2.
When the first PMOS tube MP is conducted, a main branch comprising the first PMOS tube MP works, and the third field effect tube M3 outputs positive or negative current.
When the first PMOS transistor MP is turned off, the secondary branch is turned on, and the third fet M3 outputs zero current, i.e., the output current Iout is 0. When the main branch is operated, if the source drain current Imp of the first PMOS MP is negative, the fourth fet M4 connected in series with the first PMOS MP provides a forward voltage drop, so that the voltage V2 is still lower than Vdd, and therefore, the differential input voltages V1 and V2 of the common gate amplifying circuit can be ensured to be similar, so that the fifth fet M5 can still operate normally, and a relatively accurate detection current is generated.
The situation when the first switch SW1 is closed and the second switch SW2 is opened is the same as that of fig. 2, and the description thereof will be omitted.
When the first PMOS tube MP is turned off, the first switch SW1 is turned off, and when the second switch SW2 is turned on, the side branch circuit works. In this case, by trimming the bias current I5, the gate voltage and current of the third fet M3 can be controlled so that the output current Iout becomes 0.
When the first PMOS transistor MP is turned off, the node LX is at a low level, the load current is set to 0, and the current I 5 (fifth current source) is trimmed to make I out be 0. The modified fifth current source I 5 can be obtained from the following equation:
(I5+I2)RM6＝(I4+I3)RM5
wherein R M6 is the equivalent on-resistance of the sixth fet M6.
As shown in fig. 4, the current detection circuit further includes a third switch SW3, wherein a first end of the third switch SW3 is connected to the drain of the fifth fet M5, and a second end of the third switch SW3 is connected to the source of the first fet M1 and the source of the third fet M3.
To match the first switch SW1 and the second switch SW2, a third switch SW3 is added to the detection branch, and the third switch SW3 is always closed during the detection phase.
The embodiment of the invention also provides a power chip which comprises the current detection circuit.
The embodiment of the invention also provides an electronic device, as shown in fig. 5, which comprises a first PMOS transistor MP, a first NMOS transistor MN, an inductance L, a capacitance C, a load resistor RL and the current detection circuit;
the drain electrode of the first PMOS tube MP is connected with the drain electrode of the first NMOS tube MN and the first end of the inductor L, the second end of the inductor L is connected with the positive electrode of the capacitor C and the positive electrode of the load resistor RL, and the negative electrode of the capacitor C and the negative electrode of the load resistor RL are commonly connected to the power ground.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
The foregoing embodiments are merely illustrative of the technical solutions of the present application, and not restrictive, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

1.一种电流检测电路，其特征在于，与直流-直流变换器连接，所述直流-直流变换器包括第一PMOS管和第一NMOS管；所述电流检测电路包括第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第一电流、第二电流源、第三电流源以及第四电流源；1. A current detection circuit, characterized in that it is connected to a DC-DC converter, the DC-DC converter includes a first PMOS tube and a first NMOS tube; the current detection circuit includes a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a first current, a second current source, a third current source and a fourth current source; 所述第四场效应管的源极与所述第一PMOS管的漏极和所述第一NMOS管的漏极连接，所述第四场效应管的漏极与所述第二场效应管的源极和第一电流源的正极连接，所述第五场效应管的源极和所述第一PMOS管的源极共接于第一电源，所述第五场效应管的漏极与所述第一场效应管的源极和所述第三场效应管的源极连接，所述第二场效应管的栅极与所述第一场效应管的栅极、所述第一场效应管的漏极以及所述第三电流源的正极连接，所述第二场效应管的漏极与所述第三场效应管的栅极和所述第二电流源的正极连接，所述第三场效应管的漏极和所述第四电流源的正极共同作为所述电流检测电路的输出电流输出端，以输出输出电流；The source of the fourth field effect transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, the drain of the fourth field effect transistor is connected to the source of the second field effect transistor and the positive electrode of the first current source, the source of the fifth field effect transistor and the source of the first PMOS transistor are connected to the first power supply, the drain of the fifth field effect transistor is connected to the source of the first field effect transistor and the source of the third field effect transistor, the gate of the second field effect transistor is connected to the gate of the first field effect transistor, the drain of the first field effect transistor and the positive electrode of the third current source, the drain of the second field effect transistor is connected to the gate of the third field effect transistor and the positive electrode of the second current source, and the drain of the third field effect transistor and the positive electrode of the fourth current source serve together as the output current output terminal of the current detection circuit to output the output current; 所述第一NMOS管的源极、所述第一电流源的负极、所述第二电流源的负极、所述第三电流源的负极以及所述第四电流源的负极共接于电源地。The source of the first NMOS tube, the cathode of the first current source, the cathode of the second current source, the cathode of the third current source and the cathode of the fourth current source are connected to a power ground. 2.如权利要求1所述的电流检测电路，其特征在于，还包括第一开关、第二开关、第六场效应管以及第五电流源；2. The current detection circuit according to claim 1, further comprising a first switch, a second switch, a sixth field effect transistor and a fifth current source; 所述第一开关的第一端与所述第四场效应管的漏极和第一电流源的正极连接，所述第一开关的第二端与所述第二场效应管的源极和所述第二开关的第二端连接；A first end of the first switch is connected to the drain of the fourth field effect transistor and the positive electrode of the first current source, and a second end of the first switch is connected to the source of the second field effect transistor and the second end of the second switch; 所述第六场效应管的源极与所述第一电源连接，所述第六场效应管的漏极与所述第五电流源的正极和所述第二开关的第一端连接，所述第五电流源的负极与电源地连接。The source of the sixth field effect transistor is connected to the first power supply, the drain of the sixth field effect transistor is connected to the positive electrode of the fifth current source and the first end of the second switch, and the negative electrode of the fifth current source is connected to the power ground. 3.如权利要求2所述的电流检测电路，其特征在于，所述第五电流源的电流I5从以下计算公式得出：(I5+I2)RM6＝(I4+I3)RM5 3. The current detection circuit according to claim 2, characterized in that the current I5 of the fifth current source is obtained from the following calculation formula: ( I5 + I2 )R M6 =( I4 + I3 )R M5 其中，I2为所述第二电流源的电流，RM6为所述第六场效应管的等效导通电阻，I4为所述第四电流源的电流，I3为所述第三电流源的电流，RM5为所述第五场效应管的等效导通电阻。Among them, I2 is the current of the second current source, R M6 is the equivalent on-resistance of the sixth field effect transistor, I4 is the current of the fourth current source, I3 is the current of the third current source, and R M5 is the equivalent on-resistance of the fifth field effect transistor. 4.如权利要求2所述的电流检测电路，其特征在于，同一时刻，所述第一开关和所述第二开关中至多一个闭合。4 . The current detection circuit as claimed in claim 2 , wherein at most one of the first switch and the second switch is closed at the same time. 5.如权利要求2所述的电流检测电路，其特征在于，还包括第三开关；5. The current detection circuit according to claim 2, further comprising a third switch; 所述第三开关的第一端与所述第五场效应管的漏极连接，所述第三开关的第二端与所述第一场效应管的源极和所述第三场效应管的源极连接。A first end of the third switch is connected to the drain of the fifth field effect transistor, and a second end of the third switch is connected to the source of the first field effect transistor and the source of the third field effect transistor. 6.如权利要求1所述的电流检测电路，其特征在于，所述第四电流源I4的电流I4由以下计算公式得出：ImpRmp+(I1+I2)RM4＝IM5RM5 6. The current detection circuit according to claim 1, characterized in that the current I4 of the fourth current source I4 is obtained by the following calculation formula: I mp R mp +(I 1 +I 2 )R M4 =I M5 R M5 其中，IM5为所述第五场效应管M5的源漏电流，Rmp为所述第一PMOS管MP的等效导通电阻，I1为所述第一电流源的电流，I2为所述第二电流源的电流，RM4为所述第四场效应管的等效导通电阻，RM5为所述第五场效应管的等效导通电阻。Among them, I M5 is the source-drain current of the fifth field effect transistor M5, R mp is the equivalent on-resistance of the first PMOS transistor MP, I 1 is the current of the first current source, I 2 is the current of the second current source, R M4 is the equivalent on-resistance of the fourth field effect transistor, and R M5 is the equivalent on-resistance of the fifth field effect transistor. 7.如权利要求6所述的电流检测电路，其特征在于，所述输出电流Iout满足以下计算公式： 7. The current detection circuit according to claim 6, characterized in that the output current I out satisfies the following calculation formula: 其中，Rmp所述第一PMOS管的等效导通电阻，Imp为所述第一PMOS管的源漏电流。Among them, R mp is the equivalent on-resistance of the first PMOS tube, and I mp is the source-drain current of the first PMOS tube. 8.如权利要求1所述的电流检测电路，其特征在于，所述第一PMOS管为功率上管。8 . The current detection circuit according to claim 1 , wherein the first PMOS tube is a power upper tube. 9.一种电源芯片，其特征在于，所述电源芯片包括如权利要求1至8任意一项所述的电流检测电路。9. A power chip, characterized in that the power chip comprises the current detection circuit according to any one of claims 1 to 8. 10.一种电子设备，其特征在于，所述电子设备包括第一PMOS管、第一NMOS管、电感、电容、负载电阻以及如权利要求1至8任意一项所述的电流检测电路；10. An electronic device, characterized in that the electronic device comprises a first PMOS transistor, a first NMOS transistor, an inductor, a capacitor, a load resistor and a current detection circuit according to any one of claims 1 to 8; 所述第一PMOS管的漏极与所述第一NMOS管的漏极以及所述电感的第一端连接，所述电感的第二端与所述电容的正极和所述负载电阻的正极连接；The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the first end of the inductor, and the second end of the inductor is connected to the positive electrode of the capacitor and the positive electrode of the load resistor; 所述电容的负极以及所述负载电阻的负极共接于电源地。The negative electrode of the capacitor and the negative electrode of the load resistor are connected to the power ground.
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