CN118591280B - Capacitor and method for manufacturing the same - Google Patents
Capacitor and method for manufacturing the same Download PDFInfo
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- CN118591280B CN118591280B CN202411067578.9A CN202411067578A CN118591280B CN 118591280 B CN118591280 B CN 118591280B CN 202411067578 A CN202411067578 A CN 202411067578A CN 118591280 B CN118591280 B CN 118591280B
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Abstract
本发明提供了一种电容器及其制造方法，半导体衬底中形成有第一沟槽，第一介质层覆盖所述第一沟槽表面，第一导电层形成在所述第一介质层上并且所述第一导电层的表面呈凹凸状，第二介质层保形覆盖所述第一导电层，第二导电层形成在所述第二介质层上，由此，增加了所述半导体衬底上所述第一介质层和所述第二介质层的面积，相应的，提高了半导体衬底、第一介质层和第一导电层形成的第一电容器以及第一导电层、第二介质层和第二导电层形成的第二电容器的电容量。
The present invention provides a capacitor and a manufacturing method thereof. A first groove is formed in a semiconductor substrate, a first dielectric layer covers the surface of the first groove, a first conductive layer is formed on the first dielectric layer and the surface of the first conductive layer is concave-convex, a second dielectric layer conformally covers the first conductive layer, and the second conductive layer is formed on the second dielectric layer. Thus, the areas of the first dielectric layer and the second dielectric layer on the semiconductor substrate are increased, and accordingly, the capacitance of a first capacitor formed by the semiconductor substrate, the first dielectric layer and the first conductive layer and the capacitance of a second capacitor formed by the first conductive layer, the second dielectric layer and the second conductive layer are increased.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a capacitor and a manufacturing method thereof.
Background
The capacitor has wide application in integrated circuits and can play a plurality of roles of coupling, filtering, compensation and the like. And how to increase the capacitance of the capacitor is an innovative direction.
Disclosure of Invention
The invention aims to provide a capacitor and a manufacturing method thereof, so as to improve the capacitance of the capacitor.
In order to solve the above technical problem, the present invention provides a capacitor, including:
a semiconductor substrate having at least one first trench formed therein;
The first dielectric layer is positioned on the semiconductor substrate and covers the surface of the semiconductor substrate and the surface of the first groove;
The first conductive layer is positioned on the first dielectric layer, fills the first groove and protrudes out of the surface of the semiconductor substrate, and the surface of the first conductive layer is in an uneven shape;
a second dielectric layer on the first conductive layer, the second dielectric layer conformally covering the first conductive layer, and
And a second conductive layer positioned on the second dielectric layer.
Optionally, in the capacitor, a doped region is formed in the semiconductor substrate, the first dielectric layer exposes at least a portion of the doped region, and the second dielectric layer exposes a portion of the first conductive layer.
Optionally, in the capacitor, the capacitor further comprises a first plug connected with the doped region, a second plug connected with the first conductive layer, and a third plug connected with the second conductive layer.
Optionally, in the capacitor, at least one second trench is further formed in the semiconductor substrate, and the second trench is filled with the first isolation structure.
Optionally, in the capacitor, a depth of the second trench is the same as a depth of the first trench.
Optionally, in the capacitor, at least one third trench is further formed in the semiconductor substrate, and the second isolation structure is filled in the third trench.
Optionally, in the capacitor, the semiconductor substrate comprises a first region, a second region and a third region, the first trench is located in the first region, the second trench is located in the second region, the third trench is located in the third region, the first dielectric layer covers the semiconductor substrate of the first region, the second region and the third region, the first conductive layer covers the first dielectric layer of the first region and the second region, the second dielectric layer covers the first conductive layer, and the second conductive layer covers the second dielectric layer and the first dielectric layer.
The invention also provides a manufacturing method of the capacitor, which comprises the following steps:
Providing a semiconductor substrate;
Forming at least one first trench in the semiconductor substrate;
Forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer covers the surface of the semiconductor substrate and the surface of the first groove;
forming a first conductive layer on the first dielectric layer, wherein the first conductive layer fills the first groove and protrudes out of the surface of the semiconductor substrate, and the surface of the first conductive layer is in an uneven shape;
Forming a second dielectric layer on the first conductive layer, the second dielectric layer conformally covering the first conductive layer, and
And forming a second conductive layer on the second dielectric layer.
Optionally, in the method for manufacturing a capacitor, before forming the first dielectric layer on the semiconductor substrate, the method for manufacturing a capacitor further includes:
at least one second trench and at least one third trench are formed in the semiconductor substrate.
Optionally, in the method for manufacturing a capacitor, before forming the first dielectric layer on the semiconductor substrate, the method for manufacturing a capacitor further includes:
filling dielectric material in the first trench, the second trench and the third trench, and
And removing the dielectric material in the first groove.
In the capacitor and the manufacturing method thereof provided by the invention, the first groove is formed in the semiconductor substrate, the first dielectric layer covers the surface of the first groove, the first conductive layer is formed on the first dielectric layer, the surface of the first conductive layer is in an uneven shape, the second dielectric layer is conformally covered on the first conductive layer, and the second conductive layer is formed on the second dielectric layer, so that the areas of the first dielectric layer and the second dielectric layer on the semiconductor substrate are increased, and accordingly, the capacitance of the first capacitor formed by the semiconductor substrate, the first dielectric layer and the first conductive layer and the capacitance of the second capacitor formed by the first conductive layer, the second dielectric layer and the second conductive layer are increased.
Drawings
Fig. 1 is a schematic cross-sectional view of a capacitor according to an embodiment of the present invention.
Fig. 2 is a schematic top view of a capacitor according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a device formed after forming a first trench, a second trench, and a third trench and filling a dielectric material in a method of manufacturing a capacitor according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a device formed after exposing a first trench in a method of manufacturing a capacitor according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a device formed after forming a first dielectric layer and a first conductive layer in a method of manufacturing a capacitor according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a device formed after forming a second dielectric layer in a method of manufacturing a capacitor according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a device formed after forming a second conductive layer in a method of manufacturing a capacitor according to an embodiment of the present invention.
Wherein reference numerals are as follows:
100-semiconductor substrate, 101-first region, 102-second region, 103-third region, 110-first trench, 110-first fill structure, 112-second trench, 112A-second fill structure, 114-third trench, 114A-third fill structure, 120-first dielectric layer, 130-first conductive layer, 140-second dielectric layer, 150-second conductive layer, 160-doped region, 170-first plug, 180-second plug, 190-third plug, 200-first isolation structure, 210-second isolation structure.
Detailed Description
The capacitor and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise in the present document, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper/upper," "lower/lower," and the like are used for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
Fig. 1 and 2 are schematic cross-sectional views and schematic top views of a capacitor according to an embodiment of the application. As shown in fig. 1 and 2, in the embodiment of the application, the capacitor comprises a semiconductor substrate 100, a first dielectric layer 120 located on the semiconductor substrate 100 and covering the surface of the semiconductor substrate 100 and the surface of the first trench 110, a first conductive layer 130 located on the first dielectric layer 120, the first conductive layer 130 filling the first trench 110 and protruding from the surface of the semiconductor substrate 100, the surface of the first conductive layer 130 being in a concave-convex shape, a second dielectric layer 140 located on the first conductive layer 130, the second dielectric layer 140 conformally covering the first conductive layer 130, and a second conductive layer 150 located on the second dielectric layer 140.
The materials of the first conductive layer 130 and the second conductive layer 150 may be monocrystalline silicon, polycrystalline silicon, or metal, and further, the materials of the first conductive layer 130 and the second conductive layer 150 may be the same or different. In one embodiment of the present application, the materials of the first conductive layer 130 and the second conductive layer 150 are polysilicon.
In the embodiment of the present application, at least one first trench 110 is formed in the semiconductor substrate 100, and the first dielectric layer 120 covers the surface of the first trench 110, so that the area of the first dielectric layer 120 on the semiconductor substrate 100 is increased by the first trench 110, thereby increasing the capacitance of the capacitor formed by the semiconductor substrate 100, the first dielectric layer 120 and the first conductive layer 130.
Meanwhile, in the embodiment of the present application, the surface of the first conductive layer 130 is in an uneven shape, and the second dielectric layer 140 conformally covers the first conductive layer 130, that is, the surface of the second dielectric layer 140 is also in an uneven shape, so that the area of the second dielectric layer 140 on the semiconductor substrate 100 is correspondingly increased, thereby improving the capacitance of the capacitor formed by the first conductive layer 130, the second dielectric layer 140 and the second conductive layer 150.
In the embodiment of the present application, since the first trench 110 is formed in the semiconductor substrate 100, that is, the surface of the semiconductor substrate 100 is in an uneven shape, the surface of the first conductive layer 130 is in an uneven shape only by a conventional deposition process, and the process is simple.
With continued reference to fig. 1 and 2, in an embodiment of the present application, a doped region 160 is formed in the semiconductor substrate 100, and the electrical connection performance may be improved by the doped region 160, and in other embodiments of the present application, the doped region 160 may not be provided. The first dielectric layer 120 exposes at least a portion of the doped region 160, and the second dielectric layer 140 exposes a portion of the first conductive layer 130. Further, the capacitor further includes a first plug 170 connected to the doped region 160, a second plug 180 connected to the first conductive layer 130, and a third plug 190 connected to the second conductive layer 150. In other embodiments of the present application, the first plug 170 may not be provided accordingly.
Specifically, a first window (not shown) may be formed in the first dielectric layer 120, where the first window exposes the doped region 160, and the first window penetrates the first dielectric layer 120 and the first conductive layer 130, the second dielectric layer 140, and the second conductive layer 150 on the first dielectric layer 120. A second window (not shown) may be formed in the second dielectric layer 140, where the second window exposes the first conductive layer 130, and the second window penetrates the second dielectric layer 140 and the second conductive layer 150 on the second dielectric layer 140.
Further, a third dielectric layer (not shown) may be formed, and the third dielectric layer covers the second conductive layer 150. The first to third dielectric layers and other layer structures may be single-layer film structures or multilayer film structures, for example, the third dielectric layer may include a silicon oxide layer, and for example, the third dielectric layer may include a stacked silicon oxide layer and silicon nitride layer. In the embodiment of the present application, the first window and the second window both penetrate through the third dielectric layer, so as to expose the doped region 160 and the first conductive layer 130. Further, a third window (not shown) may be formed through the third dielectric layer, where the third window exposes the second conductive layer 150. Wherein the first plug 170 is formed in the first window, the second plug 180 is formed in the second window, and the third plug 190 is formed in the third window.
Referring to fig. 3 to 7 in combination, further, at least one second trench 112 is formed in the semiconductor substrate 100, and the second trench 112 is filled with the first isolation structure 200. In an embodiment of the present application, the first isolation structure 200 may be used as a shallow trench isolation structure between a plurality of memory cells.
Wherein the depth of the second trench 112 is the same as the depth of the first trench 110. It should be noted that, a certain depth difference may exist between the first trench 110 and the second trench 112 due to a process error, and at this time, the second trench 112 may be slightly deeper than the first trench 110, or the first trench 110 may be slightly deeper than the second trench 112.
Further, at least one third trench 114 is further formed in the semiconductor substrate 100, and the second isolation structure 210 is filled in the third trench 114, and the third trench 114 is deeper than the second trench 112. In an embodiment of the present application, the second isolation structure 210 may be a shallow trench isolation structure between a plurality of transistors.
Correspondingly, the embodiment of the application also provides a manufacturing method of the capacitor, specifically please refer to fig. 3 to 7, and please refer to fig. 1 and 2 in combination. The manufacturing method of the capacitor comprises the following steps:
Step S10, providing a semiconductor substrate;
step S20, forming at least one first groove in the semiconductor substrate;
Step S30, forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer covers the surface of the semiconductor substrate and the surface of the first groove;
Step S40, forming a first conductive layer on the first dielectric layer, wherein the first conductive layer fills the first groove and protrudes out of the surface of the semiconductor substrate, and the surface of the first conductive layer is in an uneven shape;
Step S50, forming a second dielectric layer on the first conductive layer, wherein the second dielectric layer conformally covers the first conductive layer, and
And S60, forming a second conductive layer on the second dielectric layer.
The semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, or the like. As shown in fig. 3, in the embodiment of the present application, the semiconductor substrate 100 includes a first region 101, a second region 102, and a third region 103, where the first region 101, the second region 102, and the third region 103 may be used to form different device structures. For example, the first region 101 may be used to form a capacitor, the second region 102 may be used to form a memory cell, the third region 103 may be used to form a transistor or a control unit of transistors, etc.
Reference may be made in conjunction with fig. 1, wherein a doped region 160 is formed in said semiconductor substrate 100 of the first region 101. Further, doped regions may also be formed in the second region 102 and the third region 103 to achieve adjustment of conductivity properties.
With continued reference to fig. 3, in an embodiment of the present application, at least one first trench 110 and at least one second trench 112 and at least one third trench 114 are formed in the semiconductor substrate 100. In other embodiments of the present application, the first trench 110, the second trench 112, and the third trench 114 may be formed separately, for example, the first trench 110 is formed first, and then the second trench 112 and/or the third trench 114 are formed, which is not limited in this application. As illustrated in fig. 3, two first trenches 110 are schematically shown formed in the first region 101, two second trenches 112 are formed in the second region 102, and two third trenches 114 are formed in the third region 103.
Next, dielectric materials are filled in the first trench 110, the second trench 112, and the third trench 114 to form a first filling structure 110A, a second filling structure 112A, and a third filling structure 114A, respectively, where the first filling structure 110A, the second filling structure 112A, and the third filling structure 114A protrude from the surface of the semiconductor substrate 100.
As shown in fig. 4, the first filling structure 110A is removed, and the first trench 110 is exposed. Specifically, the first filling structure 110A may be removed by an etching process, for example, the first filling structure 110A may be removed by a wet etching process.
In an embodiment of the present application, as shown in fig. 5, a first dielectric layer 120 is formed, and the first dielectric layer 120 covers the semiconductor substrate 100 and the first trench 110. Here, the first dielectric layer 120 covers the semiconductor substrate 100 of the first region 101, the second region 102 and the third region 103. The first dielectric layer 120 is, for example, a tunnel oxide layer, which may be formed by a thermal oxidation process. The first dielectric layer 120 may be formed with a first window in the first region 101 to expose the doped region 160.
Next, a first conductive layer 130 is formed on the first dielectric layer 120, where the first conductive layer 130 fills the first trench 110 and protrudes from the surface of the semiconductor substrate 100, and the surface of the first conductive layer 130 is in an uneven shape.
Specifically, the first conductive layer 130 may be formed through a deposition process. Due to the presence of the first trench 110, the surface of the semiconductor substrate 100 is made uneven, and in the embodiment of the present application, most importantly, the surface of the semiconductor substrate 100 in the first region 101 is made uneven, so that the surface of the first conductive layer 130 in the first region 101 is made uneven only by a conventional deposition process.
Next, as shown in fig. 6, a second dielectric layer 140 is formed on the first conductive layer 130, and the second dielectric layer 140 conformally covers the first conductive layer 130, that is, the surface of the second dielectric layer 140 of the first region 101 is also concave-convex. Wherein, the second dielectric layer 140 may be formed with a second window in the first region 101 to expose the first conductive layer 130.
In an embodiment of the present application, before forming the second dielectric layer 140, a portion of the second filling structure 112A protruding from the surface of the semiconductor substrate 100 may be at least partially removed, so as to form the first isolation structure 200. Specifically, the portion of the second filling structure 112A protruding from the surface of the semiconductor substrate 100 may be at least partially removed by an etching process.
Next, as shown in fig. 7, a second conductive layer 150 is formed on the second dielectric layer 140. Wherein, after the second conductive layer 150 is formed, an etching/polishing process may be performed on the second conductive layer 150 to adjust the surface flatness of the second conductive layer 150.
In an embodiment of the present application, before forming the second conductive layer 150, a portion of the third filling structure 114A protruding from the surface of the semiconductor substrate 100 may be at least partially removed to form the second isolation structure 210. Further, the first conductive layer 130 on the third region 103 is also removed, so that different transistor structures can be formed in the second region 102 and the third region 103. The transistor structure formed may include a first dielectric layer 120, a first conductive layer 130 (acting as a floating gate), a second dielectric layer 140, and a second conductive layer 150 (acting as a control gate) on the second region 102, and a first dielectric layer 120 (acting as a gate dielectric layer) and a second conductive layer 150 (acting as a gate conductive layer) on the third region 103.
Here, a capacitor is formed in the first region 101, wherein the capacitor may be as described above with reference to fig. 1, 2 and 7 in combination.
In this embodiment of the present application, a third dielectric layer may be further formed, and the third dielectric layer covers the second conductive layer 150, where the third dielectric layer may be a single-layer film structure or a stacked structure of multiple layers of films. In the embodiment of the present application, the first window and the second window both penetrate through the third dielectric layer, so as to expose the doped region 160 and the first conductive layer 130. Further, a third window (not shown) may be formed through the third dielectric layer, where the third window exposes the second conductive layer 150. Wherein the first plug 170 is formed in the first window, the second plug 180 is formed in the second window, and the third plug 190 is formed in the third window. Wherein the first plug 170 and the third plug 190 may be grounded, and the second plug 180 may be high.
In summary, in the capacitor and the method for manufacturing the same provided by the present invention, the first trench 110 is formed in the semiconductor substrate 100, the first dielectric layer 120 covers the surface of the first trench 110, the first conductive layer 130 is formed on the first dielectric layer 120, the surface of the first conductive layer 130 is in an uneven shape, the second dielectric layer 140 conformally covers the first conductive layer 130, and the second conductive layer 150 is formed on the second dielectric layer 140, thereby increasing the areas of the first dielectric layer 120 and the second dielectric layer 140 on the semiconductor substrate 100, and correspondingly increasing the capacitance of the first capacitor formed by the semiconductor substrate 100, the first dielectric layer 120 and the first conductive layer 130, and the second capacitor formed by the first conductive layer 130, the second dielectric layer 140 and the second conductive layer 150.
Reference throughout this specification to "one embodiment," "some embodiments," or "a" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, at least some embodiments, of the present application. Thus, the appearances of the phrases "in one embodiment," "in some embodiments," or "in various places of the application" are not necessarily referring to the same embodiment or embodiments. Furthermore, the features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments.
While certain specific embodiments of the application have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the application. The embodiments of the present application may be combined arbitrarily without departing from the spirit and scope of the present application. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the application. The scope of the application is defined by the appended claims.
Claims (9)
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| CN117995826A (en) * | 2022-10-28 | 2024-05-07 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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