CN118590035B - Duty cycle correction circuit - Google Patents

Abstract

The application belongs to the technical field of signal calibration, and particularly relates to a duty ratio correction circuit, which comprises a plurality of cascade duty ratio adjustment modules, wherein each duty ratio adjustment module comprises an edge adjustment unit, a waveform shaping unit and a phase adjustment unit, the edge adjustment unit adjusts rising edge time or falling edge time of a clock signal input end signal according to a feedback signal input end signal to generate a clock signal output end signal, the waveform shaping unit is connected with clock signal output ends of two edge adjustment units and is used for shortening the rising edge time and the falling edge time of the clock signal output end signal, and the phase adjustment unit is connected between the edge adjustment unit and the waveform shaping unit or connected with two output ends of the waveform shaping unit. The phase adjusting unit is used for adjusting the output phase of the single duty ratio adjusting module, increasing the common mode gain of the plurality of cascaded duty ratio adjusting modules, and improving the transmission efficiency of common mode signals and the precision and accuracy of signal transmission.

Description

Duty Cycle Correction Circuit

Technical Field

The present application belongs to the technical field of signal calibration, and in particular relates to a duty cycle correction circuit.

Background Art

With the advancement of integrated circuit manufacturing technology, the upper limit frequency of integrated circuit operation has also increased, which requires the frequency range of circuit system operation to be wider. In a circuit system with a wide frequency range, in order to ensure the accuracy of signal transmission, the duty cycle of the clock signal needs to be calibrated to 50% during sampling. However, since the circuit system is easily affected by the process, voltage and temperature, the duty cycle is easily distorted during the signal transmission process, causing the duty cycle of the clock signal to seriously deviate from 50% during sampling, which in turn causes signal transmission errors.

In order to solve the signal transmission error caused by duty cycle distortion, the prior art uses a duty cycle correction circuit to correct the distorted clock signal. In some technical solutions, the duty cycle correction circuit includes a detection unit, a judgment unit and a duty cycle adjustment unit, the detection unit is used to detect whether the duty cycle of the clock signal is distorted, the judgment unit judges the degree of duty cycle distortion, and the duty cycle adjustment unit is used to adjust the duty cycle.

Since the adjustment range of a single duty cycle adjustment unit is limited, the duty cycle correction circuit requires multiple duty cycle adjustment units to be cascaded. However, after the multiple duty cycle adjustment units are cascaded, the common mode gain decreases significantly, affecting the precision and accuracy of signal transmission.

Summary of the invention

The purpose of the present application is to provide a duty cycle correction circuit to solve the problem of common mode gain reduction.

In order to achieve the above object, the present application provides a duty cycle correction circuit, including a plurality of cascaded duty cycle adjustment modules, wherein the duty cycle adjustment module includes:

An edge adjustment unit, comprising a clock signal input terminal, a feedback signal input terminal and a clock signal output terminal, wherein the edge adjustment unit adjusts the rising edge time or the falling edge time of the signal at the clock signal input terminal according to the signal at the feedback signal input terminal to generate a signal at the clock signal output terminal;

A waveform shaping unit, connected to the clock signal output ends of the two edge adjustment units, and used to shorten the rising edge time and falling edge time of the signal at the clock signal output ends;

A phase adjustment unit is connected between the edge adjustment unit and the waveform shaping unit or connected to the two output ends of the waveform shaping unit, and is at least used to adjust the phase of the common mode signal output by the edge adjustment unit or the phase of the common mode signal output by the edge adjustment unit and the waveform shaping unit, thereby increasing the common mode gain of multiple cascaded duty cycle adjustment modules.

Optionally, the edge adjustment unit includes a first adjustment unit and a second adjustment unit, the input end of the first adjustment unit and the input end of the second adjustment unit are the clock signal input end, the output end of the first adjustment unit and the output end of the second adjustment unit are the clock signal output end, the control end of the first adjustment unit is the feedback signal input end, and the first adjustment unit adjusts the signal of the clock signal input end according to the signal of the feedback signal input end and outputs it to the clock signal output end.

Optionally, the first adjustment unit includes a first transistor, a second transistor and a first inverter, the second adjustment unit includes a second inverter, the first transistor is a P-channel field effect transistor, the second transistor is an N-channel field effect transistor, the control end of the first transistor and the control end of the second transistor are the control ends of the first adjustment unit, the first end of the first transistor is connected to a first power supply, the second end of the first transistor is connected to a first power supply end of the first inverter, the first end of the second transistor is connected to a second power supply end, the second end of the second transistor is connected to a second power supply end of the first inverter, the input end of the first inverter is the input end of the first adjustment unit, the output end of the first inverter is the output end of the first adjustment unit, the first power supply end of the second inverter is connected to the first power supply, the second power supply end of the second inverter is connected to the second power supply, and the input end and output end of the second inverter are the input end and output end of the second adjustment unit respectively.

Optionally, the first inverter includes a third transistor and a fourth transistor, the third transistor is a P-channel field effect transistor, the fourth transistor is an N-channel field effect transistor, the control end of the third transistor and the control end of the fourth transistor are input ends of the first inverter, the first end of the third transistor is connected to the first transistor, the second end of the third transistor and the second end of the fourth transistor are output ends of the first inverter, and the first end of the fourth transistor is connected to the second transistor;

The second inverter includes a fifth transistor and a sixth transistor, the fifth transistor is a P-channel field effect transistor, the sixth transistor is an N-channel field effect transistor, the control end of the fifth transistor and the control end of the sixth transistor are input ends of the second inverter, the first end of the fifth transistor is connected to the first power supply end, the second end of the fifth transistor and the second end of the sixth transistor are output ends of the second inverter, and the first end of the sixth transistor is the second power supply end.

Optionally, the waveform shaping unit includes a first buffer, a second buffer, a first latch and a second latch, the first buffer and the second buffer include an inverting buffer, the input end of the first buffer is the first input end of the waveform shaping unit, the input end of the second buffer is the second input end of the waveform shaping unit, the first buffer is connected to the second output end of the waveform shaping unit through a first node and a second node in sequence, the second buffer is connected to the second output end of the waveform shaping unit through a third node and a fourth node in sequence, the input end and the output end of the first latch are connected to the third node and the first node respectively, and the input end and the output end of the second latch are connected to the fourth node and the second node respectively.

Optionally, the phase adjustment unit includes a first signal amplifier and a second signal amplifier, and the first signal amplifier and the second signal amplifier are used to shift the phase of the common-mode signal output by the edge adjustment unit and the waveform shaping unit of the duty cycle adjustment module of the previous stage by 180°, so as to be in phase with the common-mode signal of the duty cycle adjustment module of the current stage, and the two common-mode signals are summed in phase at the edge adjustment unit of the duty cycle adjustment module of the current stage, the input end of the first signal amplifier is connected to the first output end of the waveform shaping unit, and the input end of the second signal amplifier is connected to the second output end of the waveform shaping unit.

Optionally, the first signal amplifier and the second signal amplifier include inverting buffers or push-pull common-source amplifiers.

Optionally, the phase adjustment unit includes a first signal amplifier and a second signal amplifier, and the first signal amplifier and the second signal amplifier are used to shift the phase of the common-mode signal output by the edge adjustment unit of the duty cycle adjustment module of the previous stage by 180°, and to be in phase with the common-mode signal of the duty cycle adjustment module of the current stage, and the two common-mode signals are summed in phase at the edge adjustment unit of the duty cycle adjustment module of the current stage, and the two edge adjustment units include a first edge adjustment unit and a second edge adjustment unit, and the input end of the first signal amplifier is connected to the output end of the first edge adjustment unit and the first input end of the waveform shaping unit, and the input end of the second signal amplifier is connected to the output end of the second edge adjustment unit and the second input end of the waveform shaping unit.

Optionally, the first signal amplifier and the second signal amplifier include inverting buffers or push-pull common-source amplifiers.

Optionally, the duty cycle correction circuit also includes a detection module and a judgment module, the detection module is used to detect whether the duty cycle of the clock signal is distorted, the judgment module connects the detection module and the first-stage duty cycle adjustment module, and the judgment module outputs a feedback signal reflecting the degree of duty cycle distortion to the feedback signal input terminal.

The duty cycle correction circuit disclosed in the present application has the following beneficial effects:

In the present application, the duty cycle correction circuit includes a plurality of cascaded duty cycle adjustment modules, the duty cycle adjustment module includes an edge adjustment unit, a waveform shaping unit and a phase adjustment unit, the edge adjustment unit adjusts the rising edge time or falling edge time of the clock signal at the clock signal input end according to the feedback signal at the feedback signal input end, and generates a signal at the clock signal output end, the waveform shaping unit is connected to the clock signal output ends of the two edge adjustment units, and is used to shorten the rising edge time and falling edge time of the signal at the clock signal output end, and the phase adjustment unit is connected between the edge adjustment unit and the waveform shaping unit or connects the two output ends of the waveform shaping unit. The phase adjustment unit adjusts the phase of the common mode signal output by the edge adjustment unit and the waveform shaping unit, thereby increasing the common mode gain of the plurality of cascaded duty cycle adjustment modules, and improving the transmission efficiency of the common mode signal and the precision and accuracy of the signal transmission.

Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of the structure of a duty cycle correction circuit in an embodiment of the present application.

FIG. 2 is a schematic diagram of the structure of a duty cycle adjustment module in an embodiment of the present application.

FIG. 3 is a schematic diagram of the structure of an edge adjustment unit in an embodiment of the present application.

FIG. 4 is a schematic diagram of the structure of a waveform shaping unit in an embodiment of the present application.

FIG. 5 is a schematic diagram showing that the phase adjustment unit is located after the waveform shaping unit in an embodiment of the present application.

FIG. 6 is a schematic diagram showing that a phase adjustment unit is located before a waveform shaping unit in an embodiment of the present application.

Description of reference numerals:

10. Duty cycle adjustment module;

100, edge adjustment unit; 100a, first edge adjustment unit; 100b, second edge adjustment unit; 110, first adjustment unit; 111, first transistor; 112, second transistor; 113, third transistor; 114, fourth transistor; 120, second adjustment unit; 121, fifth transistor; 122, sixth transistor;

200, waveform shaping unit; 210, first buffer; 220, second buffer; 230, first latch; 240, second latch;

300, phase adjustment unit; 310, first signal amplifier; 320, second signal amplifier.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

1 and 2 , the duty cycle correction circuit in this embodiment includes a plurality of cascaded duty cycle adjustment modules 10 , and the duty cycle adjustment module 10 includes an edge adjustment unit 100 , a waveform shaping unit 200 and a phase adjustment unit 300 .

The edge adjustment unit 100 includes a clock signal input terminal, a feedback signal input terminal and a clock signal output terminal. The edge adjustment unit 100 adjusts the rising edge time or the falling edge time of the clock signal at the clock signal input terminal according to the feedback signal at the feedback signal input terminal, and generates a signal at the clock signal output terminal. The duty cycle adjustment module 10 includes two edge adjustment units 100, namely a first edge adjustment unit 100a and a second edge adjustment unit 100b.

The waveform shaping unit 200 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of the waveform shaping unit 200 are connected to the clock signal output terminals of the first edge adjustment unit 100a and the second edge adjustment unit 100b in a one-to-one correspondence. The waveform shaping unit 200 is used to shorten the rising edge time and the falling edge time of the signal at the clock signal output terminal, and shape the rising edge and the falling edge of the clock signal into sharp edges, that is, adjust the lengths of the high and low levels, thereby achieving the purpose of adjusting the duty cycle.

The phase adjustment unit 300 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of the phase adjustment unit 300 are connected to the first output terminal and the second output terminal of the waveform shaping unit 200 in a one-to-one correspondence. The first output terminal and the second output terminal of the phase adjustment unit 300 are two output terminals of the duty cycle adjustment module 10. In other words, the phase adjustment unit 300 is connected to the two output terminals of the waveform shaping unit 200. The phase adjustment unit 300 is used to adjust the phase of the common mode signal output by the edge adjustment unit 100 and the waveform shaping unit 200, thereby increasing the common mode gain and differential mode gain of multiple cascaded duty cycle adjustment modules 10.

The clock signal of the input duty cycle adjustment module 10 includes a differential input first input clock signal clk.inp and a second input clock signal clk.inm, the first input clock signal clk.inp is input from the clock signal input end of the first edge adjustment unit 100a, and the second input clock signal clk.inm is input from the clock signal input end of the second edge adjustment unit 100b. The feedback signal includes a first feedback signal Vdcc.m and a second feedback signal Vdcc.p, and the two edge adjustment units 100 adjust the rising edge time or the falling edge time of the first input clock signal clk.inp and the second input clock signal clk.inm according to the first feedback signal Vdcc.m and the second feedback signal Vdcc.p respectively, to generate a first intermediate clock signal clk.tsm and a second intermediate clock signal clk.tsp, and the first intermediate clock signal clk.tsm and the second intermediate clock signal clk.tsp are then shaped by the waveform shaping unit 200 to generate a first output clock signal clk.outp and a second output clock signal clk.outm.

It should be noted that the phase adjustment unit 300 can be connected to the two output ends of the waveform shaping unit 200, but is not limited thereto. The phase adjustment unit 300 can also be connected between the edge adjustment unit 100 and the waveform shaping unit 200, depending on the specific situation. That is, the first input end and the second input end of the phase adjustment unit 300 are connected to the clock signal output ends of the first edge adjustment unit 100a and the second edge adjustment unit 100b in a one-to-one correspondence, and the first output end and the second output end of the phase adjustment unit 300 are connected to the first input end and the second input end of the waveform shaping unit 200 in a one-to-one correspondence. The first output end and the second output end of the waveform shaping unit 200 are the two output ends of the duty cycle adjustment module 10.

Since the adjustment range of a single edge adjustment unit 100 is limited, the duty cycle correction circuit requires a cascade of multiple edge adjustment units 100. When the duty cycle adjustment module 10 is an edge adjustment unit 100 and a waveform shaping unit 200, the common mode signal at the output end of the edge adjustment unit 100 of the previous stage is opposite in phase to the common mode input signal of the current stage, resulting in a significant decrease in the common mode gain, a decrease in the transmission efficiency of the common mode signal, and affecting the precision and accuracy of signal transmission.

In this embodiment, the duty cycle correction circuit includes a plurality of cascaded duty cycle adjustment modules 10, the duty cycle adjustment module 10 includes an edge adjustment unit 100, a waveform shaping unit 200 and a phase adjustment unit 300, the edge adjustment unit 100 adjusts the rising edge time or falling edge time of the clock signal at the clock signal input end according to the feedback signal at the feedback signal input end, and generates a signal at the clock signal output end, the waveform shaping unit 200 is connected to the clock signal output ends of the two edge adjustment units 100, and is used to shorten the rising edge time and falling edge time of the signal at the clock signal output end, and the phase adjustment unit 300 is connected between the edge adjustment unit 100 and the waveform shaping unit 200 or connected to the two output ends of the waveform shaping unit 200. The phase adjustment unit 300 adjusts the phase of the common mode signal output by the edge adjustment unit 100 and the waveform shaping unit 200, thereby increasing the common mode gain of the plurality of cascaded duty cycle adjustment modules 10, and improving the transmission efficiency of the common mode signal and the precision and accuracy of the signal transmission.

2 and 3, the edge adjustment unit 100 in this embodiment includes a first adjustment unit 110 and a second adjustment unit 120. The input end of the first adjustment unit 110 and the input end of the second adjustment unit 120 are clock signal input ends, and the output end of the first adjustment unit 110 and the output end of the second adjustment unit 120 are clock signal output ends. The control end of the first adjustment unit 110 is a feedback signal input end. The first adjustment unit 110 adjusts the signal at the clock signal input end according to the signal at the feedback signal input end and outputs it to the clock signal output end.

The edge adjustment unit 100 is composed of a first adjustment unit 110 and a second adjustment unit 120. The first adjustment unit 110 and the second adjustment unit 120 are connected in parallel to ensure that the circuit can still pass the input clock signal when the feedback loop fails in extreme cases, thereby ensuring the stability of the clock path circuit.

In some embodiments, the first adjustment unit 110 includes a first transistor 111, a second transistor 112 and a first inverter, and the second adjustment unit 120 includes a second inverter. The first transistor 111 is a P-channel field effect transistor, and the second transistor 112 is an N-channel field effect transistor. The control end of the first transistor 111 and the control end of the second transistor 112 are the control ends of the first adjustment unit 110, the first end of the first transistor 111 is connected to the first power supply Vcc, the second end of the first transistor 111 is connected to the first power supply end of the first inverter, the first end of the second transistor 112 is connected to the second power supply, the second power supply includes a ground terminal GND, and the second end of the second transistor 112 is connected to the second power supply end of the first inverter.

The input end of the first inverter is the input end of the first adjustment unit 110, and the output end of the first inverter is the output end of the first adjustment unit 110. The first power supply end of the second inverter is connected to the first power supply Vcc, the second power supply end of the second inverter is connected to the second power supply, and the input end and output end of the second inverter are the input end and output end of the second adjustment unit 120 respectively.

The first adjustment unit 110 includes a first transistor 111, a second transistor 112 and a first inverter, and the second adjustment unit 120 includes a second inverter. The first adjustment unit 110 and the second adjustment unit 120 have simple structures, and the cascade connection of multiple edge adjustment units 100 is easy to implement.

In some embodiments, the first inverter includes a third transistor 113 and a fourth transistor 114, the third transistor 113 is a P-channel field effect transistor, and the fourth transistor 114 is an N-channel field effect transistor. The control end of the third transistor 113 and the control end of the fourth transistor 114 are the input end of the first inverter, the first end of the third transistor 113 is connected to the second end of the first transistor 111, the second end of the third transistor 113 and the second end of the fourth transistor 114 are the output end of the first inverter, and the first end of the fourth transistor 114 is connected to the second end of the second transistor 112.

The second inverter includes a fifth transistor 121 and a sixth transistor 122, wherein the fifth transistor 121 is a P-channel field effect transistor, and the sixth transistor 122 is an N-channel field effect transistor. The control end of the fifth transistor 121 and the control end of the sixth transistor 122 are input ends of the second inverter, the first end of the fifth transistor 121 is a first power supply end, connected to the first power supply Vcc, the second end of the fifth transistor 121 and the second end of the sixth transistor 122 are output ends of the second inverter, and the first end of the sixth transistor 122 is a second power supply end, connected to the ground end GND.

The control terminal, the first terminal, and the second terminal of the first transistor 111 , the second transistor 112 , the third transistor 113 , the fourth transistor 114 , the fifth transistor 121 , and the sixth transistor 122 may be the gate, the source, and the drain thereof, respectively.

If the input signal of the edge adjustment unit 100 is Vin, the output signal is Vout, and the feedback signal is Vdcc, then the relationship between the output signal Vout and the input signal Vin is as follows:

Wherein, gm1 is the transconductance of the first transistor 111, gm3 is the transconductance of the third transistor 113, gm5 is the transconductance of the fifth transistor 121, gds1 is the output admittance of the first transistor 111, and gds5 is the output admittance of the fifth transistor 121. The transconductance and output transconductance of the second transistor 112 are the same as the transconductance and output transconductance of the first transistor 111, the transconductance and output transconductance of the fourth transistor 114 are the same as the transconductance and output transconductance of the third transistor 113, and the transconductance and output transconductance of the sixth transistor 122 are the same as the transconductance and output transconductance of the fifth transistor 121.

It can be seen from Formula 1 that for the input signal Vin and the feedback signal Vdcc, the gain of the edge adjustment unit 100 is almost at the same order of magnitude. The common-mode signal at the output end of the edge adjustment unit 100 of the previous stage is inverted and summed at the edge adjustment unit 100 of the current stage, which will cause the common-mode gain to decrease significantly.

As shown in FIG. 2 and FIG. 4 , the waveform shaping unit 200 includes two buffers and two latches, specifically including a first buffer 210, a second buffer 220, a first latch 230, and a second latch 240. The first buffer 210 and the second buffer 220 include inverting buffers. The input end of the first buffer 210 is the first input end of the waveform shaping unit 200, and the input end of the second buffer 220 is the second input end of the waveform shaping unit 200. The first buffer 210 is connected to the first output end of the waveform shaping unit 200 through the first node A and the second node B in sequence, and the second buffer 220 is connected to the second output end of the waveform shaping unit 200 through the third node C and the fourth node D in sequence. The input end and the output end of the first latch 230 are connected to the first node A and the third node C, respectively, and the input end and the output end of the second latch 240 are connected to the fourth node D and the second node B, respectively.

If the first input terminal signal of the waveform shaping unit 200 is Vinp, the second input terminal signal of the waveform shaping unit 200 is Vinm, the first output terminal signal of the waveform shaping unit 200 is Voutm, and the second output terminal signal of the waveform shaping unit 200 is Voutp, the relationship between the input signal and the output signal of the waveform shaping unit 200 is the following formulas 2 and 3:

Among them, gm_buffer1 is the transconductance of the first buffer 210, gm_latch3 is the transconductance of the first latch 230, gds_buffer1 is the output admittance of the first buffer 210, and gds_latch3 is the output admittance of the first latch 230. The transconductance and output admittance of the second buffer 220 are the same as those of the first buffer 210, and the transconductance and output admittance of the second latch 240 are the same as those of the first latch 230.

According to Formula 1 and Formula 2, the common-mode transfer function of the output terminal of the waveform shaping unit 200 to the feedback signal Vdcc is as follows:

If the phase adjustment unit 300 is not used to adjust the phase of the common mode signal, the common mode signal at the output end of the edge adjustment unit 100 of the second-stage duty cycle adjustment module 10 is expressed by the following formula 5:

Transforming formula 5, we can get the following formula 6:

It can be seen from Equations 5 and 6 that if the phase of the common-mode signal is not adjusted with the help of the phase adjustment unit 300, the common-mode signal of the previous stage and the input common-mode signal of the edge adjustment unit 100 of the duty cycle adjustment module 10 of the current stage will be in opposite phase, and will be summed in reverse phase at the edge adjustment unit 100 of the current stage, thereby reducing the transmission efficiency of the common-mode signal.

2 and 5 , the phase adjustment unit 300 includes a first signal amplifier 310 and a second signal amplifier 320. The first signal amplifier 310 and the second signal amplifier 320 are used to shift the phase of the common mode signal output by the edge adjustment unit 100 and the waveform shaping unit 200 of the duty cycle adjustment module 10 of the previous stage by 180°, and to be in phase with the common mode signal of the duty cycle adjustment module 10 of the current stage, and the two common mode signals are summed in phase at the edge adjustment unit 100 of the duty cycle adjustment module 10 of the current stage. The input end of the first signal amplifier 310 is connected to the first output end of the waveform shaping unit 200, and the input end of the second signal amplifier 320 is connected to the second output end of the waveform shaping unit 200.

When the phase adjustment unit 300 is connected to two output ends of the waveform shaping unit 200, if the first input end signal of the waveform shaping unit 200 is Vinp, the second input end signal of the waveform shaping unit 200 is Vinm, the first output end signal of the phase adjustment unit 300 is Voutm, and the second output end signal of the phase adjustment unit 300 is Voutp, the relationship between the input signal and the output signal is as follows: Formulas 7 and 8:

Among them, gm_buffer5 is the transconductance of the first signal amplifier 310 , gds_buffer5 is the output admittance of the first signal amplifier 310 , and the transconductance and output admittance of the second signal amplifier 320 are the same as the transconductance and output admittance of the first signal amplifier 310 .

From equations 7 and 8, it can be obtained that the phase of the common-mode signal is shifted by 180° relative to equation 2, and the gain amplitude increases the intrinsic gain of an inverter. The phase of the differential-mode signal does not change, and the gain amplitude also increases the intrinsic gain of an inverter. Combining equations 1 and 9, the common-mode signal of the output node of the edge adjustment unit 100 of the second stage in the duty cycle adjustment module 10 chain can be obtained as the following equation 9:

It can be seen from Formula 9 that when the phase adjustment unit 300 is not set, the common-mode signal of the previous stage of the cascade link of the duty cycle adjustment module 10 will be summed in anti-phase at the current stage, reducing the transmission efficiency of the common-mode signal. After the phase adjustment unit 300 is set, the common-mode signal of the previous stage will be summed in phase with the input common-mode signal at the current stage, thereby improving the common-mode gain, improving the transmission efficiency of the common-mode signal, and reducing the voltage margin overhead in the common-mode link.

It should be noted that a phase adjustment unit 300 may be provided at the output end of the waveform shaping unit 200 so that the edge adjustment unit 100 of the duty cycle adjustment module 10 of the previous stage and the waveform shaping unit 200 output common mode signals, and the two common mode signals are summed in phase at the edge adjustment unit 100 of the duty cycle adjustment module 10 of the current stage, but the present invention is not limited thereto. The gain of the first latch 230 and the second latch 240 in the waveform shaping unit 200 may also be reduced to increase the common mode gain of the link, and the specific situation may depend on the situation.

The gain of the first latch 230 and the second latch 240 in the waveform shaping unit 200 is reduced so that , the input signal Vincm of the second-stage duty cycle adjustment unit is in phase with the feedback signal Vdccm. At this time, equation 6 will be rewritten as the following equation 10:

It can be seen from formula 10 that the common mode signal of the edge adjustment unit 100 of the duty cycle adjustment module 10 of the previous stage and the common mode signal of the edge adjustment unit 100 of the duty cycle adjustment module 10 of the current stage will also be summed in phase, thereby improving the common mode gain of the link in the step-by-step superposition.

It should be noted that after the phase adjustment unit 300 is set, the common mode signal of the previous stage will be summed with the input common mode signal in phase at the current stage, thereby improving the common mode gain, and at the same time, the gain of the first latch 230 and the second latch 240 in the waveform shaping unit 200 can be improved, so that , to avoid the latch gain reduction affecting the differential mode gain.

In some embodiments, the first signal amplifier 310 and the second signal amplifier 320 include inverting buffers.

It should be noted that the first signal amplifier 310 and the second signal amplifier 320 may be inverting buffers, but are not limited thereto. The first signal amplifier 310 and the second signal amplifier 320 may be inverting buffers or push-pull common source amplifiers, depending on the specific situation.

When the first signal amplifier 310 and the second signal amplifier 320 are inverting buffers, the structures thereof may be the same as those of the first buffer 210 and the second buffer 220 , thereby simplifying the circuit structure.

2 and 6 , the phase adjustment unit 300 includes a first signal amplifier 310 and a second signal amplifier 320. The first signal amplifier 310 and the second signal amplifier 320 are used to shift the phase of the common mode signal output by the edge adjustment unit 100 of the duty cycle adjustment module 10 of the previous stage by 180°, and make it in phase with the common mode signal of the duty cycle adjustment module 10 of the current stage. The two common mode signals are summed in phase at the edge adjustment unit 100 of the duty cycle adjustment module 10 of the current stage. The input end of the first signal amplifier 310 is connected to the output end of the first edge adjustment unit 100a, the output end of the first signal amplifier 310 is connected to the first input end of the waveform shaping unit 200, the input end of the second signal amplifier 320 is connected to the output end of the second edge adjustment unit 100b, and the output end of the second signal amplifier 320 is connected to the second input end of the waveform shaping unit 200.

The phase adjustment unit 300 is arranged between the duty cycle adjustment module 10 and the waveform shaping unit 200. Compared with the case where the phase adjustment unit 300 is arranged after the waveform shaping unit 200, the calculation formulas for the common-mode signal and the differential-mode signal are the same, that is, the phase adjustment unit 300 is arranged between the duty cycle adjustment module 10 and the waveform shaping unit 200, which can also increase the common-mode gain of multiple cascaded duty cycle adjustment modules 10, thereby improving the transmission efficiency of the common-mode signal and the precision and accuracy of signal transmission.

When the phase adjustment unit 300 is disposed between the duty cycle adjustment module 10 and the waveform shaping unit 200 , the first signal amplifier 310 and the second signal amplifier 320 include an inverting buffer or a push-pull common source amplifier.

When the first signal amplifier 310 and the second signal amplifier 320 are inverting buffers, the structures thereof may be the same as those of the first buffer 210 and the second buffer 220 , thereby simplifying the circuit structure.

In some embodiments, the duty cycle correction circuit also includes a detection module and a judgment module. The detection module is used to detect whether the duty cycle of the clock signal is distorted. The judgment module connects the detection module and the first-stage duty cycle adjustment module 10. The judgment module outputs a feedback signal Vdcc reflecting the degree of duty cycle distortion to the feedback signal input terminal.

The duty cycle correction circuit also includes a detection module, a judgment module and a cascaded duty cycle adjustment module 10. The detection module detects whether the duty cycle of the clock signal is distorted. The judgment module outputs a feedback signal Vdcc reflecting the degree of duty cycle distortion according to the detection result of the detection module. The cascaded duty cycle adjustment module 10 corrects the duty cycle of the clock signal according to the feedback signal Vdcc, reduces or eliminates the distortion of the duty cycle, and ensures the accuracy of signal transmission.

The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims (10)

1. A duty cycle correction circuit comprising a plurality of cascaded duty cycle adjustment modules, the duty cycle adjustment modules comprising:

The edge adjusting unit comprises a clock signal input end, a feedback signal input end and a clock signal output end, and adjusts rising edge time or falling edge time of a signal of the clock signal input end according to the signal of the feedback signal input end to generate a signal of the clock signal output end;

The waveform shaping unit is connected with the clock signal output ends of the two edge adjusting units and is used for shortening the rising edge time and the falling edge time of the signals of the clock signal output ends;

And the phase adjusting unit is connected between the edge adjusting unit and the waveform shaping unit or connected with two output ends of the waveform shaping unit and is at least used for adjusting the phase of the common mode signal output by the edge adjusting unit or the phase of the common mode signal output by the edge adjusting unit and the waveform shaping unit, so as to increase the common mode gains of a plurality of cascaded duty ratio adjusting modules.

2. The duty cycle correction circuit of claim 1, wherein the edge adjustment unit includes a first adjustment unit and a second adjustment unit, an input terminal of the first adjustment unit and an input terminal of the second adjustment unit are the clock signal input terminals, an output terminal of the first adjustment unit and an output terminal of the second adjustment unit are the clock signal output terminals, a control terminal of the first adjustment unit is the feedback signal input terminal, and the first adjustment unit adjusts a signal of the clock signal input terminal and outputs the signal to the clock signal output terminal according to a signal of the feedback signal input terminal.

3. The duty cycle correction circuit of claim 2, wherein the first adjustment unit comprises a first transistor, a second transistor, and a first inverter, the second adjustment unit comprises a second inverter, the first transistor is a P-channel field effect transistor, the second transistor is an N-channel field effect transistor, the control terminal of the first transistor and the control terminal of the second transistor are the control terminals of the first adjustment unit, the first terminal of the first transistor is connected to a first power supply, the second terminal of the first transistor is connected to a first power supply terminal of the first inverter, the first terminal of the second transistor is connected to a second power supply, the second terminal of the second transistor is connected to a second power supply terminal of the first inverter, the input terminal of the first inverter is an input terminal of the first adjustment unit, the output terminal of the first inverter is an output terminal of the first adjustment unit, the second terminal of the second transistor is connected to a second power supply terminal of the second inverter, and the second input terminal of the second inverter is connected to the second power supply terminal of the second adjustment unit, respectively.

4. The duty cycle correction circuit of claim 3, wherein the first inverter comprises a third transistor and a fourth transistor, the third transistor is a P-channel field effect transistor, the fourth transistor is an N-channel field effect transistor, a control terminal of the third transistor and a control terminal of the fourth transistor are input terminals of the first inverter, a first terminal of the third transistor is connected to the first transistor, a second terminal of the third transistor and a second terminal of the fourth transistor are output terminals of the first inverter, and a first terminal of the fourth transistor is connected to the second transistor;

The second inverter comprises a fifth transistor and a sixth transistor, the fifth transistor is a P-channel field effect transistor, the sixth transistor is an N-channel field effect transistor, a control end of the fifth transistor and a control end of the sixth transistor are input ends of the second inverter, a first end of the fifth transistor is connected with the first power supply end, a second end of the fifth transistor and a second end of the sixth transistor are output ends of the second inverter, and a first end of the sixth transistor is the second power supply end.

5. The duty cycle correction circuit of claim 4, wherein the waveform shaping unit comprises a first buffer, a second buffer, a first latch and a second latch, the first buffer and the second buffer comprise inverting buffers, an input of the first buffer is a first input of the waveform shaping unit, an input of the second buffer is a second input of the waveform shaping unit, the first buffer is connected with a first output of the waveform shaping unit sequentially through a first node and a second node, the second buffer is connected with a second output of the waveform shaping unit sequentially through a third node and a fourth node, an input and an output of the first latch are respectively connected with the first node and the third node, and an input and an output of the second latch are respectively connected with the fourth node and the second node.

6. The duty cycle correction circuit of any one of claims 1 to 5, wherein the phase adjustment unit includes a first signal amplifier and a second signal amplifier, the first signal amplifier and the second signal amplifier are used for shifting phases of common mode signals output by the edge adjustment unit and the waveform shaping unit of the duty cycle adjustment module of a previous stage by 180 degrees, the common mode signals are in phase with the common mode signals of the duty cycle adjustment module of a current stage, the two common mode signals are in phase and summed at the edge adjustment unit of the duty cycle adjustment module of the current stage, and an input end of the first signal amplifier is connected with a first output end of the waveform shaping unit, and an input end of the second signal amplifier is connected with a second output end of the waveform shaping unit.

7. The duty cycle correction circuit of claim 6, wherein the first signal amplifier and the second signal amplifier comprise inverting buffers or push-pull common source amplifiers.

8. The duty cycle correction circuit of any one of claims 1 to 5, wherein the phase adjustment unit includes a first signal amplifier and a second signal amplifier, the first signal amplifier and the second signal amplifier are configured to shift a phase of a common mode signal output by the edge adjustment unit of a previous stage by 180 ° and in phase with the common mode signal of the duty cycle adjustment module of a current stage, two common mode signals are summed in phase at the edge adjustment unit of the duty cycle adjustment module of the current stage, the two edge adjustment units include a first edge adjustment unit and a second edge adjustment unit, an input end of the first signal amplifier is connected to an output end of the first edge adjustment unit, an output end of the first signal amplifier is connected to a first input end of the waveform shaping unit, an input end of the second signal amplifier is connected to an output end of the second edge adjustment unit, and an output end of the second signal amplifier is connected to a second input end of the waveform shaping unit.

9. The duty cycle correction circuit of claim 8, wherein the first signal amplifier and the second signal amplifier comprise inverting buffers or push-pull common source amplifiers.

10. The duty cycle correction circuit of claim 1, further comprising a detection module for detecting whether a duty cycle of a clock signal is distorted, and a determination module coupled to the detection module and the duty cycle adjustment module of the first stage, the determination module outputting a feedback signal reflecting a degree of the duty cycle distortion to the feedback signal input.