CN118588773A - A cell structure for improving the UV attenuation resistance of a cell and a method for preparing the same - Google Patents

Abstract

The invention relates to the field of battery technology, and in particular to a battery cell structure and a preparation method thereof for improving the UV attenuation resistance of a battery cell; the structure comprises a single crystal silicon wafer, wherein a tunneling oxide layer, a first doping layer and a first anti-reflection layer are sequentially arranged at the bottom of the single crystal silicon wafer, and a second doping layer, a silicon dioxide passivation layer, an aluminum oxide field passivation layer and a first anti-reflection layer are sequentially arranged at the top of the single crystal silicon wafer; the invention provides four new processes for growing silicon oxide, namely, adding ozone gas in a drying tank, utilizing the strong oxidizing property of ozone, forming a silicon dioxide passivation layer on the surface of the silicon wafer during the drying process, or adding hydrogen peroxide to form a silicon dioxide passivation layer on the surface of the silicon wafer, or forming a silicon dioxide passivation layer on the surface of the silicon wafer in a wet oxygen environment, or adding ozone in a furnace tube to form a silicon dioxide passivation layer on the surface of the silicon wafer, thereby solving the UV attenuation problem of TOPcon battery cells and improving the UV resistance of the battery cells.

Description

A cell structure for improving the UV attenuation resistance of a cell and a method for preparing the same

Technical Field

The present invention relates to the technical field of batteries, and in particular to a battery cell structure capable of improving the UV attenuation resistance of a battery cell and a preparation method thereof.

Background Art

TOPCon cell technology, also known as tunneling oxide passivation contact cell technology, is a high-efficiency photovoltaic cell technology. The front surface of the cell is a boron-diffused emitter, using an Al ₂ O ₃ /SiN double-layer passivation film, a 1-2 nm tunneling oxide layer is prepared on the back, and then a layer of doped polysilicon is deposited. The two together form a passivation contact structure, providing good interface passivation for the back of the silicon wafer.

In the patent document with application number "CN202311520474.4" and titled "A double-sided tunneling passivation contact solar cell structure and its preparation method", it is recorded that "the structure includes a silicon substrate, and a front tunneling oxide layer, a first N-type doped polysilicon layer, an N-type doped silicon carbide layer and a front anti-reflection layer or a transparent conductive oxide film are arranged in the front non-metallized area thereof, and a front tunneling oxide layer, a first N-type doped polysilicon layer, an N-type doped silicon carbide layer, a second N-type doped polysilicon layer, a front anti-reflection layer or a transparent conductive oxide film and a front electrode are arranged in the front metallized area, and an ohmic contact is formed. In the present invention, a tunneling contact structure is constructed in the metallized area and the non-metallized area on the front of the battery, which can not only improve the front passivation effect, but also reduce the front parasitic absorption and improve the front optical utilization, thereby constructing a double-sided tunneling passivation contact battery structure with good passivation effect and high conversion efficiency, which is of great significance for realizing the wide application of TOPCon batteries."

Although the cell manufactured by the above patent document has advantages such as good front passivation effect, its UV resistance is relatively insufficient and still needs further improvement. Based on this, the present invention provides a cell structure and a preparation method for improving the UV attenuation resistance of the cell to solve the above technical problems.

Summary of the invention

The purpose of the present invention is to provide a cell structure and a preparation method thereof for improving the UV attenuation resistance of the cell, provide four new processes for growing silicon oxide, solve the UV attenuation problem of TOPcon cells, and improve the UV resistance of the cells.

To achieve the above object, the present invention provides the following technical solutions:

The first aspect of the present invention provides a cell structure for improving the UV attenuation resistance of a cell, comprising a monocrystalline silicon wafer, wherein a tunneling oxide layer, a first doping layer and a first anti-reflection layer are sequentially arranged at the bottom of the monocrystalline silicon wafer, and a second doping layer, a silicon dioxide passivation layer, an aluminum oxide field passivation layer and a first anti-reflection layer are sequentially arranged at the top of the monocrystalline silicon wafer.

The present invention is further configured as follows: a conductive electrode is also provided on the single crystal silicon wafer.

The second aspect of the present invention is to provide a method for preparing the above-mentioned cell structure for improving the UV attenuation resistance of the cell, comprising the following steps:

S1. Soak the single crystal silicon wafer in a 70°C soaking solution in a texturing tank for 115 to 155 seconds, then take out the single crystal silicon wafer and place it in an alkaline sodium hydroxide solution with a concentration of 0.5 to 1.5% for 360 to 480 seconds to form a pyramid structure by anisotropic corrosion;

S2, using a high-temperature tubular diffusion furnace, diffusing boron trichloride for 80 to 120 minutes, and then passing oxygen at high temperature to form a second doping layer on the front surface of the single crystal silicon wafer;

S3, using 20-25% hydrofluoric acid to etch the back of the single crystal silicon wafer at room temperature, then using 3-7% sodium hydroxide to clean at 60-70°C for 3-7 minutes, and then alkaline polishing;

S4, depositing a tunneling oxide layer with a thickness of 1 to 3 nm on the back of the single crystal silicon wafer by plasma enhanced chemical vapor deposition (PECVD), and then depositing a mixed gas of silane, laughing gas and phosphine on the surface of the tunneling oxide layer for 10 minutes to form a first doped layer mixed with amorphous silicon;

S5, using a high temperature annealing furnace, annealing the obtained single crystal silicon wafer at an annealing temperature of 880 to 950° C. for 20 to 60 minutes;

S6, forming a silicon dioxide passivation layer on the single crystal silicon wafer;

S7, using atomic layer deposition (ALD) at a temperature of 200-300° C., reacting trimethylaluminum with a flow rate of 2000-4000 sccm and water with a flow rate of 2000-3000 sccm, depositing on the front side of the silicon wafer for 10 minutes to form an aluminum oxide field passivation layer, and then using PECVD deposition to form a first anti-reflection layer;

S8, using a plasma enhanced chemical vapor deposition (PECVD) method to form a first anti-reflection layer by using a mixed gas deposition method;

S9, and then sequentially undergoing silk screen sintering, light decay recovery and LECO sintering to obtain a cell structure containing a conductive electrode.

The present invention is further configured as follows: in step S1, the soaking liquid is formed by mixing sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340.

The present invention is further configured as follows: in step S1, the size of the pyramid velvet surface is 1.1-2.1 um, and the reflectivity is 8-12%.

The present invention is further configured as follows: in step S2, the flow rate of the boron trichloride is 150-350 sccm, the diffusion temperature is 850-950°C, the diffusion time is 25-35 min, the flow rate of the oxygen is 20000-30000 sccm, the high temperature is 1000-1060°C, and the high temperature treatment time is 100-150 min.

The present invention is further configured as follows: in step S2, the diffusion sheet resistance of the first anti-reflection layer is 260-550Ω/sqr.

The present invention is further configured as follows: in step S3, the alkali polishing reduces weight by 0.14 to 0.26 g, the reflectivity is 38% to 48%, and the tower base size is 2 to 14 um.

The present invention is further configured as follows: in the step S4, the thickness of the first doping layer is 90-130 nm.

The present invention is further configured as follows: in step S5, the annealing square resistance is 35-75Ω.

The present invention is further configured as follows: in step S6, the process of forming the silicon dioxide passivation layer is as follows:

Use hydrofluoric acid with a concentration of 25-35% to etch the front side of the single crystal silicon wafer at room temperature, and then use sodium hydroxide with a concentration of 3-7% and hydrofluoric acid with a concentration of 25-35% to remove the residue on the front side of the single crystal silicon wafer;

Ozone gas is introduced into the cleaning and drying tank, and the strong oxidizing property of the ozone gas is utilized to react on the surface of the single crystal silicon wafer to form a silicon dioxide passivation layer during the drying process;

The ozone gas flow rate is 300 to 700 sccm, and the time is 5 to 15 minutes;

The thickness of the silicon dioxide passivation layer is 0.3-1.5 nm.

The present invention is further configured as follows: the cleaning and drying tank is a drying tank for an RCA process.

The present invention is further configured as follows: in step S6, the process of forming the silicon dioxide passivation layer is as follows:

Use hydrofluoric acid with a concentration of 25-35% to etch the front side of the single crystal silicon wafer at room temperature, and then use sodium hydroxide with a concentration of 3-7% and hydrofluoric acid with a concentration of 25-35% to remove the residue on the front side of the single crystal silicon wafer;

Then, the silicon wafer is treated with 30% hydrogen peroxide for 12 to 18 minutes and dried to form a silicon dioxide passivation layer on the surface of the single crystal silicon wafer.

The thickness of the silicon dioxide passivation layer is 0.3-1.5 nm.

The present invention is further configured as follows: the hydrogen peroxide treatment is to place the hydrogen peroxide in the slow pull tank of the RCA process to treat the single crystal silicon wafer for 12 to 18 minutes.

The present invention is further configured as follows: in step S6, the process of forming the silicon dioxide passivation layer is as follows:

Use hydrofluoric acid with a concentration of 25-35% to etch the front side of the single crystal silicon wafer at room temperature, and then use sodium hydroxide with a concentration of 3-7% and hydrofluoric acid with a concentration of 25-35% to remove the residue on the front side of the single crystal silicon wafer;

After drying, the wafer is placed in a wet oxygen environment at a humidity of 40 to 60% for 6 to 24 hours to form a silicon dioxide passivation layer on the surface of the single crystal silicon wafer;

The thickness of the silicon dioxide passivation layer is 0.3-1.5 nm.

The present invention is further configured as follows: in step S6, the process of forming the silicon dioxide passivation layer is as follows:

Use hydrofluoric acid with a concentration of 25-35% to etch the front side of the single crystal silicon wafer at room temperature, and then use sodium hydroxide with a concentration of 3-7% and hydrofluoric acid with a concentration of 25-35% to remove the residue on the front side of the single crystal silicon wafer;

Ozone is introduced into the furnace tube, and the treatment is carried out for 2 to 8 minutes at a temperature of 210 to 310° C. and a flow rate of 4000 to 6000 sccm to form a silicon dioxide passivation layer on the surface of the single crystal silicon wafer;

The thickness of the silicon dioxide passivation layer is 0.3-1.5 nm.

The present invention is further configured as follows: the furnace tube is a positive film alumina process furnace tube.

The present invention is further configured as follows: in step S7, the thickness of the aluminum oxide field passivation layer is 6-14 nm.

The present invention is further configured as follows: in the step S7, the thickness of the second anti-reflection layer is 65-85 nm, and the refractive index is 1.98%-2.14%.

The present invention is further configured as follows: in the step S8, the flow rate of silane in the mixed gas for forming the first anti-reflection layer is 2000-3000 sccm, the flow rate of nitrous oxide is 8000-10000 sccm, and the flow rate of ammonia is 9900-10500 sccm, and the time is 20 minutes.

The present invention is further configured as follows: in the step S8, the thickness of the first anti-reflection layer is 70-90 nm, and the reflectivity is 2.01-2.17%.

The present invention is further configured as follows: in step S9, screen-printed silver (Ag)/silver aluminum (Ag/Al) metal electrodes are used to collect current; the slurry on the silicon wafer is dried to burn out the organic components of the slurry so that the slurry and the silicon wafer form a good ohmic contact.

The present invention is further configured as follows: in the step S10, the light decay recovery is to activate the H in the SiNx film and reduce the H-X recombination in the silicon wafer by continuous illumination at a high temperature of 800°C for 2 minutes.

The present invention is further configured as follows: in the step S11, LECO sintering utilizes high-intensity laser irradiation of the cell to excite charge carriers, and simultaneously applies a deflection voltage of 10V or more, thereby generating a local current of several amperes, and sintering occurs at the corresponding location to induce mutual diffusion of silver paste and silicon, which will significantly reduce the contact resistance between the metal and the semiconductor.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention provides four new process methods for growing silicon oxide, namely, adding ozone gas in a drying tank, utilizing the strong oxidizing property of ozone to form a silicon dioxide passivation layer on the surface of a silicon wafer during the drying process, or adding hydrogen peroxide to form a silicon dioxide passivation layer on the surface of a silicon wafer, or forming a silicon dioxide passivation layer on the surface of a silicon wafer in a wet oxygen environment, or adding ozone in a furnace tube to form a silicon dioxide passivation layer on the surface of a silicon wafer, thereby solving the UV attenuation problem of TOPcon cells and improving the UV resistance of the cells. The cell structure and preparation method thereof for improving the UV attenuation resistance of cells provided by the present invention have broader market prospects and are more suitable for promotion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a cell structure for improving the UV attenuation resistance of a cell.

Legend: 100, single crystal silicon wafer; 200, tunneling oxide layer; 300, first doping layer; 400, first anti-reflection layer; 500, second doping layer; 600, silicon dioxide passivation layer; 700, aluminum oxide field passivation layer; 800, second anti-reflection layer; 900, conductive electrode.

DETAILED DESCRIPTION

The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Example 1

As shown in FIG1 , the present embodiment provides a cell structure for improving the UV attenuation resistance of a cell, including a monocrystalline silicon wafer 100, wherein a tunneling oxide layer 200, a first doping layer 300 and a first anti-reflection layer 400 are sequentially arranged at the bottom of the monocrystalline silicon wafer 100, and a second doping layer 500, a silicon dioxide passivation layer 600, an aluminum oxide field passivation layer 700 and a second anti-reflection layer 800 are sequentially arranged at the top of the monocrystalline silicon wafer 100.

A conductive electrode 900 is also disposed on the single crystal silicon wafer 100 .

In addition, the second anti-reflection layer 800 is an anti-reflection SiN layer;

The aluminum oxide field passivation layer 700 is an Al ₂ O ₃ aluminum oxide field passivation layer;

The silicon dioxide passivation layer 600 is a SiO ₂ chemical passivation layer;

The second doping layer 500 is a P-type B doping layer;

The single crystal silicon wafer 100 is an N-type single crystal silicon wafer;

The tunneling oxide layer 200 is a SiO ₂ tunneling oxide layer;

The first doped layer 300 is an N-type P-doped layer;

The first anti-reflection layer 400 is a SIN anti-reflection layer;

The conductive electrode 900 is a Ag conductive electrode, and forms an ohmic contact with the first anti-reflection layer 400 .

In addition, this embodiment also provides a method for preparing the above-mentioned cell structure for improving the UV attenuation resistance of the cell, comprising the following steps:

S1. Soak the single crystal silicon wafer 100 in a 70°C soaking solution in a texturing tank for 115 seconds, then take out the single crystal silicon wafer 100 and place it in an alkaline sodium hydroxide solution with a concentration of 0.5% for 360 to 480 seconds to form a pyramid structure by anisotropic corrosion.

The soaking liquid is a mixture of sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340.

The size of the pyramid velvet is 1.1um and the reflectivity is 8%.

S2, using a high-temperature tubular diffusion furnace, diffusing boron trichloride for 80 minutes, and then passing oxygen at high temperature to form a second doping layer 500 on the front surface of the single crystal silicon wafer 100,

Among them, the flow rate of boron trichloride is 150sccm, the diffusion temperature is 850°C, the diffusion time is 25min, the flow rate of oxygen is 20000sccm, the high temperature temperature is 1000°C, and the high temperature treatment time is 100min.

S3, etching the back side of the single crystal silicon wafer 100 with hydrofluoric acid having a concentration of 20% at room temperature, then cleaning with sodium hydroxide having a concentration of 3% at 60° C. for 3 minutes, and then alkaline polishing;

S4, depositing a tunnel oxide layer 200 with a thickness of 1 nm on the back side of the single crystal silicon wafer 100 by plasma enhanced chemical vapor deposition (PECVD), and then depositing a mixed gas of silane (SiH ₄ ), nitrous oxide (N ₂ O) and phosphine (PH ₃ ) on the surface of the tunnel oxide layer 200 for 10 minutes to form a first doped layer 300 mixed with amorphous silicon and P doping;

S5, using a high temperature annealing furnace, annealing the obtained single crystal silicon wafer 100 at an annealing temperature of 880° C. for 20 minutes;

S6 , forming a silicon dioxide passivation layer 600 on the single crystal silicon wafer 100 .

The process of forming the silicon dioxide passivation layer 600 is as follows:

Using 25% hydrofluoric acid to etch the front side of the single crystal silicon wafer 100 at room temperature, and then using 3% sodium hydroxide and 25% hydrofluoric acid to remove the residue on the front side of the single crystal silicon wafer 100;

Ozone gas is introduced into the cleaning and drying tank, and the strong oxidizing property of the ozone gas is utilized to react on the surface of the single crystal silicon wafer 100 to form a silicon dioxide passivation layer 600 during the drying process;

The ozone gas flow rate is 300 sccm and the time is 5 minutes.

S7, using atomic layer deposition (ALD) at a temperature of 200° C., reacting trimethylaluminum with a flow rate of 2000 sccm and water with a flow rate of 2000 sccm, and depositing on the front side of the silicon wafer for 10 minutes to form an aluminum oxide field passivation layer 700, and then using PECVD deposition to form a second anti-reflection layer 800;

S8. Using plasma enhanced chemical vapor deposition (PECVD) to form a first anti-reflection layer 400 using mixed gas deposition.

The mixed gas used to form the first anti-reflection layer 400 has a flow rate of silane (SiH ₄ ) of 2000 sccm, a flow rate of nitrous oxide (N ₂ O) of 8000 sccm, and a flow rate of ammonia (NH ₃ ) of 9900 sccm, and the time is 20 minutes.

S9, and then sequentially undergoing silk screen sintering, light decay recovery and LECO sintering to obtain a cell structure containing a conductive electrode 900.

Example 2

As shown in FIG1 , the present embodiment provides a cell structure for improving the UV attenuation resistance of a cell, including a monocrystalline silicon wafer 100, wherein a tunneling oxide layer 200, a first doping layer 300 and a first anti-reflection layer 400 are sequentially arranged at the bottom of the monocrystalline silicon wafer 100, and a second doping layer 500, a silicon dioxide passivation layer 600, an aluminum oxide field passivation layer 700 and a second anti-reflection layer 800 are sequentially arranged at the top of the monocrystalline silicon wafer 100.

A conductive electrode 900 is also disposed on the single crystal silicon wafer 100 .

In addition, the second anti-reflection layer 800 is an anti-reflection SiN layer;

The aluminum oxide field passivation layer 700 is an Al ₂ O ₃ aluminum oxide field passivation layer;

The silicon dioxide passivation layer 600 is a SiO ₂ chemical passivation layer;

The second doped layer 500 is a P-type B doped layer;

The single crystal silicon wafer 100 is an N-type single crystal silicon wafer;

The tunneling oxide layer 200 is a SiO ₂ tunneling oxide layer;

The first doped layer 300 is an N-type P-doped layer;

The first anti-reflection layer 400 is a SIN anti-reflection layer;

The conductive electrode 900 is a Ag conductive electrode, and forms an ohmic contact with the first anti-reflection layer 400 .

In addition, this embodiment also provides a method for preparing the above-mentioned cell structure for improving the UV attenuation resistance of the cell, comprising the following steps:

S1. Soak the single crystal silicon wafer 100 in a 70°C soaking solution in a texturing tank for 125 seconds, then take out the single crystal silicon wafer 100 and place it in an alkaline sodium hydroxide solution with a concentration of 0.7% for 380 seconds to form a pyramid structure by anisotropic corrosion.

The soaking liquid is a mixture of sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340.

The size of the pyramid velvet is 1.4um and the reflectivity is 9%.

S2, using a high-temperature tubular diffusion furnace, diffusing boron trichloride for 90 minutes, and then passing oxygen at high temperature to form a second doping layer 500 on the front surface of the single crystal silicon wafer 100,

Among them, the flow rate of boron trichloride is 200 sccm, the diffusion temperature is 860°C, the diffusion time is 27 minutes, the flow rate of oxygen is 25000 sccm, the high temperature temperature is 1020°C, and the high temperature treatment time is 110 minutes.

S3, etching the back side of the single crystal silicon wafer 100 with hydrofluoric acid having a concentration of 21% at room temperature, then cleaning with sodium hydroxide having a concentration of 3% at 62° C. for 4 minutes, and then alkaline polishing;

S4, depositing a tunnel oxide layer 200 with a thickness of 2 nm on the back side of the single crystal silicon wafer 100 by plasma enhanced chemical vapor deposition (PECVD), and then depositing a mixed gas of silane (SiH ₄ ), nitrous oxide (N ₂ O) and phosphine (PH ₃ ) on the surface of the tunnel oxide layer 200 for 10 minutes to form a first doped layer 300 mixed with amorphous silicon and P doping;

S5, using a high temperature annealing furnace, annealing the obtained single crystal silicon wafer 100 at an annealing temperature of 890° C. for 30 minutes;

S6 , forming a silicon dioxide passivation layer 600 on the single crystal silicon wafer 100 .

The process of forming the silicon dioxide passivation layer 600 is as follows:

Using hydrofluoric acid with a concentration of 28% to etch the front side of the single crystal silicon wafer 100 at room temperature, and then using sodium hydroxide with a concentration of 4% and hydrofluoric acid with a concentration of 28% to remove the residue on the front side of the single crystal silicon wafer 100;

Then, the single crystal silicon wafer 100 is treated with 30% hydrogen peroxide for 13 minutes and dried to form a silicon dioxide passivation layer 600 on the surface of the single crystal silicon wafer 100;

The thickness of the silicon dioxide passivation layer 600 is 0.4 nm.

S7, using atomic layer deposition (ALD) at a temperature of 210° C., reacting trimethylaluminum with a flow rate of 2500 sccm and water with a flow rate of 2500 sccm, and depositing on the front side of the silicon wafer for 10 minutes to form an aluminum oxide field passivation layer 700, and then using PECVD deposition to form a second anti-reflection layer 800;

S8. Using plasma enhanced chemical vapor deposition (PECVD) to form a first anti-reflection layer 400 using mixed gas deposition.

The mixed gas used to form the first anti-reflection layer 400 has a flow rate of silane (SiH ₄ ) of 2500 sccm, a flow rate of nitrous oxide (N ₂ O) of 9000 sccm, and a flow rate of ammonia (NH ₃ ) of 10000 sccm, and the time is 20 minutes.

S9, and then sequentially undergoing silk screen sintering, light decay recovery and LECO sintering to obtain a cell structure containing a conductive electrode 900.

Example 3

As shown in FIG1 , the present embodiment provides a cell structure for improving the UV attenuation resistance of a cell, including a monocrystalline silicon wafer 100, wherein a tunneling oxide layer 200, a first doping layer 300 and a first anti-reflection layer 400 are sequentially arranged at the bottom of the monocrystalline silicon wafer 100, and a second doping layer 500, a silicon dioxide passivation layer 600, an aluminum oxide field passivation layer 700 and a second anti-reflection layer 800 are sequentially arranged at the top of the monocrystalline silicon wafer 100.

A conductive electrode 900 is also disposed on the single crystal silicon wafer 100 .

In addition, the second anti-reflection layer 800 is an anti-reflection SiN layer;

The aluminum oxide field passivation layer 700 is an Al ₂ O ₃ aluminum oxide field passivation layer;

The silicon dioxide passivation layer 600 is a SiO ₂ chemical passivation layer;

The second doping layer 500 is a P-type B doping layer;

The single crystal silicon wafer 100 is an N-type single crystal silicon wafer;

The tunneling oxide layer 200 is a SiO ₂ tunneling oxide layer;

The first doped layer 300 is an N-type P-doped layer;

The first anti-reflection layer 400 is a SIN anti-reflection layer;

The conductive electrode 900 is a Ag conductive electrode, and forms an ohmic contact with the first anti-reflection layer 400 .

In addition, this embodiment also provides a method for preparing the above-mentioned cell structure for improving the UV attenuation resistance of the cell, comprising the following steps:

S1. Soak the single crystal silicon wafer 100 in a 70°C soaking solution in a texturing tank for 135 seconds, then take out the single crystal silicon wafer 100 and place it in a 1% alkaline sodium hydroxide solution for 360 to 480 seconds to form a pyramid structure by anisotropic corrosion.

The soaking liquid is a mixture of sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340.

The size of the pyramid velvet is 1.6um and the reflectivity is 10%.

S2, using a high-temperature tubular diffusion furnace, diffusing boron trichloride for 100 minutes, and then passing oxygen at high temperature to form a second doping layer 500 on the front surface of the single crystal silicon wafer 100,

Among them, the flow rate of boron trichloride is 250sccm, the diffusion temperature is 900°C, the diffusion time is 30min, the flow rate of oxygen is 25000sccm, the high temperature temperature is 1030°C, and the high temperature treatment time is 120min.

S3, etching the back side of the single crystal silicon wafer 100 at room temperature using hydrofluoric acid having a concentration of 22%, then cleaning it at 65° C. for 5 minutes using sodium hydroxide having a concentration of 5%, and then alkaline polishing;

S4, depositing a tunnel oxide layer 200 with a thickness of 2 nm on the back side of the single crystal silicon wafer 100 by plasma enhanced chemical vapor deposition (PECVD), and then depositing a mixed gas of silane (SiH ₄ ), nitrous oxide (N ₂ O) and phosphine (PH ₃ ) on the surface of the tunnel oxide layer 200 for 10 minutes to form a first doped layer 300 mixed with amorphous silicon and P doping;

S5, using a high temperature annealing furnace, annealing the obtained single crystal silicon wafer 100 at an annealing temperature of 915° C. for 40 minutes;

S6 , forming a silicon dioxide passivation layer 600 on the single crystal silicon wafer 100 .

The process of forming the silicon dioxide passivation layer 600 is as follows:

Using 30% hydrofluoric acid to etch the front side of the single crystal silicon wafer 100 at room temperature, and then using 5% sodium hydroxide and 30% hydrofluoric acid to remove the residue on the front side of the single crystal silicon wafer 100;

After drying, the single crystal silicon wafer 100 is placed in a wet oxygen environment with a humidity of 50% for 15 hours to form a silicon dioxide passivation layer 600 on the surface of the single crystal silicon wafer 100;

The thickness of the silicon dioxide passivation layer 600 is 0.5 nm.

S7, using atomic layer deposition (ALD) at a temperature of 250° C., reacting trimethylaluminum with a flow rate of 3000 sccm and water with a flow rate of 2500 sccm, and depositing on the front side of the silicon wafer for 10 minutes to form an aluminum oxide field passivation layer 700, and then using PECVD deposition to form a second anti-reflection layer 800;

S8. Using plasma enhanced chemical vapor deposition (PECVD) to form a first anti-reflection layer 400 using mixed gas deposition.

The mixed gas used to form the first anti-reflection layer 400 has a flow rate of silane (SiH ₄ ) of 2500 sccm, a flow rate of nitrous oxide (N ₂ O) of 9000 sccm, and a flow rate of ammonia (NH ₃ ) of 9900-10500 sccm, and the time is 20 minutes.

S9, and then sequentially undergoing silk screen sintering, light decay recovery and LECO sintering to obtain a cell structure containing a conductive electrode 900.

Example 4

As shown in FIG1 , the present embodiment provides a cell structure for improving the UV attenuation resistance of a cell, including a monocrystalline silicon wafer 100, wherein a tunneling oxide layer 200, a first doping layer 300 and a first anti-reflection layer 400 are sequentially arranged at the bottom of the monocrystalline silicon wafer 100, and a second doping layer 500, a silicon dioxide passivation layer 600, an aluminum oxide field passivation layer 700 and a second anti-reflection layer 800 are sequentially arranged at the top of the monocrystalline silicon wafer 100.

A conductive electrode 900 is also disposed on the single crystal silicon wafer 100 .

In addition, the second anti-reflection layer 800 is an anti-reflection SiN layer;

The aluminum oxide field passivation layer 700 is an Al ₂ O ₃ aluminum oxide field passivation layer;

The silicon dioxide passivation layer 600 is a SiO ₂ chemical passivation layer;

The second doping layer 500 is a P-type B doping layer;

The single crystal silicon wafer 100 is an N-type single crystal silicon wafer;

The tunneling oxide layer 200 is a SiO ₂ tunneling oxide layer;

The first doped layer 300 is an N-type P-doped layer;

The first anti-reflection layer 400 is a SIN anti-reflection layer;

The conductive electrode 900 is a Ag conductive electrode, and forms an ohmic contact with the first anti-reflection layer 400 .

In addition, this embodiment also provides a method for preparing the above-mentioned cell structure for improving the UV attenuation resistance of the cell, comprising the following steps:

S1. Soak the single crystal silicon wafer 100 in a 70°C soaking solution in a texturing tank for 155 seconds, then take out the single crystal silicon wafer 100 and place it in an alkaline sodium hydroxide solution with a concentration of 1.5% for 480 seconds to form a pyramid structure by anisotropic corrosion.

The soaking liquid is a mixture of sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340.

The size of the pyramid velvet is 2.1um and the reflectivity is 12%.

S2, using a high-temperature tubular diffusion furnace, diffusing boron trichloride for 120 minutes, and then passing oxygen at high temperature to form a second doping layer 500 on the front surface of the single crystal silicon wafer 100,

Among them, the flow rate of boron trichloride is 350sccm, the diffusion temperature is 950°C, the diffusion time is 35min, the flow rate of oxygen is 30000sccm, the high temperature temperature is 1060°C, and the high temperature treatment time is 150min.

S3, etching the back side of the single crystal silicon wafer 100 with hydrofluoric acid having a concentration of 25% at room temperature, then cleaning with sodium hydroxide having a concentration of 7% at 70° C. for 7 minutes, and then alkaline polishing;

S4, depositing a tunnel oxide layer 200 with a thickness of 3 nm on the back side of the single crystal silicon wafer 100 by plasma enhanced chemical vapor deposition (PECVD), and then depositing a mixed gas of silane (SiH ₄ ), nitrous oxide (N ₂ O) and phosphine (PH ₃ ) on the surface of the tunnel oxide layer 200 for 10 minutes to form a first doped layer 300 mixed with amorphous silicon and P doping;

S5, using a high temperature annealing furnace, annealing the obtained single crystal silicon wafer 100 at an annealing temperature of 950° C. for 60 minutes;

S6 , forming a silicon dioxide passivation layer 600 on the single crystal silicon wafer 100 .

The process of forming the silicon dioxide passivation layer 600 is as follows:

Using 35% hydrofluoric acid to etch the front side of the single crystal silicon wafer 100 at room temperature, and then using 7% sodium hydroxide and 35% hydrofluoric acid to remove the residue on the front side of the single crystal silicon wafer 100;

Ozone is introduced into the furnace tube, and the treatment is carried out for 8 minutes at a temperature of 310° C. and a flow rate of 6000 sccm to form a silicon dioxide passivation layer 600 on the surface of the single crystal silicon wafer 100;

The thickness of the silicon dioxide passivation layer 600 is 1.5 nm.

S7, using atomic layer deposition (ALD) at a temperature of 300° C., reacting trimethylaluminum with a flow rate of 4000 sccm and water with a flow rate of 3000 sccm, and depositing on the front side of the silicon wafer for 10 minutes to form an aluminum oxide field passivation layer 700, and then using PECVD deposition to form a second anti-reflection layer 800;

S8. Using plasma enhanced chemical vapor deposition (PECVD) to form a first anti-reflection layer 400 using mixed gas deposition.

The mixed gas used to form the first anti-reflection layer 400 has a flow rate of silane (SiH ₄ ) of 3000 sccm, a flow rate of nitrous oxide (N ₂ O) of 10000 sccm, and a flow rate of ammonia (NH ₃ ) of 10500 sccm, and the time is 20 minutes.

S9, and then sequentially undergoing silk screen sintering, light decay recovery and LECO sintering to obtain a cell structure containing a conductive electrode 900.

Comparative Example 1: The difference from Example 1 is that in this example, ozone gas is not introduced into the cleaning and drying tank.

Comparative Example 2: The difference from Example 2 is that: in this example, the 30% hydrogen peroxide solution was not used for treatment for 13 minutes.

Comparative Example 3: The difference from Example 3 is that: in this example, the sample was not left to stand for 15 hours in a wet oxygen environment with a humidity of 50%.

Comparative Example 4: The difference from Example 4 is that in this example, ozone is not introduced into the furnace tube.

Performance test: The battery cell samples provided in Examples 1 to 4 and Comparative Examples 1 to 4 are marked as Examples 1 to 4 and Comparative Examples 1 to 4, respectively; and the relevant performances of the battery cells provided in Examples 1 to 4 and Comparative Examples 1 to 4 are tested as follows:

Test: After testing the cell efficiency Eta, place the cells in the MeiNeng Photovoltaic UV test box at the same time. According to the IEC (International Electrotechnical Commission) UV30 test standard, set the UV conditions: irradiation intensity 600w/ ^m2 , irradiation temperature 40℃, cumulative irradiation 30 kW·h. After the experiment is over, test the cell efficiency.

The obtained test data are recorded in Tables 1 to 4 below:

Table 1: Path 1 test results

Table 2: Path 2 test results

Table 3: Path 3 test results

Table 4: Path 4 test results

By comparing and analyzing the relevant data in Tables 1 to 4, it can be seen that the cell prepared by the present invention solves the UV attenuation problem of TOPcon cell, improves the UV resistance of the cell, and effectively guarantees its quality. This shows that the cell structure and preparation method for improving the UV attenuation resistance of the cell provided by the present invention have a broader market prospect and are more suitable for promotion.

In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. The utility model provides an improve battery piece structure of resistant UV decay performance of battery piece, its characterized in that includes monocrystalline silicon piece (100), tunneling oxide layer (200), first doped layer (300) and first antireflection layer (400) have been set gradually to the bottom of monocrystalline silicon piece (100), and monocrystalline silicon piece (100) top has set gradually second doped layer (500), silica passivation layer (600), alumina field passivation layer (700) and second antireflection layer (800).

2. The cell structure for improving the UV attenuation resistance of a cell according to claim 1, wherein a conductive electrode (900) is further provided on the monocrystalline silicon piece (100).

3. The preparation method of the battery piece structure for improving the UV attenuation resistance of the battery piece is characterized by comprising the following steps of:

s1, soaking a monocrystalline silicon wafer (100) in a soaking solution at 70 ℃ in a texturing groove for 115-155S, then taking out the monocrystalline silicon wafer (100), placing the monocrystalline silicon wafer in an alkaline sodium hydroxide solution with the concentration of 0.5-1.5% for 360-480S, and carrying out anisotropic etching to form a pyramid structure;

s2, using a high-temperature tube type diffusion furnace to diffuse boron trichloride for 80-120 min, and then introducing oxygen to form a second doping layer (500) on the front surface of the monocrystalline silicon wafer (100) at high temperature;

S3, etching the back surface of the monocrystalline silicon piece (100) at normal temperature by using hydrofluoric acid with the concentration of 20-25%, then cleaning for 3-7 min at the temperature of 60-70 ℃ by using sodium hydroxide with the concentration of 3-7%, and then performing alkali polishing;

S4, depositing a tunneling oxide layer (200) with the thickness of 1-3 nm on the back surface of the monocrystalline silicon wafer (100) by utilizing a plasma enhanced chemical vapor deposition PECVD mode, and then depositing mixed gas of silane, laughing gas and phosphane on the surface of the tunneling oxide layer (200) for 10min to form a first doped layer (300) mixed with amorphous silicon and P;

s5, annealing the monocrystalline silicon piece (100) for 20-60 min at the annealing temperature of 880-950 ℃ by adopting a high-temperature annealing furnace;

s6, forming a silicon dioxide passivation layer (600) on the monocrystalline silicon piece (100);

s7, utilizing an atomic layer deposition mode ALD to react trimethyl aluminum with the flow rate of 2000-4000 sccm and water with the flow rate of 2000-3000 sccm at the temperature of 200-300 ℃, depositing for 10min on the front surface of a silicon wafer to form an aluminum oxide field passivation layer (700), and then utilizing PECVD to deposit to form a second anti-reflection layer (800);

S8, forming a first anti-reflection layer (400) by adopting a plasma enhanced chemical vapor deposition PECVD mode through mixed gas deposition;

And S9, sequentially performing screen printing sintering, light attenuation recovery and LECO sintering to obtain the battery piece structure containing the conductive electrode (900).

4. The method for manufacturing a battery piece structure for improving UV attenuation resistance of a battery piece according to claim 3, wherein in the step S1, the soaking solution is prepared from sodium hydroxide, hydrogen peroxide and pure water according to a ratio of 1:6:340 by mass ratio.

5. The method of claim 3, wherein in the step S2, the flow rate of boron trichloride is 150-350 sccm, the diffusion temperature is 850-950 ℃, the diffusion time is 25-35 min, the flow rate of oxygen is 20000-30000 sccm, the high temperature is 1000-1060 ℃, and the high temperature treatment time is 100-150 min.

6. A method for manufacturing a battery cell structure for improving UV attenuation resistance of a battery cell according to claim 3, wherein in the step S6, the process of forming the silicon dioxide passivation layer (600) is as follows:

Etching the front surface of the monocrystalline silicon piece (100) at normal temperature by using hydrofluoric acid with the concentration of 25-35%, and removing front surface residues of the monocrystalline silicon piece (100) by using sodium hydroxide with the concentration of 3-7% and hydrofluoric acid with the concentration of 25-35%;

Ozone gas is introduced into the cleaning and drying groove, and a silicon dioxide passivation layer (600) is formed on the surface of the monocrystalline silicon wafer (100) in the drying process by utilizing the strong oxidizing property of the ozone gas;

wherein, the flow rate of the ozone gas is 300-700 sccm, and the time is 5-15 min;

the thickness of the silicon dioxide passivation layer (600) is 0.3-1.5 nm.

7. A method for manufacturing a battery cell structure for improving UV attenuation resistance of a battery cell according to claim 3, wherein in the step S6, the process of forming the silicon dioxide passivation layer (600) is as follows:

Etching the front surface of the monocrystalline silicon piece (100) at normal temperature by using hydrofluoric acid with the concentration of 25-35%, and removing front surface residues of the monocrystalline silicon piece (100) by using sodium hydroxide with the concentration of 3-7% and hydrofluoric acid with the concentration of 25-35%;

Then hydrogen peroxide with the concentration of 30% is used for treatment for 12-18 min, and a silicon dioxide passivation layer (600) is formed on the surface of the monocrystalline silicon wafer (100) after drying;

the thickness of the silicon dioxide passivation layer (600) is 0.3-1.5 nm.

8. A method for manufacturing a battery cell structure for improving UV attenuation resistance of a battery cell according to claim 3, wherein in the step S6, the process of forming the silicon dioxide passivation layer (600) is as follows:

Etching the front surface of the monocrystalline silicon piece (100) at normal temperature by using hydrofluoric acid with the concentration of 25-35%, and removing front surface residues of the monocrystalline silicon piece (100) by using sodium hydroxide with the concentration of 3-7% and hydrofluoric acid with the concentration of 25-35%;

After drying, standing for 6-24 hours under the condition that the humidity is 40-60% in a wet oxygen environment, and forming a silicon dioxide passivation layer (600) on the surface of the monocrystalline silicon wafer (100);

the thickness of the silicon dioxide passivation layer (600) is 0.3-1.5 nm.

9. A method for manufacturing a battery cell structure for improving UV attenuation resistance of a battery cell according to claim 3, wherein in the step S6, the process of forming the silicon dioxide passivation layer (600) is as follows:

Etching the front surface of the monocrystalline silicon piece (100) at normal temperature by using hydrofluoric acid with the concentration of 25-35%, and removing front surface residues of the monocrystalline silicon piece (100) by using sodium hydroxide with the concentration of 3-7% and hydrofluoric acid with the concentration of 25-35%;

Ozone is introduced into the furnace tube, the treatment is carried out for 2 to 8 minutes under the conditions that the temperature is 210 to 310 ℃ and the flow is 4000 to 6000sccm, and a silicon dioxide passivation layer (600) is formed on the surface of the monocrystalline silicon wafer (100);

the thickness of the silicon dioxide passivation layer (600) is 0.3-1.5 nm.

10. The method of claim 3, wherein in the step S8, the flow rate of silane in the mixed gas for forming the first anti-reflection layer (400) is 2000-3000 sccm, the flow rate of laughing gas is 8000-10000 sccm, and the flow rate of ammonia gas is 9900-10500 sccm, for 20min.